95 lines
2.1 KiB
Coq
95 lines
2.1 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// * Non-Disclosure Agreement (NDA). *
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// * *
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// *****************************************************************************
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// FILE NAME : sync.vp
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// AUTHOR : Tao Jiang
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// ORIGINAL TIME : 2017.06.02
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// FUNCTION : sync signal
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// :
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// :
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// :
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// RESET : Async reset
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// DFT :
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// DFP :
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// VERIFICATION :
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// RELEASE HISTORY :
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// *****************************************************************************
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// &ModuleBeg; @20
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module sync(
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fast_clk,
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in,
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out,
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pad_cpu_rst_b,
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slow_clk
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);
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// &Ports; @21
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input fast_clk;
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input in;
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input pad_cpu_rst_b;
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input slow_clk;
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output out;
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// &Regs; @22
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reg input_lv;
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reg reg_clr;
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// &Wires; @23
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wire fast_clk;
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wire in;
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wire input_vld;
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wire out;
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wire pad_cpu_rst_b;
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wire slow_clk;
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assign input_vld = in ;
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always@(posedge fast_clk or negedge pad_cpu_rst_b )
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begin
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if (!pad_cpu_rst_b)
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input_lv <= 1'b0;
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else if (input_vld)
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input_lv <= 1'b1;
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else if (reg_clr)
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input_lv <= 1'b0;
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end
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always@(posedge slow_clk or negedge pad_cpu_rst_b )
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begin
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if (!pad_cpu_rst_b)
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reg_clr <= 1'b0;
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else
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reg_clr <= 1'b1;
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end
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assign out = input_lv;
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// &ModuleEnd; @50
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endmodule
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