466 lines
13 KiB
Coq
466 lines
13 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module dahb_mem_ctrl(
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lite_mmc_hsel,
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lite_yy_haddr,
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lite_yy_hsize,
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lite_yy_htrans,
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lite_yy_hwdata,
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lite_yy_hwrite,
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mmc_lite_hrdata,
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mmc_lite_hready,
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mmc_lite_hresp,
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pad_biu_bigend_b,
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pad_cpu_rst_b,
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pll_core_cpuclk
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);
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// &Ports; @22
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input lite_mmc_hsel;
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input [31:0] lite_yy_haddr;
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input [2 :0] lite_yy_hsize;
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input [1 :0] lite_yy_htrans;
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input [31:0] lite_yy_hwdata;
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input lite_yy_hwrite;
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input pad_biu_bigend_b;
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input pad_cpu_rst_b;
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input pll_core_cpuclk;
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output [31:0] mmc_lite_hrdata;
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output mmc_lite_hready;
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output [1 :0] mmc_lite_hresp;
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// &Regs; @23
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reg [29:0] addr_holding;
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reg [3 :0] lite_mem_wen;
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reg lite_read_bypass;
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reg lite_read_bypass_vld;
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reg lite_read_stall;
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reg lite_read_stall_vld;
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reg [31:0] lite_wbuf_addr;
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reg [31:0] lite_wbuf_data;
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reg [2 :0] lite_wbuf_size;
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reg lite_write_req;
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reg lite_write_stall;
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// &Wires; @24
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wire lite_addr_hit;
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wire lite_addr_no_hit;
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wire [31:0] lite_bypass_data;
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wire [31:0] lite_mem_addr;
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wire lite_mem_cen;
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wire [31:0] lite_mem_din;
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wire [31:0] lite_mem_dout;
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wire lite_mmc_hsel;
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wire lite_read_addr_hit_with_bypass;
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wire lite_read_addr_hit_with_stall;
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wire lite_read_req;
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wire lite_wbuf_update;
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wire lite_write_cplt;
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wire lite_write_en;
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wire lite_write_req_en;
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wire lite_write_stall_en;
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wire [31:0] lite_yy_haddr;
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wire [2 :0] lite_yy_hsize;
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wire [31:0] lite_yy_hwdata;
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wire lite_yy_hwrite;
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wire [31:0] mmc_lite_hrdata;
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wire mmc_lite_hready;
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wire [1 :0] mmc_lite_hresp;
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wire pad_biu_bigend_b;
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wire pad_cpu_rst_b;
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wire pll_core_cpuclk;
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wire [7 :0] ram0_din;
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wire [7 :0] ram0_dout;
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wire [7 :0] ram1_din;
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wire [7 :0] ram1_dout;
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wire [7 :0] ram2_din;
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wire [7 :0] ram2_dout;
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wire [7 :0] ram3_din;
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wire [7 :0] ram3_dout;
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wire [7 :0] ram4_dout;
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wire [7 :0] ram5_dout;
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wire [7 :0] ram6_dout;
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wire [7 :0] ram7_dout;
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wire [29:0] ram_addr;
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wire ram_clk;
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wire [7 :0] ram_wen;
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parameter DMEM_WIDTH = 20;
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// &Force("nonport","lite_mem_addr"); @27
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// &Force("nonport","lite_mem_cen"); @28
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// &Force("nonport","lite_mem_din"); @29
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// &Force("nonport","lite_mem_dout"); @30
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// &Force("nonport","lite_mem_wen"); @31
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// &Force("input","lite_yy_htrans"); @32
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// &Force("bus", "lite_yy_htrans", 1, 0); @33
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// //&Force("nonport",""); @34
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// //&Force("nonport",""); @35
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// //&Force("nonport",""); @36
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// //&Force("nonport",""); @37
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// //&Force("nonport",""); @38
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// //&Force("nonport",""); @39
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// //&Force("nonport",""); @40
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//write buffer
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assign lite_wbuf_update = lite_yy_hwrite && lite_mmc_hsel;
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always @ (posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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lite_wbuf_addr[31:0] <= 32'b0;
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lite_wbuf_size[2:0] <= 3'b0;
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end
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else if (lite_wbuf_update)
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begin
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lite_wbuf_addr[31:0] <= lite_yy_haddr;
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lite_wbuf_size[2:0] <= lite_yy_hsize;
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end
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//else if (lite_write_cplt)
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//begin
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// lite_wbuf_addr[31:0] <= 32'b0;
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// lite_wbuf_size[2:0] <= 3'b0;
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//end
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end
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//write data
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always @ (posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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lite_wbuf_data[31:0] <= 32'b0;
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end
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else if (lite_write_req)
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begin
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lite_wbuf_data[31:0] <= lite_yy_hwdata[31:0];
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end
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end
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//read first and wirte will stall when address don't hit
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assign lite_write_stall_en = lite_write_req && lite_addr_no_hit && lite_read_req;
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always @ (posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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lite_write_stall <= 1'b0;
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end
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else if (lite_write_stall_en)
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begin
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lite_write_stall <= 1'b1;
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end
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else if (lite_write_cplt)
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begin
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lite_write_stall <=1'b0;
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end
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end
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//write request from bus interface
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assign lite_write_req_en = lite_yy_hwrite && lite_mmc_hsel;
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always @ (posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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lite_write_req <= 1'b0;
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end
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else if (lite_write_req_en)
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begin
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lite_write_req <= 1'b1;
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end
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else
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begin
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lite_write_req <= 1'b0;
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end
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end
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//read bypass and read stall
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always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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lite_read_bypass <= 1'b0;
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lite_read_stall <= 1'b0;
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end
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else
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begin
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lite_read_bypass <= lite_read_addr_hit_with_bypass;
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lite_read_stall <= lite_read_addr_hit_with_stall;
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end
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end
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//no read first and write request or write stall
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assign lite_write_en = ((lite_write_req | lite_write_stall) && (lite_addr_hit | (lite_yy_hwrite && lite_mmc_hsel) | ~lite_mmc_hsel));
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assign lite_bypass_data[31:0] = lite_wbuf_data[31:0];
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//write complete
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assign lite_write_cplt = (lite_write_req | lite_write_stall) && (lite_addr_hit | ~lite_mmc_hsel | (lite_yy_hwrite && lite_mmc_hsel));
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//read request
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assign lite_read_req = ~lite_yy_hwrite && lite_mmc_hsel;
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//address hit
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assign lite_addr_no_hit = (lite_yy_haddr[31:2] != lite_wbuf_addr[31:2]);
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assign lite_addr_hit = ~lite_addr_no_hit;
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//address hit and read will bypass
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assign lite_read_addr_hit_with_bypass = lite_read_req && (lite_write_req | lite_write_stall) && lite_addr_hit && lite_read_bypass_vld;
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//address hit but read will stall
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assign lite_read_addr_hit_with_stall = lite_read_req && (lite_write_req | lite_write_stall) && lite_addr_hit && lite_read_stall_vld;
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//read bypass or stall
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// &CombBeg; @140
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always @( lite_yy_haddr[1:0]
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or lite_wbuf_addr[1:0]
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or lite_wbuf_size[2:0]
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or lite_yy_hsize[2:0])
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begin
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casez({lite_wbuf_size[2:0],lite_yy_hsize[2:0],lite_wbuf_addr[1:0],lite_yy_haddr[1:0]})
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//st.b/ld.b
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10'b000_000_00_00,
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10'b000_000_01_01,
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10'b000_000_10_10,
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10'b000_000_11_11:
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begin
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lite_read_bypass_vld = 1'b1;
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lite_read_stall_vld = 1'b0;
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end
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//st.b/ld.h
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10'b000_001_??_??:
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begin
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lite_read_stall_vld = 1'b1;
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lite_read_bypass_vld = 1'b0;
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end
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//st.b/ld.w
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10'b000_010_??_??:
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begin
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lite_read_stall_vld = 1'b1;
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lite_read_bypass_vld = 1'b0;
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end
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//st.h/ld.b
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10'b001_000_0?_0?,
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10'b001_000_1?_1?:
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begin
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lite_read_bypass_vld = 1'b1;
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lite_read_stall_vld = 1'b0;
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end
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//st.h/ld.h
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10'b001_001_0?_0?,
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10'b001_001_1?_1?:
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begin
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lite_read_bypass_vld = 1'b1;
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lite_read_stall_vld = 1'b0;
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end
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//st.h/ld.w
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10'b001_010_??_??:
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begin
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lite_read_stall_vld = 1'b1;
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lite_read_bypass_vld = 1'b0;
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end
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//st.w/all lds
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10'b010_???_??_??:
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begin
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lite_read_bypass_vld = 1'b1;
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lite_read_stall_vld = 1'b0;
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end
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default:
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begin
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lite_read_bypass_vld = 1'b0;
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lite_read_stall_vld = 1'b0;
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end
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endcase
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// &CombEnd; @195
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end
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//memory select
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assign lite_mem_cen = ~(lite_read_req | lite_write_req | lite_write_stall);
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//memory write enable
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// &CombBeg; @202
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always @( lite_wbuf_addr[1:0]
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or lite_wbuf_size[2:0]
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or pad_biu_bigend_b
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or lite_write_en)
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begin
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case({pad_biu_bigend_b, lite_write_en, lite_wbuf_size[2:0], lite_wbuf_addr[1:0]})
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7'b0100000:
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begin
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lite_mem_wen[3:0] = 4'b0111;
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end
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7'b0100001:
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begin
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lite_mem_wen[3:0] = 4'b1011;
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end
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7'b0100010:
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begin
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lite_mem_wen[3:0] = 4'b1101;
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end
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7'b0100011:
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begin
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lite_mem_wen[3:0] = 4'b1110;
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end
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7'b0100100:
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begin
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lite_mem_wen[3:0] = 4'b0011;
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end
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7'b0100110:
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begin
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lite_mem_wen[3:0] = 4'b1100;
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end
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7'b0101000:
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begin
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lite_mem_wen[3:0] = 4'b0000;
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end
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7'b1100000:
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begin
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lite_mem_wen[3:0] = 4'b1110;
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end
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7'b1100001:
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begin
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lite_mem_wen[3:0] = 4'b1101;
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end
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7'b1100010:
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begin
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lite_mem_wen[3:0] = 4'b1011;
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end
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7'b1100011:
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begin
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lite_mem_wen[3:0] = 4'b0111;
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end
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7'b1100100:
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begin
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lite_mem_wen[3:0] = 4'b1100;
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end
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7'b1100110:
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begin
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lite_mem_wen[3:0] = 4'b0011;
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end
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7'b1101000:
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begin
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lite_mem_wen[3:0] = 4'b0000;
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end
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default:
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begin
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lite_mem_wen[3:0] = 4'b1111;
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end
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endcase
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// &CombEnd; @265
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||
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end
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||
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||
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assign lite_mem_addr[31:0] = (lite_write_en | lite_read_stall) ? lite_wbuf_addr[31:0] : lite_yy_haddr[31:0];
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assign lite_mem_din[31:0] = (lite_write_stall) ? lite_wbuf_data[31:0] : lite_yy_hwdata[31:0];
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assign mmc_lite_hrdata[31:0] = lite_read_bypass ? lite_bypass_data[31:0] : lite_mem_dout[31:0];
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assign mmc_lite_hready = !lite_read_stall;
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assign mmc_lite_hresp[1:0] = 2'b0;
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||
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||
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||
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//memory
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||
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always @(posedge pll_core_cpuclk)
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begin
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if(!lite_mem_cen)
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addr_holding[29:0] <= lite_mem_addr[31:2];
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end
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||
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assign ram_clk = pll_core_cpuclk;
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assign ram_addr[29:0] = lite_mem_cen ? addr_holding[29:0] : lite_mem_addr[31:2];
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assign ram_wen[0] = (!lite_mem_cen && !lite_mem_wen[0]) && !ram_addr[17];
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assign ram_wen[1] = (!lite_mem_cen && !lite_mem_wen[1]) && !ram_addr[17];
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assign ram_wen[2] = (!lite_mem_cen && !lite_mem_wen[2]) && !ram_addr[17];
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||
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assign ram_wen[3] = (!lite_mem_cen && !lite_mem_wen[3]) && !ram_addr[17];
|
||
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||
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assign ram_wen[4] = !lite_mem_cen && !lite_mem_wen[0] && ram_addr[17];
|
||
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assign ram_wen[5] = !lite_mem_cen && !lite_mem_wen[1] && ram_addr[17];
|
||
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assign ram_wen[6] = !lite_mem_cen && !lite_mem_wen[2] && ram_addr[17];
|
||
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assign ram_wen[7] = !lite_mem_cen && !lite_mem_wen[3] && ram_addr[17];
|
||
|
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|
||
|
|
assign ram0_din[7:0] = lite_mem_din[7:0];
|
||
|
|
assign ram1_din[7:0] = lite_mem_din[15:8];
|
||
|
|
assign ram2_din[7:0] = lite_mem_din[23:16];
|
||
|
|
assign ram3_din[7:0] = lite_mem_din[31:24];
|
||
|
|
assign lite_mem_dout[31:0] = addr_holding[17] ? {ram7_dout[7:0], ram6_dout[7:0], ram5_dout[7:0], ram4_dout[7:0]}
|
||
|
|
: {ram3_dout[7:0], ram2_dout[7:0], ram1_dout[7:0], ram0_dout[7:0]};
|
||
|
|
|
||
|
|
// memory unit is in DPTHx8 size, 4 units are instanced
|
||
|
|
soc_fpga_ram #(8, 17) ram0(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[16:0]),
|
||
|
|
.PortADataIn (ram0_din),
|
||
|
|
.PortAWriteEnable(ram_wen[0]),
|
||
|
|
.PortADataOut(ram0_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 17) ram1(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[16:0]),
|
||
|
|
.PortADataIn (ram1_din),
|
||
|
|
.PortAWriteEnable(ram_wen[1]),
|
||
|
|
.PortADataOut(ram1_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 17) ram2(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[16:0]),
|
||
|
|
.PortADataIn (ram2_din),
|
||
|
|
.PortAWriteEnable(ram_wen[2]),
|
||
|
|
.PortADataOut(ram2_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 17) ram3(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[16:0]),
|
||
|
|
.PortADataIn (ram3_din),
|
||
|
|
.PortAWriteEnable(ram_wen[3]),
|
||
|
|
.PortADataOut(ram3_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 16) ram4(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[15:0]),
|
||
|
|
.PortADataIn (ram0_din),
|
||
|
|
.PortAWriteEnable(ram_wen[4]),
|
||
|
|
.PortADataOut(ram4_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 16) ram5(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[15:0]),
|
||
|
|
.PortADataIn (ram1_din),
|
||
|
|
.PortAWriteEnable(ram_wen[5]),
|
||
|
|
.PortADataOut(ram5_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 16) ram6(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[15:0]),
|
||
|
|
.PortADataIn (ram2_din),
|
||
|
|
.PortAWriteEnable(ram_wen[6]),
|
||
|
|
.PortADataOut(ram6_dout));
|
||
|
|
|
||
|
|
soc_fpga_ram #(8, 16) ram7(
|
||
|
|
.PortAClk (ram_clk),
|
||
|
|
.PortAAddr(ram_addr[15:0]),
|
||
|
|
.PortADataIn (ram3_din),
|
||
|
|
.PortAWriteEnable(ram_wen[7]),
|
||
|
|
.PortADataOut(ram7_dout));
|
||
|
|
|
||
|
|
|
||
|
|
// &Force("nonport", "ram_addr"); @359
|
||
|
|
// &Force("nonport", "ram0_din"); @360
|
||
|
|
// &Force("nonport", "ram1_din"); @361
|
||
|
|
// &Force("nonport", "ram2_din"); @362
|
||
|
|
// &Force("nonport", "ram3_din"); @363
|
||
|
|
// &Force("nonport", "ram0_dout"); @364
|
||
|
|
// &Force("nonport", "ram1_dout"); @365
|
||
|
|
// &Force("nonport", "ram2_dout"); @366
|
||
|
|
// &Force("nonport", "ram3_dout"); @367
|
||
|
|
// &Force("nonport", "ram4_dout"); @368
|
||
|
|
// &Force("nonport", "ram5_dout"); @369
|
||
|
|
// &Force("nonport", "ram6_dout"); @370
|
||
|
|
// &Force("nonport", "ram7_dout"); @371
|
||
|
|
// &Force("nonport", "ram_wen"); @372
|
||
|
|
// &Force("nonport", "ram_clk"); @373
|
||
|
|
// &ModuleEnd; @374
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|
||
|
|
|