abstractaccelerator/fpga/xc7z010/led.v

module led(
	input  wire clk,	// 输入时钟
	output reg  led     // led 输出(高电平有效)
);

localparam  MAX_DELAY_CNT = 50000000,
            CYCLE_NUMBER  = 100;  //占空比分为0~100个级别

reg myclk;
reg [31:0] delay_cnt;
reg [7:0] current_cycle;
reg flag;
reg [7:0] cycle;

//--------------------------------------------------------
// myclk分频
always@(posedge clk) begin
	if(delay_cnt < MAX_DELAY_CNT)
		delay_cnt <= delay_cnt + 1'b1;
	else begin
		delay_cnt <= 32'd1;
		myclk <= ~myclk;  // 100Mhz
	end
end

//--------------------------------------------------------
// 0的时候，占空比最小，这个时候直接完全输出高电平，led灯最亮
// 100的时候，占空比最大，这个时候直接完全输出低电平，led等熄灭
always@(posedge myclk) begin
	if(flag == 0) begin // 占空比递增
		if(current_cycle < (CYCLE_NUMBER/10))
			current_cycle <= current_cycle + 1'b1;
		else
			flag <= ~flag;
	end
	else begin // 占空比递减
		if(current_cycle > 0)
			current_cycle <= current_cycle - 1'b1;
		else
			flag <= ~flag;
	end
end

//--------------------------------------------------------
// 轮询 0~100个级别的占空比
always@(posedge clk)
	if(cycle < CYCLE_NUMBER)
		cycle <= cycle + 1'b1;
	else
		cycle <= 1'b1;

//--------------------------------------------------------
// cycle小于current_cycle的时候是低电平
// cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平
// always@(posedge clk)
// 	if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
// 		led <= 1'b1;
// 	else if(cycle < current_cycle)
// 		led <= 1'b1;
// 	else
// 		led <= 1'b0;


always@(posedge clk)
	if((delay_cnt[20:14] ==0) && myclk)
		led <= 1'b1;
	else
		led <= 1'b0;


reg [17:0] a;
reg [17:0] b;
wire [17:0] p;

mult_gen_0 mul(
	.CLK(clk),
	.A(a),
	.B(b),
	.P(p)
);



endmodule