85 lines
1.9 KiB
Verilog
85 lines
1.9 KiB
Verilog
module led(
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input wire clk, // 输入时钟
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output reg led // led 输出(高电平有效)
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);
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localparam MAX_DELAY_CNT = 50000000,
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CYCLE_NUMBER = 100; //占空比分为0~100个级别
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reg myclk;
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reg [31:0] delay_cnt;
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reg [7:0] current_cycle;
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reg flag;
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reg [7:0] cycle;
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//--------------------------------------------------------
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// myclk分频
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always@(posedge clk) begin
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if(delay_cnt < MAX_DELAY_CNT)
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delay_cnt <= delay_cnt + 1'b1;
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else begin
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delay_cnt <= 32'd1;
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myclk <= ~myclk; // 100Mhz
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end
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end
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//--------------------------------------------------------
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// 0的时候，占空比最小，这个时候直接完全输出高电平，led灯最亮
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// 100的时候，占空比最大，这个时候直接完全输出低电平，led等熄灭
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always@(posedge myclk) begin
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if(flag == 0) begin // 占空比递增
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if(current_cycle < (CYCLE_NUMBER/10))
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current_cycle <= current_cycle + 1'b1;
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else
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flag <= ~flag;
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end
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else begin // 占空比递减
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if(current_cycle > 0)
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current_cycle <= current_cycle - 1'b1;
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else
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flag <= ~flag;
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end
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end
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//--------------------------------------------------------
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// 轮询 0~100个级别的占空比
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always@(posedge clk)
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if(cycle < CYCLE_NUMBER)
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cycle <= cycle + 1'b1;
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else
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cycle <= 1'b1;
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//--------------------------------------------------------
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// cycle小于current_cycle的时候是低电平
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// cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平
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// always@(posedge clk)
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// if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
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// led <= 1'b1;
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// else if(cycle < current_cycle)
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// led <= 1'b1;
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// else
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// led <= 1'b0;
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always@(posedge clk)
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if((delay_cnt[20:14] ==0) && myclk)
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led <= 1'b1;
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else
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led <= 1'b0;
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reg [17:0] a;
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reg [17:0] b;
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wire [17:0] p;
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mult_gen_0 mul(
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.CLK(clk),
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.A(a),
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.B(b),
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.P(p)
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);
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endmodule
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