59 lines
1.3 KiB
Coq
59 lines
1.3 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module ahb_fifo_entry(
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create_en,
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data_in,
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data_out,
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entry_clk,
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entry_rst_b
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);
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// &Ports; @20
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input create_en;
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input [54:0] data_in;
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input entry_clk;
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input entry_rst_b;
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output [54:0] data_out;
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// &Regs; @21
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reg [54:0] data_out;
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// &Wires; @22
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wire create_en;
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wire [54:0] data_in;
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wire entry_clk;
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wire entry_rst_b;
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always @(posedge entry_clk or negedge entry_rst_b)
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begin
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if (!entry_rst_b)
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data_out[54:0] <= 54'b0;
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else if (create_en)
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data_out[54:0] <= data_in[54:0];
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else
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data_out[54:0] <= data_out[54:0];
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end
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// &Force("output","data_out"); @34
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// &ModuleEnd; @39
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endmodule
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