476 lines
11 KiB
Coq
476 lines
11 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`define PS1_BASE_START 32'h40015000
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`define PS1_BASE_END 32'h40015fff
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// Timer
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`define PS2_BASE_START 32'h40011000
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`define PS2_BASE_END 32'h40011fff
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// PMU
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`define PS3_BASE_START 32'h40016000
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`define PS3_BASE_END 32'h40016fff
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//GPIO
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`define PS4_BASE_START 32'h40019000
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`define PS4_BASE_END 32'h40019fff
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//STimer
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`define PS5_BASE_START 32'h40018000
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`define PS5_BASE_END 32'h40018fff
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//CLKGEN
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`define PS6_BASE_START 32'h40017000
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`define PS6_BASE_END 32'h40017fff
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//SMPU
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`define PS7_BASE_START 32'h4001A000
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`define PS7_BASE_END 32'h4001Afff
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//NMI_WAKE
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`define PS8_BASE_START 32'h40021000
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`define PS8_BASE_END 32'h40021fff
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//NEW TIMER
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`define PS9_BASE_START 32'h40031000
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`define PS9_BASE_END 32'h40031fff
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// &ModuleBeg; @48
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module apb_bridge(
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apb_harb_hrdata,
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apb_harb_hready,
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apb_harb_hresp,
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apb_xx_paddr,
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apb_xx_penable,
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apb_xx_pwdata,
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apb_xx_pwrite,
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harb_apb_hsel,
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harb_xx_haddr,
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harb_xx_hwdata,
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harb_xx_hwrite,
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hclk,
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hrst_b,
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prdata_s1,
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prdata_s2,
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prdata_s3,
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prdata_s4,
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prdata_s5,
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prdata_s6,
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prdata_s7,
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prdata_s8,
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prdata_s9,
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psel_s1,
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psel_s2,
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psel_s3,
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psel_s4,
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psel_s5,
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psel_s6,
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psel_s7,
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psel_s8,
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psel_s9
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);
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// &Ports; @49
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input harb_apb_hsel;
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input [31:0] harb_xx_haddr;
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input [31:0] harb_xx_hwdata;
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input harb_xx_hwrite;
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input hclk;
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input hrst_b;
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input [31:0] prdata_s1;
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input [31:0] prdata_s2;
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input [31:0] prdata_s3;
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input [31:0] prdata_s4;
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input [31:0] prdata_s5;
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input [31:0] prdata_s6;
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input [31:0] prdata_s7;
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input [31:0] prdata_s8;
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input [31:0] prdata_s9;
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output [31:0] apb_harb_hrdata;
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output apb_harb_hready;
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output [1 :0] apb_harb_hresp;
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output [31:0] apb_xx_paddr;
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output apb_xx_penable;
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output [31:0] apb_xx_pwdata;
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output apb_xx_pwrite;
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output psel_s1;
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output psel_s2;
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output psel_s3;
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output psel_s4;
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output psel_s5;
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output psel_s6;
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output psel_s7;
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output psel_s8;
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output psel_s9;
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// &Regs; @50
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reg [31:0] apb_harb_hrdata;
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reg apb_harb_hready;
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reg [31:0] apb_xx_paddr;
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reg apb_xx_penable;
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reg apb_xx_psel;
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reg [31:0] apb_xx_pwdata;
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reg apb_xx_pwrite;
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reg [2 :0] cur_state;
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reg [31:0] haddr_latch;
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reg hwrite_latch;
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reg [2 :0] nxt_state;
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// &Wires; @51
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wire [1 :0] apb_harb_hresp;
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wire busy_s1;
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wire busy_s2;
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wire busy_s3;
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wire busy_s4;
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wire busy_s5;
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wire busy_s6;
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wire busy_s7;
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wire busy_s8;
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wire busy_s9;
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wire enable_latch;
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wire enable_r_select;
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wire harb_apb_hsel;
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wire [31:0] harb_xx_haddr;
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wire [31:0] harb_xx_hwdata;
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wire harb_xx_hwrite;
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wire hclk;
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wire hrst_b;
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wire idle_latch;
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wire idle_r_select;
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wire [31:0] prdata_s1;
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wire [31:0] prdata_s2;
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wire [31:0] prdata_s3;
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wire [31:0] prdata_s4;
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wire [31:0] prdata_s5;
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wire [31:0] prdata_s6;
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wire [31:0] prdata_s7;
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wire [31:0] prdata_s8;
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wire [31:0] prdata_s9;
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wire psel_s1;
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wire psel_s2;
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wire psel_s3;
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wire psel_s4;
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wire psel_s5;
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wire psel_s6;
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wire psel_s7;
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wire psel_s8;
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wire psel_s9;
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// &Force("output","apb_xx_paddr") @53
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// &Force("output","apb_xx_penable") @54
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// &Force("output","apb_xx_pwdata") @55
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// &Force("output","apb_xx_pwrite") @56
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// &Force("output","psel_s1") @57
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// &Force("output","psel_s2") @58
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// &Force("output","psel_s3") @59
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// &Force("output","psel_s4") @60
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// &Force("output","psel_s5") @61
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// &Force("output","psel_s6") @62
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// &Force("output","psel_s7") @63
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// &Force("output","psel_s8") @64
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// &Force("output","psel_s9") @65
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assign apb_harb_hresp[1:0] = 2'b0; //always OK
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parameter IDLE = 3'b000;
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parameter LATCH = 3'b001;
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parameter W_SELECT = 3'b010;
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parameter R_SELECT = 3'b011;
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parameter ENABLE = 3'b100;
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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cur_state[2:0] <= IDLE;
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end
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else
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begin
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cur_state[2:0] <= nxt_state[2:0];
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end
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end
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assign idle_latch = harb_apb_hsel && harb_xx_hwrite;
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assign idle_r_select = harb_apb_hsel && !harb_xx_hwrite;
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assign enable_latch = harb_apb_hsel && harb_xx_hwrite;
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assign enable_r_select = harb_apb_hsel && !harb_xx_hwrite;
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//always @(cur_state[2:0] or harb_apb_hsel or harb_xx_hwrite)
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//begin
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// &CombBeg; @94
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always @( enable_r_select
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or idle_latch
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or idle_r_select
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or enable_latch
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or cur_state[2:0])
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begin
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nxt_state[2:0] = IDLE;
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case(cur_state[2:0])
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IDLE:
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begin
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if(idle_latch)
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begin
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nxt_state[2:0] = LATCH;
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end
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else if(idle_r_select)
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begin
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nxt_state[2:0] = R_SELECT;
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end
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else
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begin
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nxt_state[2:0] = IDLE;
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end
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end
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LATCH:
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begin
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nxt_state[2:0] = W_SELECT;
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end
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W_SELECT:
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begin
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nxt_state[2:0] = ENABLE;
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end
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R_SELECT:
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begin
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nxt_state[2:0] = ENABLE;
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end
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ENABLE:
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begin
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if(enable_latch)
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begin
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nxt_state[2:0] = LATCH;
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end
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else if(enable_r_select)
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begin
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nxt_state[2:0] = R_SELECT;
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end
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else
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begin
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nxt_state[2:0] = IDLE;
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end
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end
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endcase
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// &CombEnd; @140
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end
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//end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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haddr_latch[31:0] <= 32'b0;
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hwrite_latch <= 1'b0;
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end
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else if(nxt_state[2:0]==LATCH)
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begin
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haddr_latch[31:0] <= harb_xx_haddr[31:0];
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hwrite_latch <= harb_xx_hwrite;
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end
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else
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begin
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haddr_latch[31:0] <= haddr_latch[31:0];
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hwrite_latch <= hwrite_latch;
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end
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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apb_xx_paddr[31:0] <= 32'b0;
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apb_xx_pwrite <= 1'b0;
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end
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else if(nxt_state[2:0]==W_SELECT)
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begin
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apb_xx_paddr[31:0] <= haddr_latch[31:0];
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apb_xx_pwrite <= hwrite_latch;
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end
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else if(nxt_state[2:0]==R_SELECT)
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begin
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apb_xx_paddr[31:0] <= harb_xx_haddr[31:0];
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apb_xx_pwrite <= harb_xx_hwrite;
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end
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else
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begin
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apb_xx_paddr[31:0] <= apb_xx_paddr[31:0];
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apb_xx_pwrite <= apb_xx_pwrite;
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end
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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apb_xx_pwdata[31:0] <= 32'b0;
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end
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else if(nxt_state[2:0]==W_SELECT)
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begin
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apb_xx_pwdata[31:0] <= harb_xx_hwdata[31:0];
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end
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else
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begin
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apb_xx_pwdata[31:0] <= apb_xx_pwdata[31:0];
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end
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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apb_xx_psel <= 1'b0;
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end
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else if(nxt_state[2:0]==W_SELECT)
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begin
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apb_xx_psel <= 1'b1;
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end
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else if(nxt_state[2:0]==R_SELECT)
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begin
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apb_xx_psel <= 1'b1;
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end
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else if(nxt_state[2:0]==ENABLE)
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begin
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apb_xx_psel <= 1'b1;
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end
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else
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begin
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apb_xx_psel <= 1'b0;
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end
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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apb_xx_penable <= 1'b0;
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end
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else if(nxt_state[2:0]==ENABLE)
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begin
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apb_xx_penable <= 1'b1;
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end
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else
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begin
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apb_xx_penable <= 1'b0;
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end
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if(!hrst_b)
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begin
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apb_harb_hready <= 1'b1;
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end
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else if(nxt_state[2:0]==LATCH)
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begin
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apb_harb_hready <= 1'b0;
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end
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else if(nxt_state[2:0]==W_SELECT)
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begin
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apb_harb_hready <= 1'b0;
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end
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else if(nxt_state[2:0]==R_SELECT)
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begin
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apb_harb_hready <= 1'b0;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
apb_harb_hready <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign psel_s1 = apb_xx_psel && (apb_xx_paddr>=`PS1_BASE_START) && (apb_xx_paddr<=`PS1_BASE_END);
|
||
|
|
assign psel_s2 = apb_xx_psel && (apb_xx_paddr>=`PS2_BASE_START) && (apb_xx_paddr<=`PS2_BASE_END);
|
||
|
|
assign psel_s3 = apb_xx_psel && (apb_xx_paddr>=`PS3_BASE_START) && (apb_xx_paddr<=`PS3_BASE_END);
|
||
|
|
assign psel_s4 = apb_xx_psel && (apb_xx_paddr>=`PS4_BASE_START) && (apb_xx_paddr<=`PS4_BASE_END);
|
||
|
|
assign psel_s5 = apb_xx_psel && (apb_xx_paddr>=`PS5_BASE_START) && (apb_xx_paddr<=`PS5_BASE_END);
|
||
|
|
assign psel_s6 = apb_xx_psel && (apb_xx_paddr>=`PS6_BASE_START) && (apb_xx_paddr<=`PS6_BASE_END);
|
||
|
|
assign psel_s7 = apb_xx_psel && (apb_xx_paddr>=`PS7_BASE_START) && (apb_xx_paddr<=`PS7_BASE_END);
|
||
|
|
assign psel_s8 = apb_xx_psel && (apb_xx_paddr>=`PS8_BASE_START) && (apb_xx_paddr<=`PS8_BASE_END);
|
||
|
|
assign psel_s9 = apb_xx_psel && (apb_xx_paddr>=`PS9_BASE_START) && (apb_xx_paddr<=`PS9_BASE_END);
|
||
|
|
|
||
|
|
|
||
|
|
assign busy_s1 = apb_xx_penable && psel_s1;
|
||
|
|
assign busy_s2 = apb_xx_penable && psel_s2;
|
||
|
|
assign busy_s3 = apb_xx_penable && psel_s3;
|
||
|
|
assign busy_s4 = apb_xx_penable && psel_s4;
|
||
|
|
assign busy_s5 = apb_xx_penable && psel_s5;
|
||
|
|
assign busy_s6 = apb_xx_penable && psel_s6;
|
||
|
|
assign busy_s7 = apb_xx_penable && psel_s7;
|
||
|
|
assign busy_s8 = apb_xx_penable && psel_s8;
|
||
|
|
assign busy_s9 = apb_xx_penable && psel_s9;
|
||
|
|
|
||
|
|
// &CombBeg; @287
|
||
|
|
always @( busy_s9
|
||
|
|
or busy_s3
|
||
|
|
or busy_s4
|
||
|
|
or prdata_s3[31:0]
|
||
|
|
or prdata_s8[31:0]
|
||
|
|
or busy_s7
|
||
|
|
or busy_s2
|
||
|
|
or prdata_s5[31:0]
|
||
|
|
or busy_s6
|
||
|
|
or prdata_s6[31:0]
|
||
|
|
or busy_s5
|
||
|
|
or busy_s1
|
||
|
|
or prdata_s1[31:0]
|
||
|
|
or busy_s8
|
||
|
|
or prdata_s4[31:0]
|
||
|
|
or prdata_s9[31:0]
|
||
|
|
or prdata_s2[31:0]
|
||
|
|
or prdata_s7[31:0])
|
||
|
|
begin
|
||
|
|
case({busy_s1,busy_s2,busy_s3,busy_s4,busy_s5,busy_s6,busy_s7,busy_s8,busy_s9})
|
||
|
|
9'b100000000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s1[31:0];
|
||
|
|
end
|
||
|
|
9'b010000000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s2[31:0];
|
||
|
|
end
|
||
|
|
9'b001000000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s3[31:0];
|
||
|
|
end
|
||
|
|
9'b000100000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s4[31:0];
|
||
|
|
end
|
||
|
|
9'b000010000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s5[31:0];
|
||
|
|
end
|
||
|
|
9'b000001000:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s6[31:0];
|
||
|
|
end
|
||
|
|
9'b000000100:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s7[31:0];
|
||
|
|
end
|
||
|
|
9'b000000010:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s8[31:0];
|
||
|
|
end
|
||
|
|
9'b000000001:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = prdata_s9[31:0];
|
||
|
|
end
|
||
|
|
|
||
|
|
default:
|
||
|
|
begin
|
||
|
|
apb_harb_hrdata[31:0] = 32'b0;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
// &CombEnd; @331
|
||
|
|
end
|
||
|
|
|
||
|
|
// &ModuleEnd; @333
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|
||
|
|
|