abstractaccelerator/testbench/hex/data.hex

@00001000
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 
65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20 
53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D 
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation. 2019-08-08 08:04:48 +08:00			`@00001000`
			`2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D`
			`2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48`
			`65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20`
			`53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D`
			`2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D`
			`2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00`