209 lines
10 KiB
Systemverilog
209 lines
10 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2018 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Owner:
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// Function: SVCI to AXI4 Bridge
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// Comments:
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//
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//********************************************************************************
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module svci_to_axi4 #(parameter TAG = 1,
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ID = 1,
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PRTY = 1) (
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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input logic bus_clk_en,
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input logic clk_override,
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// AXI signals
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// AXI Write Channels
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output logic axi_awvalid,
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input logic axi_awready,
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output logic axi_awposted,
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output logic [TAG-1:0] axi_awid,
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output logic [31:0] axi_awaddr,
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output logic [2:0] axi_awsize,
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output logic [2:0] axi_awprot,
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output logic [7:0] axi_awlen,
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output logic [1:0] axi_awburst,
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output logic [ID-1:0] axi_awmid,
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output logic [PRTY-1:0] axi_awprty,
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output logic axi_wvalid,
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input logic axi_wready,
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output logic [63:0] axi_wdata,
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output logic [7:0] axi_wstrb,
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output logic axi_wlast,
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input logic axi_bvalid,
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output logic axi_bready,
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input logic axi_bposted,
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input logic [1:0] axi_bresp,
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input logic [TAG-1:0] axi_bid,
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input logic [ID-1:0] axi_bmid,
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input logic [PRTY-1:0] axi_bprty,
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// AXI Read Channels
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output logic axi_arvalid,
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input logic axi_arready,
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output logic [TAG-1:0] axi_arid,
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output logic [31:0] axi_araddr,
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output logic [2:0] axi_arsize,
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output logic [2:0] axi_arprot,
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output logic [7:0] axi_arlen,
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output logic [1:0] axi_arburst,
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output logic [ID-1:0] axi_armid,
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output logic [PRTY-1:0] axi_arprty,
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input logic axi_rvalid,
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output logic axi_rready,
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input logic [TAG-1:0] axi_rid,
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input logic [63:0] axi_rdata,
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input logic [1:0] axi_rresp,
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input logic [ID-1:0] axi_rmid,
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input logic [PRTY-1:0] axi_rprty,
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// SVCI signals
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input logic svci_cmd_valid,
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output logic svci_cmd_ready,
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input logic [TAG-1:0] svci_cmd_tag,
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input logic [ID-1:0] svci_cmd_mid,
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input logic [31:0] svci_cmd_addr,
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input logic [63:0] svci_cmd_wdata,
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input logic [7:0] svci_cmd_wbe,
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input logic [2:0] svci_cmd_length,
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input logic [2:0] svci_cmd_opc,
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input logic [PRTY-1:0] svci_cmd_prty,
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input logic dma_slv_algn_err,
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output logic svci_rsp_valid,
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input logic svci_rsp_ready,
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output logic [TAG-1:0] svci_rsp_tag,
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output logic [ID-1:0] svci_rsp_mid,
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output logic [63:0] svci_rsp_rdata,
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output logic [3:0] svci_rsp_opc,
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output logic [PRTY-1:0] svci_rsp_prty
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);
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logic cmdbuf_wr_en, cmdbuf_data_en, cmdbuf_rst, cmdbuf_data_rst;
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logic cmdbuf_full;
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logic cmdbuf_vld, cmdbuf_data_vld;
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logic [2:0] cmdbuf_opc, cmdbuf_size;
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logic [7:0] cmdbuf_wstrb;
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logic [31:0] cmdbuf_addr;
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logic [63:0] cmdbuf_wdata;
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logic [TAG-1:0] cmdbuf_tag;
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logic [ID-1:0] cmdbuf_mid;
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logic [PRTY-1:0] cmdbuf_prty;
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logic wrbuf_en, wrbuf_rst;
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logic wrbuf_vld;
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logic wrbuf_posted;
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logic [TAG-1:0] wrbuf_tag;
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logic [ID-1:0] wrbuf_mid;
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logic [1:0] wrbuf_resp;
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logic [63:0] error_address; // SVCI needs the error address back on the rdata.
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logic [PRTY-1:0] wrbuf_prty;
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logic [1:0] axi_bresp_in; // need to map 2 errors in to 3 errors
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logic bus_clk;
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// Command buffer
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assign cmdbuf_wr_en = svci_cmd_valid & svci_cmd_ready;
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assign cmdbuf_data_en = cmdbuf_wr_en & (svci_cmd_opc[2:1] == 2'b01);
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assign cmdbuf_rst = ((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en;
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assign cmdbuf_data_rst = (axi_wvalid & axi_wready) & (cmdbuf_opc[2:1] == 2'b01) & ~cmdbuf_data_en;
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assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready))) | (cmdbuf_data_vld & ~((axi_wvalid & axi_wready) & (cmdbuf_opc[2:1] == 2'b01)));
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rvdffsc #(.WIDTH(1)) cmdbuf_vldff(.din(1'b1), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clear(cmdbuf_rst), .clk(bus_clk), .*);
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rvdffsc #(.WIDTH(1)) cmdbuf_data_vldff(.din(1'b1), .dout(cmdbuf_data_vld), .en(cmdbuf_data_en), .clear(cmdbuf_data_rst), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(3)) cmdbuf_opcff(.din(svci_cmd_opc[2:0]), .dout(cmdbuf_opc[2:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(3)) cmdbuf_sizeff(.din(svci_cmd_length[2:0]), .dout(cmdbuf_size[2:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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rvdffe #(.WIDTH(8)) cmdbuf_wstrbff(.din(svci_cmd_wbe[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
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rvdffe #(.WIDTH(32)) cmdbuf_addrff(.din(svci_cmd_addr[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
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rvdffe #(.WIDTH(64)) cmdbuf_wdataff(.din(svci_cmd_wdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_data_en & bus_clk_en), .*);
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rvdffs #(.WIDTH(TAG)) cmdbuf_tagff(.din(svci_cmd_tag[TAG-1:0]), .dout(cmdbuf_tag[TAG-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(ID)) cmdbuf_midff(.din(svci_cmd_mid[ID-1:0]), .dout(cmdbuf_mid[ID-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(PRTY)) cmdbuf_prtyff(.din(svci_cmd_prty[PRTY-1:0]), .dout(cmdbuf_prty[PRTY-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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// AXI Write Channels
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assign axi_awvalid = cmdbuf_vld & (cmdbuf_opc[2:1] == 2'b01);
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assign axi_awposted = axi_awvalid & ~cmdbuf_opc[0];
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assign axi_awid[TAG-1:0] = cmdbuf_tag[TAG-1:0];
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assign axi_awaddr[31:0] = cmdbuf_addr[31:0];
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assign axi_awsize[2:0] = cmdbuf_size[2:0];
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assign axi_awprot[2:0] = 3'b0;
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assign axi_awlen[7:0] = '0;
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assign axi_awburst[1:0] = 2'b01;
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assign axi_awmid = cmdbuf_mid[ID-1:0];
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assign axi_awprty = cmdbuf_prty[PRTY-1:0];
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assign axi_wvalid = cmdbuf_data_vld;
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assign axi_wdata[63:0] = cmdbuf_wdata[63:0];
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assign axi_wstrb[7:0] = cmdbuf_wstrb[7:0];
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assign axi_wlast = 1'b1;
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assign axi_bready = ~wrbuf_vld | svci_rsp_ready;
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// AXI Read Channels
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assign axi_arvalid = cmdbuf_vld & (cmdbuf_opc[2:0] == 3'b0);
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assign axi_arid[TAG-1:0] = cmdbuf_tag[TAG-1:0];
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assign axi_araddr[31:0] = cmdbuf_addr[31:0];
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assign axi_arsize[2:0] = cmdbuf_size[2:0];
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assign axi_arprot = 3'b0;
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assign axi_arlen[7:0] = '0;
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assign axi_arburst[1:0] = 2'b01;
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assign axi_armid = cmdbuf_mid[ID-1:0];
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assign axi_rready = ~wrbuf_vld & svci_rsp_ready;
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assign axi_arprty = cmdbuf_prty[PRTY-1:0];
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// SVCI_response signals
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assign svci_rsp_valid = wrbuf_vld | axi_rvalid;
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assign svci_rsp_tag[TAG-1:0] = wrbuf_vld ? wrbuf_tag[TAG-1:0] : axi_rid[TAG-1:0];
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assign svci_rsp_mid[ID-1:0] = wrbuf_vld ? wrbuf_mid[ID-1:0] : axi_rmid[ID-1:0];
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assign svci_rsp_rdata[63:0] = wrbuf_vld ? {32'b0, error_address[31:0]} : axi_rdata[63:0]; // rdata
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assign svci_rsp_opc[3:2] = wrbuf_vld ? {1'b1, ~wrbuf_posted} : 2'b0;
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// assign svci_rsp_opc[1:0] = wrbuf_vld ? {wrbuf_resp[1] ? (wrbuf_resp[0] ? 2'b10 : 2'b01) : 2'b0} : // AXI Slave Error -> SVCI Slave Error, AXI Decode Error -> SVCI Address Error
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// {axi_rresp[1] ? (axi_rresp[0] ? 2'b10 : 2'b01) : 2'b0};
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assign svci_rsp_opc[1:0] = wrbuf_vld ? wrbuf_resp[1:0] : // AXI Slave Error -> SVCI Slave Error, AXI Decode Error -> SVCI Address Error
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{axi_rresp[1] ? (axi_rresp[0] ? 2'b10 : {dma_slv_algn_err, 1'b1}) : 2'b0};
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assign svci_rsp_prty[PRTY-1:0] = wrbuf_vld ? wrbuf_prty[PRTY-1:0] : axi_rprty[PRTY-1:0];
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assign svci_cmd_ready = ~cmdbuf_full;
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// Write Response Buffer. Errors for writes need to send the Error address back on the rsp_rdata for SVCI. The address is sent back on axi_rdata bus for both reads and writes that have errors.
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// assign wrbuf_en = axi_bvalid & svci_rsp_ready & (~axi_bposted | axi_bresp[1]);
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assign wrbuf_en = axi_bvalid & axi_bready & (~axi_bposted | axi_bresp[1]);
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assign wrbuf_rst = svci_rsp_valid & svci_rsp_ready & svci_rsp_opc[3] & ~wrbuf_en;
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assign axi_bresp_in[1:0] = {axi_bresp[1] ? (axi_bresp[0] ? 2'b10 : {dma_slv_algn_err, 1'b1}) : 2'b0};
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rvdffsc #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(32)) wrbuf_erroff (.din(axi_rdata[31:0]), .dout(error_address[31:0]), .en(wrbuf_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(1)) wrbuf_postedff(.din(axi_bposted), .dout(wrbuf_posted), .en(wrbuf_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_bid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(ID)) wrbuf_midff (.din(axi_bmid[ID-1:0]), .dout(wrbuf_mid[ID-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(PRTY))wrbuf_prtyff (.din(axi_bprty[PRTY-1:0]), .dout(wrbuf_prty[PRTY-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
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rvdffs #(.WIDTH(2)) wrbuf_respff (.din(axi_bresp_in[1:0]), .dout(wrbuf_resp[1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
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// Clock header logic
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rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
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endmodule // svci_to_axi4
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