353 lines
9.8 KiB
Coq
353 lines
9.8 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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//SYS MEM
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`define S1_BASE_START 32'h60000000
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`define S1_BASE_END 32'h600fffff
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//APB
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`define S2_BASE_START 32'h40000000
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`define S2_BASE_END 32'h4fffffff
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//IMEM
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`define S4_BASE_START 32'h00000000
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`define S4_BASE_END 32'h0007ffff
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//DMEM
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`define S5_BASE_START 32'h20000000
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`define S5_BASE_END 32'h2007ffff
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// &Depend("environment.h"); @35
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// &ModuleBeg; @36
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module ahb(
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biu_pad_haddr,
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biu_pad_hburst,
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biu_pad_hprot,
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biu_pad_hsize,
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biu_pad_htrans,
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biu_pad_hwdata,
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biu_pad_hwrite,
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haddr_s1,
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haddr_s2,
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haddr_s3,
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hburst_s1,
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hburst_s3,
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hmastlock,
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hprot_s1,
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hprot_s3,
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hrdata_s1,
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hrdata_s2,
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hrdata_s3,
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hready_s1,
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hready_s2,
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hready_s3,
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hresp_s1,
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hresp_s2,
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hresp_s3,
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hsel_s1,
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hsel_s2,
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hsel_s3,
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hsize_s1,
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hsize_s3,
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htrans_s1,
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htrans_s3,
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hwdata_s1,
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hwdata_s2,
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hwdata_s3,
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hwrite_s1,
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hwrite_s2,
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hwrite_s3,
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pad_biu_hrdata,
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pad_biu_hready,
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pad_biu_hresp,
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pad_cpu_rst_b,
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pll_core_cpuclk,
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smpu_deny
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);
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// &Ports; @37
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input [31:0] biu_pad_haddr;
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input [2 :0] biu_pad_hburst;
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input [3 :0] biu_pad_hprot;
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input [2 :0] biu_pad_hsize;
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input [1 :0] biu_pad_htrans;
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input [31:0] biu_pad_hwdata;
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input biu_pad_hwrite;
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input [31:0] hrdata_s1;
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input [31:0] hrdata_s2;
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input [31:0] hrdata_s3;
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input hready_s1;
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input hready_s2;
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input hready_s3;
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input [1 :0] hresp_s1;
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input [1 :0] hresp_s2;
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input [1 :0] hresp_s3;
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input pad_cpu_rst_b;
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input pll_core_cpuclk;
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input smpu_deny;
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output [31:0] haddr_s1;
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output [31:0] haddr_s2;
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output [31:0] haddr_s3;
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output [2 :0] hburst_s1;
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output [2 :0] hburst_s3;
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output hmastlock;
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output [3 :0] hprot_s1;
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output [3 :0] hprot_s3;
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output hsel_s1;
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output hsel_s2;
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output hsel_s3;
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output [2 :0] hsize_s1;
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output [2 :0] hsize_s3;
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output [1 :0] htrans_s1;
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output [1 :0] htrans_s3;
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output [31:0] hwdata_s1;
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output [31:0] hwdata_s2;
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output [31:0] hwdata_s3;
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output hwrite_s1;
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output hwrite_s2;
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output hwrite_s3;
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output [31:0] pad_biu_hrdata;
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output pad_biu_hready;
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output [1 :0] pad_biu_hresp;
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// &Regs; @38
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reg busy_s1;
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reg busy_s2;
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reg busy_s3;
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reg busy_s4;
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reg busy_s5;
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reg [31:0] pad_biu_hrdata;
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reg pad_biu_hready;
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reg [1 :0] pad_biu_hresp;
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// &Wires; @39
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wire arb_block;
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wire [31:0] biu_pad_haddr;
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wire [2 :0] biu_pad_hburst;
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wire [3 :0] biu_pad_hprot;
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wire [2 :0] biu_pad_hsize;
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wire [1 :0] biu_pad_htrans;
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wire [31:0] biu_pad_hwdata;
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wire biu_pad_hwrite;
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wire [31:0] haddr_s1;
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wire [31:0] haddr_s2;
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wire [31:0] haddr_s3;
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wire [2 :0] hburst_s1;
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wire [2 :0] hburst_s2;
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wire [2 :0] hburst_s3;
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wire hmastlock;
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wire [3 :0] hprot_s1;
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wire [3 :0] hprot_s2;
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wire [3 :0] hprot_s3;
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wire [31:0] hrdata_s1;
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wire [31:0] hrdata_s2;
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wire [31:0] hrdata_s3;
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wire [31:0] hrdata_s4;
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wire [31:0] hrdata_s5;
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wire hready_s1;
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wire hready_s2;
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wire hready_s3;
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wire hready_s4;
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wire hready_s5;
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wire [1 :0] hresp_s1;
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wire [1 :0] hresp_s2;
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wire [1 :0] hresp_s3;
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wire [1 :0] hresp_s4;
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wire [1 :0] hresp_s5;
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wire hsel_s1;
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wire hsel_s2;
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wire hsel_s3;
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wire hsel_s4;
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wire hsel_s5;
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wire [2 :0] hsize_s1;
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wire [2 :0] hsize_s2;
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wire [2 :0] hsize_s3;
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wire [1 :0] htrans_s1;
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wire [1 :0] htrans_s2;
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wire [1 :0] htrans_s3;
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wire [31:0] hwdata_s1;
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wire [31:0] hwdata_s2;
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wire [31:0] hwdata_s3;
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wire hwrite_s1;
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wire hwrite_s2;
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wire hwrite_s3;
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wire pad_cpu_rst_b;
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wire pll_core_cpuclk;
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wire pre_busy_s1;
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wire pre_busy_s2;
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wire pre_busy_s3;
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wire pre_busy_s4;
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wire pre_busy_s5;
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wire smpu_deny;
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// Support AHB LITE
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assign hmastlock = 1'b0;
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// &Force("input","biu_pad_hbusreq"); @48
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assign haddr_s1[31:0] = biu_pad_haddr[31:0];
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assign hburst_s1[2:0] = biu_pad_hburst[2:0];
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assign hprot_s1[3:0] = biu_pad_hprot[3:0];
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assign hsize_s1[2:0] = biu_pad_hsize[2:0];
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assign htrans_s1[1:0] = biu_pad_htrans[1:0];
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assign hwrite_s1 = biu_pad_hwrite;
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assign hwdata_s1[31:0] = biu_pad_hwdata[31:0];
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assign haddr_s2[31:0] = biu_pad_haddr[31:0];
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assign hburst_s2[2:0] = biu_pad_hburst[2:0];
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assign hprot_s2[3:0] = biu_pad_hprot[3:0];
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assign hsize_s2[2:0] = biu_pad_hsize[2:0];
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assign htrans_s2[1:0] = biu_pad_htrans[1:0];
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assign hwrite_s2 = biu_pad_hwrite;
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assign hwdata_s2[31:0] = biu_pad_hwdata[31:0];
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// &Force("nonport","hburst_s2"); @68
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// &Force("nonport","hsize_s2"); @69
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// &Force("nonport","htrans_s2"); @70
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// &Force("nonport","hprot_s2"); @71
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// &Force("bus","biu_pad_hprot",3,0); @72
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assign haddr_s3[31:0] = biu_pad_haddr[31:0];
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assign hburst_s3[2:0] = biu_pad_hburst[2:0];
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assign hprot_s3[3:0] = biu_pad_hprot[3:0];
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assign hsize_s3[2:0] = biu_pad_hsize[2:0];
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assign htrans_s3[1:0] = biu_pad_htrans[1:0];
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assign hwrite_s3 = biu_pad_hwrite;
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assign hwdata_s3[31:0] = biu_pad_hwdata[31:0];
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assign hready_s4 = 1'b0;
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assign hrdata_s4[31:0] = 32'b0;
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assign hresp_s4[1:0] = 2'b0;
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// &Force("output","hsel_s4"); @95
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assign hready_s5 = 1'b0;
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assign hrdata_s5[31:0] = 32'b0;
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assign hresp_s5[1:0] = 2'b0;
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// &Force("output","hsel_s5"); @113
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// &Force("output","hsel_s1"); @117
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// &Force("output","hsel_s2"); @118
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// &Force("output","hsel_s3"); @119
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assign hsel_s1 = (biu_pad_htrans[1]==1'b1) && (biu_pad_haddr >= `S1_BASE_START) && (biu_pad_haddr <= `S1_BASE_END)
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&& !arb_block && !smpu_deny;
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assign hsel_s2 = (biu_pad_htrans[1]==1'b1) && (biu_pad_haddr >= `S2_BASE_START) && (biu_pad_haddr <= `S2_BASE_END)
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&& !arb_block && !smpu_deny;
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assign hsel_s3 = (biu_pad_htrans[1]==1'b1) && (!hsel_s1 && !hsel_s2 && !hsel_s4 && !hsel_s5
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|| smpu_deny) && !arb_block;
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assign hsel_s4 = 0;
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assign hsel_s5 = 0;
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assign pre_busy_s1 = hsel_s1 || busy_s1 && !hready_s1;
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assign pre_busy_s2 = hsel_s2 || busy_s2 && !hready_s2;
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assign pre_busy_s3 = hsel_s3 || busy_s3 && !hready_s3;
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assign pre_busy_s4 = 1'b0;
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assign pre_busy_s5 = 1'b0;
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always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)begin
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busy_s1 <= 1'b0;
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busy_s2 <= 1'b0;
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busy_s3 <= 1'b0;
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busy_s4 <= 1'b0;
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busy_s5 <= 1'b0;
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end
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else begin
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busy_s1 <= pre_busy_s1;
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busy_s2 <= pre_busy_s2;
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busy_s3 <= pre_busy_s3;
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busy_s4 <= pre_busy_s4;
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busy_s5 <= pre_busy_s5;
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end
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end
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assign arb_block = busy_s1 && !hready_s1 ||
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busy_s2 && !hready_s2 ||
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busy_s3 && !hready_s3 ||
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busy_s4 && !hready_s4 ||
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busy_s5 && !hready_s5;
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//arbitration state machine
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// &CombBeg; @182
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always @( hresp_s3[1:0]
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or hready_s5
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or hresp_s1[1:0]
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or busy_s3
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or busy_s4
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or hresp_s5[1:0]
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or hrdata_s3[31:0]
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or hready_s3
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or busy_s2
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or hrdata_s2[31:0]
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or hrdata_s1[31:0]
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or hresp_s4[1:0]
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or busy_s5
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or hready_s2
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or busy_s1
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or hrdata_s4[31:0]
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or hready_s4
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or hrdata_s5[31:0]
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or hresp_s2[1:0]
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or hready_s1)
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begin
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case({busy_s1,busy_s2,busy_s3,busy_s4,busy_s5})
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5'b10000:
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begin
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pad_biu_hrdata[31:0] = hrdata_s1[31:0];
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pad_biu_hready = hready_s1;
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pad_biu_hresp[1:0] = hresp_s1[1:0];
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end
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5'b01000:
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begin
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pad_biu_hrdata[31:0] = hrdata_s2[31:0];
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pad_biu_hready = hready_s2;
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pad_biu_hresp[1:0] = hresp_s2[1:0];
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end
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5'b00100:
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begin
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pad_biu_hrdata[31:0] = hrdata_s3[31:0];
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pad_biu_hready = hready_s3;
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pad_biu_hresp[1:0] = hresp_s3[1:0];
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end
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5'b00010:
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begin
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pad_biu_hrdata[31:0] = hrdata_s4[31:0];
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pad_biu_hready = hready_s4;
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pad_biu_hresp[1:0] = hresp_s4[1:0];
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end
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5'b00001:
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begin
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pad_biu_hrdata[31:0] = hrdata_s5[31:0];
|
||
|
|
pad_biu_hready = hready_s5;
|
||
|
|
pad_biu_hresp[1:0] = hresp_s5[1:0];
|
||
|
|
end
|
||
|
|
default:
|
||
|
|
begin
|
||
|
|
pad_biu_hrdata[31:0] = 32'b0;
|
||
|
|
pad_biu_hready = 1'b1;
|
||
|
|
pad_biu_hresp[1:0] = 2'b0;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
// &CombEnd; @221
|
||
|
|
end
|
||
|
|
// &ModuleEnd; @222
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|