239 lines
8.8 KiB
Systemverilog
239 lines
8.8 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module axi_slv #(
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TAGW = 1
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) (
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input aclk,
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input rst_l,
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input arvalid,
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output reg arready,
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input [ 31:0] araddr,
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input [TAGW-1:0] arid,
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input [ 7:0] arlen,
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input [ 1:0] arburst,
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input [ 2:0] arsize,
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output reg rvalid,
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input rready,
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output reg [ 63:0] rdata,
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output reg [ 1:0] rresp,
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output reg [TAGW-1:0] rid,
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output rlast,
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input awvalid,
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output awready,
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input [ 31:0] awaddr,
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input [TAGW-1:0] awid,
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input [ 7:0] awlen,
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input [ 1:0] awburst,
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input [ 2:0] awsize,
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input [63:0] wdata,
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input [ 7:0] wstrb,
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input wvalid,
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output wready,
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output reg bvalid,
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input bready,
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output reg [ 1:0] bresp,
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output reg [TAGW-1:0] bid
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);
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
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parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
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bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
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bit [63:0] memdata;
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wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
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wire [7:0] rm0 = mem0[saraddr0];
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wire [7:0] rm1 = mem1[saraddr1];
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wire [7:0] rm2 = mem2[saraddr2];
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wire [7:0] rm3 = mem3[saraddr3];
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wire [7:0] rm4 = mem4[saraddr4];
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wire [7:0] rm5 = mem5[saraddr5];
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wire [7:0] rm6 = mem6[saraddr6];
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wire [7:0] rm7 = mem7[saraddr7];
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wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
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initial begin
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mem0[0] = 8'h63;
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mem1[0] = 8'h0;
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mem2[0] = 8'h0;
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mem3[0] = 8'h0;
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end
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always @(posedge aclk or negedge rst_l) begin
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if (!rst_l) begin
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rvalid <= 0;
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bvalid <= 0;
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end else begin
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bid <= awid;
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rid <= arid;
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rvalid <= arvalid;
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bvalid <= awvalid;
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rdata <= memdata;
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end
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end
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always @(negedge aclk) begin
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if (arvalid)
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case (araddr[2:0])
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3'h0: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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3'h1: begin
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memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
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end
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3'h2: begin
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memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
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end
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3'h3: begin
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memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
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end
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3'h4: begin
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memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
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end
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3'h5: begin
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memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
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end
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3'h6: begin
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memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
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end
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3'h7: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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endcase
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if (awvalid) begin
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case (awaddr[2:0])
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3'h0: begin
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if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
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if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
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if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
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if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
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if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
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if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
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if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
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if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
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end
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3'h1: begin
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if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
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if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
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if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
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if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
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if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
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if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
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if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
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if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
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end
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3'h2: begin
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if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
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if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
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if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
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if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
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if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
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if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
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if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
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if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
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end
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3'h3: begin
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if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
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if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
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if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
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if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
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if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
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if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
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if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
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if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
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end
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3'h4: begin
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if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
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if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
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if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
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if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
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if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
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if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
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if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
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if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
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end
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3'h5: begin
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if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
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if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
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if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
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if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
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if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
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if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
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if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
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if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
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end
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3'h6: begin
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if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
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if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
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if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
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if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
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if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
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if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
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if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
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if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
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end
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3'h7: begin
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if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
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if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
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if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
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if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
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if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
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if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
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if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
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if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
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end
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endcase
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end
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end
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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endmodule
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