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abstractaccelerator/Flow/soc/ahb_sif.sv

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
module axi_slv #(
TAGW = 1
) (
input aclk,
input rst_l,
input arvalid,
output reg arready,
input [ 31:0] araddr,
input [TAGW-1:0] arid,
input [ 7:0] arlen,
input [ 1:0] arburst,
input [ 2:0] arsize,
output reg rvalid,
input rready,
output reg [ 63:0] rdata,
output reg [ 1:0] rresp,
output reg [TAGW-1:0] rid,
output rlast,
input awvalid,
output awready,
input [ 31:0] awaddr,
input [TAGW-1:0] awid,
input [ 7:0] awlen,
input [ 1:0] awburst,
input [ 2:0] awsize,
input [63:0] wdata,
input [ 7:0] wstrb,
input wvalid,
output wready,
output reg bvalid,
input bready,
output reg [ 1:0] bresp,
output reg [TAGW-1:0] bid
);
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
bit [63:0] memdata;
wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
wire [7:0] rm0 = mem0[saraddr0];
wire [7:0] rm1 = mem1[saraddr1];
wire [7:0] rm2 = mem2[saraddr2];
wire [7:0] rm3 = mem3[saraddr3];
wire [7:0] rm4 = mem4[saraddr4];
wire [7:0] rm5 = mem5[saraddr5];
wire [7:0] rm6 = mem6[saraddr6];
wire [7:0] rm7 = mem7[saraddr7];
wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
initial begin
mem0[0] = 8'h63;
mem1[0] = 8'h0;
mem2[0] = 8'h0;
mem3[0] = 8'h0;
end
always @(posedge aclk or negedge rst_l) begin
if (!rst_l) begin
rvalid <= 0;
bvalid <= 0;
end else begin
bid <= awid;
rid <= arid;
rvalid <= arvalid;
bvalid <= awvalid;
rdata <= memdata;
end
end
always @(negedge aclk) begin
if (arvalid)
case (araddr[2:0])
3'h0: begin
memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
end
3'h1: begin
memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
end
3'h2: begin
memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
end
3'h3: begin
memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
end
3'h4: begin
memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
end
3'h5: begin
memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
end
3'h6: begin
memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
end
3'h7: begin
memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
end
endcase
if (awvalid) begin
case (awaddr[2:0])
3'h0: begin
if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
end
3'h1: begin
if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
end
3'h2: begin
if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
end
3'h3: begin
if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
end
3'h4: begin
if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
end
3'h5: begin
if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
end
3'h6: begin
if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
end
3'h7: begin
if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
end
endcase
end
end
assign arready = 1'b1;
assign awready = 1'b1;
assign wready = 1'b1;
assign rresp = 2'b0;
assign bresp = 2'b0;
assign rlast = 1'b1;
endmodule
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