156 lines
6.7 KiB
Plaintext
156 lines
6.7 KiB
Plaintext
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#############################################################################################
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# For Upper Level Flatten STA: set parent_path, e.g. "soc_top/aaa_top/bbb_top/"
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# set cpu clock name of current chip, e.g. PLL_DIV_CLK_4
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# Keep Default Settings for Block-Level Implementation
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#############################################################################################
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if {![info exist parent_path]} { set parent_path "" } ;# Default ""
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if {![info exist APB_CLK_NAME]} { set APB_CLK_NAME SYS_APB_CLK } ;# Default SYS_APB_CLK
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if {![info exist JTG_CLK_NAME]} { set JTG_CLK_NAME JTG_CLK } ;# Default JTG_CLK
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################################################################################
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# Initial variables for synthesis; modify this part based on design
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################################################################################
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set IF_READ_BUIDIN_VARIABLES 0 ;# For standalone usage, set to "1" ; For synthesis, set to "0"
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set SYS_APB_SYNC 0 ; # For sync apb set to "1", for async apb set to "0"
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set CPU_PERIOD [expr (1000.00/1000)] ;# CPU is constrained at 1.0GHz
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set JTG_PERIOD [expr (1000.00/50)] ;# JTG is constrained at 50MHz
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if {$IF_READ_BUIDIN_VARIABLES} {
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set SETUP_UNCERTAINTY 0.2
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set HOLD_UNCERTAINTY 0.08
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set MAX_FANOUT 32
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set MAX_TRANSITION 0.5
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set LOAD_PIN "AN2D2BWP12T30P140/A1"
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set DRIVING_CELL "BUFFD2BWP12T30P140"
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}
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#################################################################################
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# Proc Used in this File
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#################################################################################
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proc list_add_prefix {input_list prefix} {
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set output_list ""
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foreach element $input_list {
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lappend output_list ${prefix}${element}
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}
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return "$output_list"
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}
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proc get_args_port_pin {input_list} {
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if {[string match */* $input_list]} {
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return "-through \[get_pins \{$input_list\}\]"
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} elseif {[string match *in* [get_attribute [get_ports [lindex $input_list 0]] direction]]} {
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return "-from \[get_ports \{$input_list\}\]"
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} elseif {[string match *out* [get_attribute [get_ports [lindex $input_list 0]] direction]]} {
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return "-to \[get_ports \{$input_list\}\]"
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} else {
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echo "! port_pin_list check failed for $input_list, mixing inputs, outputs, or pins is not allowed"
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}
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}
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if {$synopsys_program_name=="pt_shell"} {
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proc get_flat_pins {arg} {
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get_pins -hier -filter "is_hierarchical==false && full_name=~$arg"
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}
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proc get_flat_cells {arg} {
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get_cells -hier -filter "is_hierarchical==false && full_name=~$arg"
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}
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}
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#################################################################################
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# Basic Constraints
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#################################################################################
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if {$parent_path==""} {
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set SYS_APB_PERIOD [expr $CPU_PERIOD * 2.0]
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set CLK_INPUTS [get_ports {*clk *clock *tck}]
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set DATA_INPUTS [remove_from_collection [all_inputs] $CLK_INPUTS]
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set_max_fanout $MAX_FANOUT [current_design]
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set_max_transition $MAX_TRANSITION [current_design]
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set_input_transition 0.1 $CLK_INPUTS
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set_load [expr [load_of [get_lib_pins */$LOAD_PIN]]*5.0] [all_outputs]
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set_driving_cell -lib_cell $DRIVING_CELL $DATA_INPUTS
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create_clock [get_ports sys_apb_clk] -name $APB_CLK_NAME -period $SYS_APB_PERIOD
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create_clock [get_ports pad_tdt_dtm_tclk] -name $JTG_CLK_NAME -period $JTG_PERIOD
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create_clock -name V_SYS_APB_CLK -period $SYS_APB_PERIOD
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create_clock -name V_JTG_CLK -period $JTG_PERIOD
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set_max_delay [expr $SYS_APB_PERIOD] ignore_clock_latency \
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-from [get_clocks [list $APB_CLK_NAME V_SYS_APB_CLK]] \
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-to [get_clocks [list $JTG_CLK_NAME V_JTG_CLK]]
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set_max_delay [expr $SYS_APB_PERIOD] ignore_clock_latency \
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-from [get_clocks [list $JTG_CLK_NAME V_JTG_CLK]] \
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-to [get_clocks [list $APB_CLK_NAME V_SYS_APB_CLK]]
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set_false_path -hold -from [get_clocks [list $APB_CLK_NAME V_SYS_APB_CLK]] \
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-to [get_clocks [list $JTG_CLK_NAME V_JTG_CLK]]
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set_false_path -hold -from [get_clocks [list $JTG_CLK_NAME V_JTG_CLK]] \
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-to [get_clocks [list $APB_CLK_NAME V_SYS_APB_CLK]]
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}
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################################################################################
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# Ports Constrains
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################################################################################
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### JTG Ports
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set JTG_INPUTS {pad_tdt_dtm_*}
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set JTG_OUTPUTS {tdt_dtm_pad_t*}
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if {$parent_path==""} {
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set_input_delay -max [expr $JTG_PERIOD*0.9] -clock V_JTG_CLK [get_ports $JTG_INPUTS]
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set_input_delay -min 0 -clock V_JTG_CLK [get_ports $JTG_INPUTS]
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set_output_delay -max [expr $JTG_PERIOD*0.9] -clock V_JTG_CLK [get_ports $JTG_OUTPUTS] -clock_fall
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set_output_delay -min 0 -clock V_JTG_CLK [get_ports $JTG_OUTPUTS] -clock_fall
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}
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### SYS APB Ports
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set APB_INPUTS [remove_from_collection $DATA_INPUTS [get_ports $JTG_INPUTS]]
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set APB_OUTPUTS [remove_from_collection [all_outputs] [get_ports $JTG_OUTPUTS]]
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if {$parent_path==""} {
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set_input_delay -max [expr $SYS_APB_PERIOD*0.6] -clock V_SYS_APB_CLK [get_ports $APB_INPUTS]
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set_input_delay -min 0 -clock V_SYS_APB_CLK [get_ports $APB_INPUTS]
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set_output_delay -max [expr $SYS_APB_PERIOD*0.6] -clock V_SYS_APB_CLK [get_ports $APB_OUTPUTS]
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set_output_delay -min 0 -clock V_SYS_APB_CLK [get_ports $APB_OUTPUTS]
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}
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################################################################################
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# Group Path
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################################################################################
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if {$parent_path!=""} { return }
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unset parent_path
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group_path -name INPUT -from [all_inputs]
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group_path -name OUTPUT -to [all_outputs]
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group_path -name COMBO -from [all_inputs] -to [all_outputs]
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set_clock_uncertainty -setup $SETUP_UNCERTAINTY [all_clocks]
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set_clock_uncertainty -hold $HOLD_UNCERTAINTY [all_clocks]
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################################################################################
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# Set DFT Signals
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################################################################################
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set_case_analysis 0 [get_ports pad_tdt_icg_scan_en]
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set_case_analysis 0 [get_ports pad_yy_scan_mode
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