59 lines
1.6 KiB
Makefile
59 lines
1.6 KiB
Makefile
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export CODE_BASE_PATH = ${PWD}/../../E906_RTL_FACTORY
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GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
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FILELIST = -F ./dpi/jtag.fl ../Murax.v
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DEMODIR = ${PWD}
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TEST = sim
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
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# -O2 for faster runtime (slower compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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# Targets
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all: clean verilator
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clean:
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rm -rf obj_dir
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##################### Verilog Builds #####################################
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verilator-build:
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verilator --cc -CFLAGS ${CFLAGS} \
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-Wno-UNOPTFLAT \
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-Wno-STMTDLY \
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-Wno-MULTIDRIVEN \
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-Wno-CASEINCOMPLETE \
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-Wno-COMBDLY \
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-Wno-LATCH \
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-Wno-WIDTH \
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-Wno-IMPLICIT \
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${FILELIST} \
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soc_sim.v \
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--trace \
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--top-module soc_sim -exe test_soc_sim.cpp --autoflush
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cp ${DEMODIR}/test_soc_sim.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
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##################### Simulation Runs #####################################
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verilator: verilator-build
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./obj_dir/Vsoc_sim
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##################### openocd #####################################
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openocd:
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openocd -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg
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# openocd -f riscv.cfg
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# openocd -f riscv.cfg -d3
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gdb:
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$(GDB_PREFIX) -x gdbinit ./hello_world.elf
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help:
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@echo Possible targets: verilator help clean all verilator-build program.hex
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.PHONY: help clean verilator
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