Remove spurious carriage return characters.
This commit is contained in:
Joseph Rahmeh
parent
5990932214
commit
0f3f246df5
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@ -1,65 +1,65 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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// This module Synchronizes the signals between JTAG (TCK) and
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// processor (clk)
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//
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//-------------------------------------------------------------------------------------
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module dmi_jtag_to_core_sync (
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// JTAG signals
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input rd_en, // 1 bit Read Enable
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input wr_en, // 1 bit Write enable
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// Processor Signals
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input rst_n, // Core clock
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input clk, // Core reset
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output reg_en, // 1 bit Write interface bit to Processor
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output reg_wr_en // 1 bit Write enable to Processor
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);
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wire c_rd_en;
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wire c_wr_en;
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//Assign statements
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assign reg_en = c_wr_en | c_rd_en;
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assign reg_wr_en = c_wr_en;
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reg [2:0] rden, wren;
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// synchronizers
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always @ ( posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rden <= '0;
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wren <= '0;
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end
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else begin
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rden <= {rden[1:0], rd_en};
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wren <= {wren[1:0], wr_en};
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end
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end
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assign c_rd_en = rden[1] & ~rden[2];
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assign c_wr_en = wren[1] & ~wren[2];
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endmodule
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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// This module Synchronizes the signals between JTAG (TCK) and
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// processor (clk)
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//
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//-------------------------------------------------------------------------------------
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module dmi_jtag_to_core_sync (
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// JTAG signals
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input rd_en, // 1 bit Read Enable
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input wr_en, // 1 bit Write enable
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// Processor Signals
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input rst_n, // Core clock
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input clk, // Core reset
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output reg_en, // 1 bit Write interface bit to Processor
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output reg_wr_en // 1 bit Write enable to Processor
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);
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wire c_rd_en;
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wire c_wr_en;
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//Assign statements
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assign reg_en = c_wr_en | c_rd_en;
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assign reg_wr_en = c_wr_en;
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reg [2:0] rden, wren;
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// synchronizers
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always @ ( posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rden <= '0;
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wren <= '0;
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end
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else begin
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rden <= {rden[1:0], rd_en};
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wren <= {wren[1:0], wr_en};
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end
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end
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assign c_rd_en = rden[1] & ~rden[2];
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assign c_wr_en = wren[1] & ~wren[2];
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endmodule
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@ -1,91 +1,91 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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//
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// Copyright Western Digital, 2019
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// Owner : Anusha Narayanamoorthy
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// Description:
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// Wrapper module for JTAG_TAP and DMI synchronizer
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//
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//-------------------------------------------------------------------------------------
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module dmi_wrapper(
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input scan_mode, // scan mode
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// JTAG signals
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input trst_n, // JTAG reset
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input tck, // JTAG clock
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input tms, // Test mode select
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input tdi, // Test Data Input
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output tdo, // Test Data Output
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output tdoEnable, // Test Data Output enable
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// Processor Signals
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input core_rst_n, // Core reset
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input core_clk, // Core clock
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input [31:1] jtag_id, // JTAG ID
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input [31:0] rd_data, // 32 bit Read data from Processor
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output [31:0] reg_wr_data, // 32 bit Write data to Processor
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output [6:0] reg_wr_addr, // 7 bit reg address to Processor
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output reg_en, // 1 bit Read enable to Processor
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output reg_wr_en, // 1 bit Write enable to Processor
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output dmi_hard_reset
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);
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//Wire Declaration
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wire rd_en;
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wire wr_en;
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wire dmireset;
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//jtag_tap instantiation
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rvjtag_tap i_jtag_tap(
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.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
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.tck(tck), // dedicated JTAG TCK pad signal
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.tms(tms), // dedicated JTAG TMS pad signal
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.tdi(tdi), // dedicated JTAG TDI pad signal
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.tdo(tdo), // dedicated JTAG TDO pad signal
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.tdoEnable(tdoEnable), // enable for TDO pad
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.wr_data(reg_wr_data), // 32 bit Write data
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.wr_addr(reg_wr_addr), // 7 bit Write address
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.rd_en(rd_en), // 1 bit read enable
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.wr_en(wr_en), // 1 bit Write enable
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.rd_data(rd_data), // 32 bit Read data
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.rd_status(2'b0),
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.idle(3'h0), // no need to wait to sample data
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.dmi_stat(2'b0), // no need to wait or error possible
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.version(4'h1), // debug spec 0.13 compliant
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.jtag_id(jtag_id),
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.dmi_hard_reset(dmi_hard_reset),
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.dmi_reset(dmireset)
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);
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// dmi_jtag_to_core_sync instantiation
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dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
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.wr_en(wr_en), // 1 bit Write enable
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.rd_en(rd_en), // 1 bit Read enable
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.rst_n(core_rst_n),
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.clk(core_clk),
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.reg_en(reg_en), // 1 bit Write interface bit
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.reg_wr_en(reg_wr_en) // 1 bit Write enable
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);
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endmodule
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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//
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// Copyright Western Digital, 2019
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// Owner : Anusha Narayanamoorthy
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// Description:
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// Wrapper module for JTAG_TAP and DMI synchronizer
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//
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//-------------------------------------------------------------------------------------
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module dmi_wrapper(
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input scan_mode, // scan mode
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// JTAG signals
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input trst_n, // JTAG reset
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input tck, // JTAG clock
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input tms, // Test mode select
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input tdi, // Test Data Input
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output tdo, // Test Data Output
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output tdoEnable, // Test Data Output enable
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// Processor Signals
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input core_rst_n, // Core reset
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input core_clk, // Core clock
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input [31:1] jtag_id, // JTAG ID
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input [31:0] rd_data, // 32 bit Read data from Processor
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output [31:0] reg_wr_data, // 32 bit Write data to Processor
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output [6:0] reg_wr_addr, // 7 bit reg address to Processor
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output reg_en, // 1 bit Read enable to Processor
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output reg_wr_en, // 1 bit Write enable to Processor
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output dmi_hard_reset
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);
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//Wire Declaration
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wire rd_en;
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wire wr_en;
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wire dmireset;
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//jtag_tap instantiation
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rvjtag_tap i_jtag_tap(
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.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
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.tck(tck), // dedicated JTAG TCK pad signal
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.tms(tms), // dedicated JTAG TMS pad signal
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.tdi(tdi), // dedicated JTAG TDI pad signal
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.tdo(tdo), // dedicated JTAG TDO pad signal
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.tdoEnable(tdoEnable), // enable for TDO pad
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.wr_data(reg_wr_data), // 32 bit Write data
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.wr_addr(reg_wr_addr), // 7 bit Write address
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.rd_en(rd_en), // 1 bit read enable
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.wr_en(wr_en), // 1 bit Write enable
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.rd_data(rd_data), // 32 bit Read data
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.rd_status(2'b0),
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.idle(3'h0), // no need to wait to sample data
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.dmi_stat(2'b0), // no need to wait or error possible
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.version(4'h1), // debug spec 0.13 compliant
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.jtag_id(jtag_id),
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.dmi_hard_reset(dmi_hard_reset),
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.dmi_reset(dmireset)
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);
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// dmi_jtag_to_core_sync instantiation
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dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
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.wr_en(wr_en), // 1 bit Write enable
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.rd_en(rd_en), // 1 bit Read enable
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.rst_n(core_rst_n),
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.clk(core_clk),
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.reg_en(reg_en), // 1 bit Write interface bit
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.reg_wr_en(reg_wr_en) // 1 bit Write enable
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);
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endmodule
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@ -1,7 +1,7 @@
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@00001000
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48
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65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20
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53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
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@00001000
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48
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65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20
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53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
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@ -1,6 +1,6 @@
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@00000000
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73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
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B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0
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17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
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05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
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51 00 E3 0A 00 FE
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@00000000
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73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
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B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0
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17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
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05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
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51 00 E3 0A 00 FE
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