Enable demo openocd and gdb.

opene906/demo/sim/Makefile

@@ -69,6 +69,7 @@ program.hex: $(TEST).o $(LINK)
 
 openocd:
 	openocd -f riscv.cfg
+# openocd -f riscv.cfg -d3
 
 gdb:
 	$(GDB_PREFIX) -x gdbinit ./build/$(TEST).bin

opene906/demo/sim/dpi/jtagdpi/jtagdpi.c

@@ -65,16 +65,21 @@ static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
   bool act_send_resp = false;
   bool act_quit = false;
 
+  // // Use for debug jtag signal
+  // if ((((cmd - '0') >> 2) & 0x1) == 0x1 && (ctx->tck) == 0x0) {
+  //   char tdo_ascii = ctx->tdo + '0';
+  //   std::cout << "AAAAAA  tms " << (int)(((cmd - '0') >> 1) & 0x1) << "  tdi
+  //   "
+  //             << (int)(((cmd - '0') >> 0) & 0x1) << "  tdo " << tdo_ascii
+  //             << std::endl;
+  // }
+
   // parse received command byte
   if (cmd >= '0' && cmd <= '7') {
     // JTAG write
     char cmd_bit = cmd - '0';
     ctx->tdi = (cmd_bit >> 0) & 0x1;
     ctx->tms = (cmd_bit >> 1) & 0x1;
-
-    std::cout << "AAAAAA           tdi " << (int)(ctx->tdi) << std::endl;
-    std::cout << "AAAAAA tms " << (int)(ctx->tms) << std::endl;
-
     ctx->tck = (cmd_bit >> 2) & 0x1;
   } else if (cmd >= 'r' && cmd <= 'u') {
     // JTAG reset (active high from OpenOCD)
@@ -101,7 +106,6 @@ static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
   // send tdo as response
   if (act_send_resp) {
     char tdo_ascii = ctx->tdo + '0';
-    std::cout << "AAAAAA                            tdo " << tdo_ascii << std::endl;
     tcp_server_write(ctx->sock, tdo_ascii);
   }
 

opene906/demo/sim/dpi/jtagdpi/jtagdpi.sv

@@ -32,6 +32,8 @@ module jtagdpi #(
     input bit tdo
   );
 
+  reg [2:0] plit;
+
   import "DPI-C" function void jtagdpi_close(input chandle ctx);
 
   chandle ctx;
@@ -45,7 +47,9 @@ module jtagdpi #(
     ctx = 0;
   end
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i) plit <= plit + 1'b1;
+
+  always_ff @(posedge plit[2], negedge rst_ni) begin
     jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
                  jtag_tdo);
   end

opene906/demo/sim/riscv.cfg

@@ -2,6 +2,10 @@
 # speaking the remote_bitbang protocol. The adapter is implemented as 
 # SystemVerilog DPI module.
 
+
+# reset_config srst_only # donot support TRST, use five tms=1
+# adapter_nsrst_assert_width 100
+
 adapter driver remote_bitbang
 remote_bitbang host localhost
 remote_bitbang port 44853
@@ -9,10 +13,11 @@ remote_bitbang port 44853
 # Target configuration for the riscv chip
 
 set  _CHIPNAME riscv
-set _TARGETNAME $_CHIPNAME.cpu
-
-jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 01
 set _TARGETNAME $_CHIPNAME.tap
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F
+# {4'h1, 16'h0, 12'b1011_011_0111_1};
+
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME 
 
 # Configure work area in on-chip SRAM

opene906/demo/sim/soc_sim.v

@@ -14,6 +14,28 @@
 // limitations under the License.
 //
 
+
+`define E906
+// `define SOC_TOP       tb.x_soc
+// `define RTL_MEM       tb.x_soc.x_smem_ctrl
+// `define ISA_MEM       tb.x_pa_isa
+`define JTAG_5
+
+`define IAHB_LITE
+`define RTL_IAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_iahb_mem_ctrl
+
+`define DAHB_LITE
+`define RTL_DAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_dahb_mem_ctrl
+
+// `define CLK_PERIOD          10
+// `define TCLK_PERIOD         33
+// `define MAX_RUN_TIME        700000000
+// `define clk           tb.clk
+// `define rst_b         tb.rst_b
+// `include "../cpu/environment.h"
+// `timescale 1ns/100ps
+
+
 module soc_sim (
     input  bit clk,
     output     jtag_tdo,
@@ -24,19 +46,60 @@ module soc_sim (
 
   wire        rst;
 
-  bit  [31:0] cycleCnt;
+  bit  [63:0] cycleCnt;
 
   reg         uart_tx;
   wire        uart_rx;
   wire [ 7:0] gpioa;
 
-  reg         jrst_b;
+  wire        jrst_b;
-  reg         nrst_b;
+  wire        nrst_b;
 
   wire [ 7:0] WriteData;
 
   parameter MAX_CYCLES = 10_000_000_0;
 
+  assign rst = cycleCnt > 30 || cycleCnt < 10;
+  assign jrst_b = cycleCnt > 30 || cycleCnt < 10;  // Very important
+  assign nrst_b = cycleCnt > 30 || cycleCnt < 10;
+
+  ///////////////////////////////////////
+  // Memory Initialization  
+  ///////////////////////////////////////
+  integer i;
+  // reg [31:0] mem_data_size;
+  // reg [31:0] mem_inst_size;
+
+  reg [31:0] mem_inst_temp[65536];
+  // reg [31:0] mem_data_temp[65536];
+
+  initial begin
+    $display("\t******START TO LOAD PROGRAM******\n");
+    $readmemh("../work/case.pat", mem_inst_temp);
+    // $readmemh("./data.pat", mem_data_temp);
+
+    for (i = 0; i < 65536; i = i + 1) begin
+      `RTL_IAHBL_MEM.ram0.mem[i][7:0] = ((^mem_inst_temp[i][31:24]) === 1'bx ) ? 8'b0:mem_inst_temp[i][31:24];
+      `RTL_IAHBL_MEM.ram1.mem[i][7:0] = ((^mem_inst_temp[i][23:16]) === 1'bx ) ? 8'b0:mem_inst_temp[i][23:16];
+      `RTL_IAHBL_MEM.ram2.mem[i][7:0] = ((^mem_inst_temp[i][15: 8]) === 1'bx ) ? 8'b0:mem_inst_temp[i][15: 8];
+      `RTL_IAHBL_MEM.ram3.mem[i][7:0] = ((^mem_inst_temp[i][ 7: 0]) === 1'bx ) ? 8'b0:mem_inst_temp[i][ 7: 0];
+    end
+
+    for (i = 0; i <= 65536; i = i + 1) begin
+      `RTL_DAHBL_MEM.ram0.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram1.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram2.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram3.mem[i][7:0] = 8'b0;
+    end
+    for (i = 0; i <= 65536; i = i + 1) begin
+      `RTL_DAHBL_MEM.ram4.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram5.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram6.mem[i][7:0] = 8'b0;
+      `RTL_DAHBL_MEM.ram7.mem[i][7:0] = 8'b0;
+    end
+  end
+
+
   integer fd;
 
   always @(posedge clk) begin
@@ -62,24 +125,6 @@ module soc_sim (
     fd = $fopen("console.log", "w");
   end
 
-  initial begin
-    jrst_b = 1;
-    #100;
-    jrst_b = 0;
-    #100;
-    jrst_b = 1;
-  end
-
-  initial begin
-    nrst_b = 1;
-    #100;
-    nrst_b = 0;
-    #100;
-    nrst_b = 1;
-  end
-
-  assign rst = cycleCnt > 5;
-
   soc rvsoc (
       .i_pad_clk  (clk),
       .i_pad_rst_b(rst),

opene906/demo/sim/test_soc_sim.cpp

@@ -24,35 +24,37 @@
 #include "verilated_vcd_c.h"
 
 vluint64_t main_time = 0;
+const int isOpenDump = 0;
 
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv) {
   std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
 
-  Vsoc_sim* soc = new Vsoc_sim;
-
   Verilated::commandArgs(argc, argv);
-  // Verilated::mkdir("logs");
+  Vsoc_sim* soc = new Vsoc_sim;
-  Verilated::traceEverOn(true);
   VerilatedVcdC* tfp = new VerilatedVcdC;
+
+  if (isOpenDump) {
+    Verilated::traceEverOn(true);
     soc->trace(tfp, 99);
     tfp->open("vlt_dump.vcd");
+  }
 
   while (!Verilated::gotFinish()) {
     main_time += 5;
     soc->clk = !soc->clk;
     soc->eval();
 
+    if (isOpenDump) {
       tfp->dump(main_time);
-    // tfp->dump(soc->jtag_tdo,"tdo");
+    }
-    // tfp->dump(soc->jtag_tdi,"tdi");
-    // tfp->dump(soc->jtag_tms,"tms");
-    // tfp->dump(soc->jtag_tck,"tck");
   }
 
+  if (isOpenDump) {
     tfp->close();
-  // soc->final();
+  }
+  soc->final();
 
   std::cout << "\nVerilatorTB: End of sim" << std::endl;
   exit(EXIT_SUCCESS);

opene906/demo/sim/work/.gitignore

@@ -0,0 +1,5 @@
+*.o
+*.pat
+*.obj
+*.hex
+*.elf

opene906/demo/sim/work/E906_DEBUG_PATTERN.s

@@ -0,0 +1,25 @@
+/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+.global main
+
+main:
+
+csrsi mstatus, 0x8
+csrci 0x7C1, 0x1  # csrci mhcr, 0x1
+csrci 0x7C1, 0x2  # csrci mhcr, 0x2
+
+loop:
+ j loop
+

opene906/demo/sim/work/Makefile

@@ -0,0 +1,107 @@
+#/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
+#
+#Licensed under the Apache License, Version 2.0 (the "License");
+#you may not use this file except in compliance with the License.
+#You may obtain a copy of the License at
+#
+#    http://www.apache.org/licenses/LICENSE-2.0
+#
+#Unless required by applicable law or agreed to in writing, software
+#distributed under the License is distributed on an "AS IS" BASIS,
+#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#See the License for the specific language governing permissions and
+#limitations under the License.
+#*/
+#*/
+#*/
+# the compiler toolset setting
+
+TOOL_EXTENSION = /opt/riscv/bin
+
+CC      = ${TOOL_EXTENSION}/riscv64-unknown-elf-gcc
+AS      = ${TOOL_EXTENSION}/riscv64-unknown-elf-as
+LINK    = ${TOOL_EXTENSION}/riscv64-unknown-elf-ld
+OBJDUMP = ${TOOL_EXTENSION}/riscv64-unknown-elf-objdump
+OBJCOPY = ${TOOL_EXTENSION}/riscv64-unknown-elf-objcopy
+CONVERT =./Srec2vmem
+
+SSRC = $(wildcard *.S)
+sSRC = $(wildcard *.s)
+CSRC = $(wildcard *.c)
+
+OBJECTS = $(SSRC:%.S=%.o) $(sSRC:%.s=%.o) $(CSRC:%.c=%.o)
+
+CPU_ARCH_FLAG_0=e906f 
+CASENAME=debug 
+FILE=debug
+
+FLAG_MARCH = -mtune=e906 
+FLAG_MARCH += -march=rv32imafc
+FLAG_ABI   = -mabi=ilp32f
+
+CFLAGS = ${FLAG_MARCH} ${FLAG_ABI} 
+
+ifeq (${CASENAME}, coremark)
+  CFLAGS +=-c -v -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns --param max-rtl-if-conversion-unpredictable-cost=100 -msignedness-cmpiv -fno-code-hoisting -mno-thread-jumps1 -mno-iv-adjust-addr-cost -mno-expand-split-imm -fno-tree-loop-distribution
+else
+  CFLAGS += -c -v -O2
+endif
+
+LINKFLAGS = -Tlinker.lcf -nostartfiles ${FLAG_MARCH} ${FLAG_ABI}
+
+# LINKLIBS  = -L${TOOL_PATH}/lib/gcc/riscv64-unknown-elf/8.1.0/rv32imac
+# LINKLIBS += -L${TOOL_PATH}/riscv64-unknown-elf/lib/rv32imac
+# LINKLIBS += -L${TOOL_PATH}/riscv64-unknown-elf/lib
+
+LINKLIBS = -lc -lgcc
+
+OBJDUMPFLAGS = -S -Mnumeric
+
+HEXFLAGS	= -O srec
+
+%.o : %.c
+	${CC} -c ${CFLAGS} -o $@ $<
+
+%.o : %.s
+	${CC} -c ${CFLAGS} -o $@ $<
+
+%.o : %.S
+	${CC} -c ${CFLAGS} -o $@ $<
+
+${FILE}.elf : ${OBJECTS} linker.lcf
+	${CC} ${LINKFLAGS} ${LINKLIBS} ${OBJECTS} -o $@ -lm 
+
+${FILE}.obj : ${FILE}.elf
+	${OBJDUMP} ${OBJDUMPFLAGS} $< > $@
+
+INST_HEX = ${FILE}_inst.hex
+DATA_HEX = ${FILE}_data.hex
+FILE_HEX = ${FILE}.hex
+
+${FILE}.hex : ${FILE}.elf
+	${OBJCOPY} ${HEXFLAGS} $< ${INST_HEX} -j .text*  -j .rodata* -j .eh_frame*
+	${OBJCOPY} ${HEXFLAGS} $< ${DATA_HEX} -j .data*  -j .bss -j .COMMON
+	${OBJCOPY} ${HEXFLAGS} $< $@ 
+
+INST_PAT = inst.pat
+DATA_PAT = data.pat
+FILE_PAT = case.pat
+
+%.pat	: %.hex
+	rm -f *.pat
+	${CONVERT} ${INST_HEX} ${INST_PAT}
+	${CONVERT} ${DATA_HEX} ${DATA_PAT}
+	${CONVERT} ${FILE_HEX} ${FILE_PAT}
+
+
+#--------------------------------------------------------------------
+# target setting
+.PHONY :all
+all : ${FILE}.pat ${FILE}.hex ${FILE}.elf ${FILE}.obj
+
+#---------------------------------------------------------------------
+# clean some medium code and .pat
+.PHONY :clean 
+clean:
+	rm -rf *.o *.pat  *.obj *.hex
+

opene906/demo/sim/work/crt0.s

@@ -0,0 +1,177 @@
+/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+.text
+.global	__start
+__start:
+
+
+#enable btb & bht
+#  csrr x3, mhcr
+#  ori x3, x3, 0x20
+#  csrw mhcr, x3
+#
+#  li x3, 0x1000
+#  csrrs x0, mhcr, x3
+
+#la x3, 0x20000
+  la  x2, __kernel_stack
+#Init_Stack:
+#
+#  sw x0, 0(x2)
+#  addi x2, x2, -4
+#  addi x3, x3, -4
+#  bnez x3, Init_Stack
+
+  la x3, __erodata
+  la x4, __data_start__
+  la x5, __data_end__
+
+  sub x5, x5, x4
+  beqz x5, L_loop0_done
+
+L_loop0:
+   lw x6, 0(x3)
+   sw x6, 0(x4)
+   addi x3, x3, 0x4
+   addi x4, x4, 0x4
+   addi x5, x5, -4
+   bnez x5, L_loop0
+
+L_loop0_done:
+   la x3, __data_end__
+   la x4, __bss_end__
+
+   li x5, 0
+   sub x4, x4, x3
+   beqz x4, L_loop1_done
+
+L_loop1:
+   sw x5, 0(x3)
+   addi x3, x3, 0x4
+   addi x4, x4, -4
+   bnez x4, L_loop1  
+
+
+L_loop1_done:
+  
+  la x3, trap_handler
+  csrw mtvec, x3
+
+  la x3, vector_table
+  addi x3, x3, 64
+  csrw 0x307, x3  # csrw mtvt, x3
+
+
+  li a5, 0xeffff000
+  li a6, 0x20000
+  sw a6, 0(a5)
+  li a7, 0xc
+  sw a7, 4(a5)
+
+  li a6, 0x40000
+  li a7, 0xc
+  sw a6, 8(a5)
+  sw a7, 12(a5)
+  
+  li a6, 0x50000
+  li a7, 0x10
+  sw a6, 16(a5)
+  sw a7, 20(a5)
+
+  li a5, 0x40011000
+  li a6, 0xff
+  sw a6, 0(a5)
+  li a6, 0x3
+  sw a6, 8(a5)
+  lw a6, 4(a5)
+
+
+# enable mie
+  li   x3,0x88 
+  csrw mstatus,x3
+
+# enable fpu
+  li x3, 0x2000
+  csrs mstatus,x3
+
+  li   x3,0x103f
+  csrw 0x7C1,x3  # csrw mhcr,x3
+  li   x3,0x400c
+  csrw 0x7C5,x3  # csrw mhint,x3
+  
+__to_main:
+  jal main
+
+
+  .global __exit
+__exit:
+  fence.i
+  fence
+  li    x4, 0x6000fff8
+  addi  x3, x0,0xFF
+  slli  x3, x3,0x4
+  addi  x3, x3, 0xf #0xFFF
+  sw	x3, 0(x4)
+
+  .global __fail
+__fail:
+  fence.i
+  fence
+  li    x4, 0x6000fff8
+  addi  x3, x0,0xEE
+  slli  x3, x3,0x4
+  addi  x3, x3,0xe #0xEEE
+  sw	x3, 0(x4)
+
+  .align 6  
+  .global trap_handler
+trap_handler:
+  j __synchronous_exception
+  .align 2  
+  j __fail
+ 
+__synchronous_exception:
+  sw   x13,-4(x2)
+  sw   x14,-8(x2)
+  sw   x15,-12(x2)
+  csrr x14,mcause
+  andi x15,x14,0xff  #cause
+  srli x14,x14,0x1b   #int
+  andi x14,x14,0x10   #mask bit
+  add  x14,x14,x15    #{int,cause}
+
+  slli x14,x14,0x2  #offset
+  la   x15,vector_table
+  add  x15,x14,x15  #target pc
+  lw   x14, 0(x15)  #get exception addr
+  lw   x13, -4(x2)  #recover x16
+  lw   x15, -12(x2) #recover x15
+#addi x14,x14,-4
+  jr   x14
+
+
+  .global vector_table
+  .align  6
+vector_table:	#totally 256 entries
+	.rept   256
+	.long   __dummy
+	.endr
+
+  .global __dummy
+__dummy:  
+  j __fail
+  
+  .data
+  .long 0

opene906/demo/sim/work/linker.lcf

@@ -0,0 +1,55 @@
+/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+MEMORY
+{
+MEM1(RWX)  : ORIGIN = 0x00000004,  LENGTH = 0x40000
+MEM2(RWX)  : ORIGIN = 0x20000000,  LENGTH = 0xc0000
+}
+__kernel_stack = 0x200bfff8 ;
+
+ENTRY(__start)
+
+SECTIONS {
+    .text :
+    {
+        crt0.o (.text)
+        *(.text*)
+        . = ALIGN(0x10);
+    } >MEM1
+    .rodata :
+    {
+      *(.rodata*)
+          . = ALIGN(0x4);
+        __erodata = .;
+    } > MEM1
+    .data :
+    {
+      . = ALIGN(0x4);
+      __data_start__ = .;
+        *(.data*)
+        *(.eh_frame*)
+          . = ALIGN(0x4);
+        __data_end__ = .;
+    } >MEM2 AT > MEM1
+    .bss :
+    {
+      . = ALIGN(0x4);
+      __bss_start__ = .;
+        *(.bss)
+         . = ALIGN(0x4);
+        __bss_end__ = .;
+          *.(COMMON)
+    } >MEM2
+}