Enable demo openocd and gdb.
This commit is contained in:
colin
parent
1d7ba86749
commit
3258c057e3
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@ -69,6 +69,7 @@ program.hex: $(TEST).o $(LINK)
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openocd:
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openocd -f riscv.cfg
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# openocd -f riscv.cfg -d3
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gdb:
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$(GDB_PREFIX) -x gdbinit ./build/$(TEST).bin
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14026
opene906/demo/sim/a.log
14026
opene906/demo/sim/a.log
File diff suppressed because it is too large
Load Diff
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@ -65,16 +65,21 @@ static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
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bool act_send_resp = false;
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bool act_quit = false;
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// // Use for debug jtag signal
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// if ((((cmd - '0') >> 2) & 0x1) == 0x1 && (ctx->tck) == 0x0) {
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// char tdo_ascii = ctx->tdo + '0';
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// std::cout << "AAAAAA tms " << (int)(((cmd - '0') >> 1) & 0x1) << " tdi
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// "
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// << (int)(((cmd - '0') >> 0) & 0x1) << " tdo " << tdo_ascii
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// << std::endl;
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// }
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// parse received command byte
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if (cmd >= '0' && cmd <= '7') {
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// JTAG write
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char cmd_bit = cmd - '0';
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ctx->tdi = (cmd_bit >> 0) & 0x1;
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ctx->tms = (cmd_bit >> 1) & 0x1;
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std::cout << "AAAAAA tdi " << (int)(ctx->tdi) << std::endl;
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std::cout << "AAAAAA tms " << (int)(ctx->tms) << std::endl;
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ctx->tck = (cmd_bit >> 2) & 0x1;
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} else if (cmd >= 'r' && cmd <= 'u') {
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// JTAG reset (active high from OpenOCD)
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@ -101,7 +106,6 @@ static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
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// send tdo as response
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if (act_send_resp) {
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char tdo_ascii = ctx->tdo + '0';
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std::cout << "AAAAAA tdo " << tdo_ascii << std::endl;
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tcp_server_write(ctx->sock, tdo_ascii);
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}
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@ -32,6 +32,8 @@ module jtagdpi #(
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input bit tdo
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);
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reg [2:0] plit;
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import "DPI-C" function void jtagdpi_close(input chandle ctx);
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chandle ctx;
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@ -45,7 +47,9 @@ module jtagdpi #(
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ctx = 0;
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end
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always_ff @(posedge clk_i, negedge rst_ni) begin
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always_ff @(posedge clk_i) plit <= plit + 1'b1;
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always_ff @(posedge plit[2], negedge rst_ni) begin
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jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
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jtag_tdo);
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end
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@ -2,6 +2,10 @@
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# speaking the remote_bitbang protocol. The adapter is implemented as
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# SystemVerilog DPI module.
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# reset_config srst_only # donot support TRST, use five tms=1
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# adapter_nsrst_assert_width 100
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adapter driver remote_bitbang
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remote_bitbang host localhost
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remote_bitbang port 44853
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@ -9,10 +13,11 @@ remote_bitbang port 44853
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# Target configuration for the riscv chip
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set _CHIPNAME riscv
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set _TARGETNAME $_CHIPNAME.cpu
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 01
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set _TARGETNAME $_CHIPNAME.tap
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F
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# {4'h1, 16'h0, 12'b1011_011_0111_1};
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# Configure work area in on-chip SRAM
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@ -14,6 +14,28 @@
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// limitations under the License.
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//
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`define E906
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// `define SOC_TOP tb.x_soc
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// `define RTL_MEM tb.x_soc.x_smem_ctrl
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// `define ISA_MEM tb.x_pa_isa
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`define JTAG_5
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`define IAHB_LITE
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`define RTL_IAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_iahb_mem_ctrl
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`define DAHB_LITE
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`define RTL_DAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_dahb_mem_ctrl
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// `define CLK_PERIOD 10
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// `define TCLK_PERIOD 33
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// `define MAX_RUN_TIME 700000000
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// `define clk tb.clk
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// `define rst_b tb.rst_b
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// `include "../cpu/environment.h"
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// `timescale 1ns/100ps
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module soc_sim (
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input bit clk,
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output jtag_tdo,
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@ -24,19 +46,60 @@ module soc_sim (
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wire rst;
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bit [31:0] cycleCnt;
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bit [63:0] cycleCnt;
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reg uart_tx;
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wire uart_rx;
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wire [ 7:0] gpioa;
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reg jrst_b;
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reg nrst_b;
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wire jrst_b;
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wire nrst_b;
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wire [ 7:0] WriteData;
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parameter MAX_CYCLES = 10_000_000_0;
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assign rst = cycleCnt > 30 || cycleCnt < 10;
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assign jrst_b = cycleCnt > 30 || cycleCnt < 10; // Very important
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assign nrst_b = cycleCnt > 30 || cycleCnt < 10;
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///////////////////////////////////////
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// Memory Initialization
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///////////////////////////////////////
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integer i;
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// reg [31:0] mem_data_size;
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// reg [31:0] mem_inst_size;
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reg [31:0] mem_inst_temp[65536];
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// reg [31:0] mem_data_temp[65536];
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initial begin
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$display("\t******START TO LOAD PROGRAM******\n");
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$readmemh("../work/case.pat", mem_inst_temp);
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// $readmemh("./data.pat", mem_data_temp);
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for (i = 0; i < 65536; i = i + 1) begin
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`RTL_IAHBL_MEM.ram0.mem[i][7:0] = ((^mem_inst_temp[i][31:24]) === 1'bx ) ? 8'b0:mem_inst_temp[i][31:24];
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`RTL_IAHBL_MEM.ram1.mem[i][7:0] = ((^mem_inst_temp[i][23:16]) === 1'bx ) ? 8'b0:mem_inst_temp[i][23:16];
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`RTL_IAHBL_MEM.ram2.mem[i][7:0] = ((^mem_inst_temp[i][15: 8]) === 1'bx ) ? 8'b0:mem_inst_temp[i][15: 8];
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`RTL_IAHBL_MEM.ram3.mem[i][7:0] = ((^mem_inst_temp[i][ 7: 0]) === 1'bx ) ? 8'b0:mem_inst_temp[i][ 7: 0];
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end
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for (i = 0; i <= 65536; i = i + 1) begin
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`RTL_DAHBL_MEM.ram0.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram1.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram2.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram3.mem[i][7:0] = 8'b0;
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end
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for (i = 0; i <= 65536; i = i + 1) begin
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`RTL_DAHBL_MEM.ram4.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram5.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram6.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram7.mem[i][7:0] = 8'b0;
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end
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end
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integer fd;
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always @(posedge clk) begin
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@ -62,24 +125,6 @@ module soc_sim (
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fd = $fopen("console.log", "w");
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end
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initial begin
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jrst_b = 1;
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#100;
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jrst_b = 0;
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#100;
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jrst_b = 1;
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end
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initial begin
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nrst_b = 1;
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#100;
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nrst_b = 0;
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#100;
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nrst_b = 1;
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end
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assign rst = cycleCnt > 5;
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soc rvsoc (
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.i_pad_clk (clk),
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.i_pad_rst_b(rst),
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@ -24,35 +24,37 @@
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#include "verilated_vcd_c.h"
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vluint64_t main_time = 0;
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const int isOpenDump = 0;
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv) {
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std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
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Vsoc_sim* soc = new Vsoc_sim;
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Verilated::commandArgs(argc, argv);
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// Verilated::mkdir("logs");
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Verilated::traceEverOn(true);
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Vsoc_sim* soc = new Vsoc_sim;
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VerilatedVcdC* tfp = new VerilatedVcdC;
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soc->trace(tfp, 99);
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tfp->open("vlt_dump.vcd");
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if (isOpenDump) {
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Verilated::traceEverOn(true);
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soc->trace(tfp, 99);
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tfp->open("vlt_dump.vcd");
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}
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while (!Verilated::gotFinish()) {
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main_time += 5;
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soc->clk = !soc->clk;
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soc->eval();
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tfp->dump(main_time);
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// tfp->dump(soc->jtag_tdo,"tdo");
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// tfp->dump(soc->jtag_tdi,"tdi");
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// tfp->dump(soc->jtag_tms,"tms");
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// tfp->dump(soc->jtag_tck,"tck");
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if (isOpenDump) {
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tfp->dump(main_time);
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}
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}
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tfp->close();
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// soc->final();
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if (isOpenDump) {
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tfp->close();
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}
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soc->final();
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std::cout << "\nVerilatorTB: End of sim" << std::endl;
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exit(EXIT_SUCCESS);
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@ -0,0 +1,5 @@
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*.o
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*.pat
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*.obj
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*.hex
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*.elf
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@ -0,0 +1,25 @@
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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.global main
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main:
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csrsi mstatus, 0x8
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csrci 0x7C1, 0x1 # csrci mhcr, 0x1
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csrci 0x7C1, 0x2 # csrci mhcr, 0x2
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loop:
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j loop
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@ -0,0 +1,107 @@
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#/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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#
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#Licensed under the Apache License, Version 2.0 (the "License");
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#you may not use this file except in compliance with the License.
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#You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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#Unless required by applicable law or agreed to in writing, software
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#distributed under the License is distributed on an "AS IS" BASIS,
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#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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#See the License for the specific language governing permissions and
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#limitations under the License.
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#*/
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#*/
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#*/
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# the compiler toolset setting
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TOOL_EXTENSION = /opt/riscv/bin
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CC = ${TOOL_EXTENSION}/riscv64-unknown-elf-gcc
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AS = ${TOOL_EXTENSION}/riscv64-unknown-elf-as
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LINK = ${TOOL_EXTENSION}/riscv64-unknown-elf-ld
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OBJDUMP = ${TOOL_EXTENSION}/riscv64-unknown-elf-objdump
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OBJCOPY = ${TOOL_EXTENSION}/riscv64-unknown-elf-objcopy
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CONVERT =./Srec2vmem
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SSRC = $(wildcard *.S)
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sSRC = $(wildcard *.s)
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CSRC = $(wildcard *.c)
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OBJECTS = $(SSRC:%.S=%.o) $(sSRC:%.s=%.o) $(CSRC:%.c=%.o)
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CPU_ARCH_FLAG_0=e906f
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CASENAME=debug
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FILE=debug
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FLAG_MARCH = -mtune=e906
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FLAG_MARCH += -march=rv32imafc
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FLAG_ABI = -mabi=ilp32f
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CFLAGS = ${FLAG_MARCH} ${FLAG_ABI}
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ifeq (${CASENAME}, coremark)
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CFLAGS +=-c -v -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns --param max-rtl-if-conversion-unpredictable-cost=100 -msignedness-cmpiv -fno-code-hoisting -mno-thread-jumps1 -mno-iv-adjust-addr-cost -mno-expand-split-imm -fno-tree-loop-distribution
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else
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CFLAGS += -c -v -O2
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endif
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LINKFLAGS = -Tlinker.lcf -nostartfiles ${FLAG_MARCH} ${FLAG_ABI}
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# LINKLIBS = -L${TOOL_PATH}/lib/gcc/riscv64-unknown-elf/8.1.0/rv32imac
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# LINKLIBS += -L${TOOL_PATH}/riscv64-unknown-elf/lib/rv32imac
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# LINKLIBS += -L${TOOL_PATH}/riscv64-unknown-elf/lib
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LINKLIBS = -lc -lgcc
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OBJDUMPFLAGS = -S -Mnumeric
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HEXFLAGS = -O srec
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%.o : %.c
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${CC} -c ${CFLAGS} -o $@ $<
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%.o : %.s
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${CC} -c ${CFLAGS} -o $@ $<
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%.o : %.S
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${CC} -c ${CFLAGS} -o $@ $<
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${FILE}.elf : ${OBJECTS} linker.lcf
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${CC} ${LINKFLAGS} ${LINKLIBS} ${OBJECTS} -o $@ -lm
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${FILE}.obj : ${FILE}.elf
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${OBJDUMP} ${OBJDUMPFLAGS} $< > $@
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INST_HEX = ${FILE}_inst.hex
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DATA_HEX = ${FILE}_data.hex
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FILE_HEX = ${FILE}.hex
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${FILE}.hex : ${FILE}.elf
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${OBJCOPY} ${HEXFLAGS} $< ${INST_HEX} -j .text* -j .rodata* -j .eh_frame*
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${OBJCOPY} ${HEXFLAGS} $< ${DATA_HEX} -j .data* -j .bss -j .COMMON
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${OBJCOPY} ${HEXFLAGS} $< $@
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INST_PAT = inst.pat
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DATA_PAT = data.pat
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FILE_PAT = case.pat
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%.pat : %.hex
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rm -f *.pat
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${CONVERT} ${INST_HEX} ${INST_PAT}
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${CONVERT} ${DATA_HEX} ${DATA_PAT}
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${CONVERT} ${FILE_HEX} ${FILE_PAT}
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#--------------------------------------------------------------------
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# target setting
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.PHONY :all
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all : ${FILE}.pat ${FILE}.hex ${FILE}.elf ${FILE}.obj
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#---------------------------------------------------------------------
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# clean some medium code and .pat
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.PHONY :clean
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clean:
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rm -rf *.o *.pat *.obj *.hex
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Binary file not shown.
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@ -0,0 +1,177 @@
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
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.text
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.global __start
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__start:
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#enable btb & bht
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# csrr x3, mhcr
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# ori x3, x3, 0x20
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# csrw mhcr, x3
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#
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# li x3, 0x1000
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# csrrs x0, mhcr, x3
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#la x3, 0x20000
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la x2, __kernel_stack
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#Init_Stack:
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#
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# sw x0, 0(x2)
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# addi x2, x2, -4
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# addi x3, x3, -4
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# bnez x3, Init_Stack
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la x3, __erodata
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la x4, __data_start__
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la x5, __data_end__
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sub x5, x5, x4
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beqz x5, L_loop0_done
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L_loop0:
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lw x6, 0(x3)
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sw x6, 0(x4)
|
||||
addi x3, x3, 0x4
|
||||
addi x4, x4, 0x4
|
||||
addi x5, x5, -4
|
||||
bnez x5, L_loop0
|
||||
|
||||
L_loop0_done:
|
||||
la x3, __data_end__
|
||||
la x4, __bss_end__
|
||||
|
||||
li x5, 0
|
||||
sub x4, x4, x3
|
||||
beqz x4, L_loop1_done
|
||||
|
||||
L_loop1:
|
||||
sw x5, 0(x3)
|
||||
addi x3, x3, 0x4
|
||||
addi x4, x4, -4
|
||||
bnez x4, L_loop1
|
||||
|
||||
|
||||
L_loop1_done:
|
||||
|
||||
la x3, trap_handler
|
||||
csrw mtvec, x3
|
||||
|
||||
la x3, vector_table
|
||||
addi x3, x3, 64
|
||||
csrw 0x307, x3 # csrw mtvt, x3
|
||||
|
||||
|
||||
li a5, 0xeffff000
|
||||
li a6, 0x20000
|
||||
sw a6, 0(a5)
|
||||
li a7, 0xc
|
||||
sw a7, 4(a5)
|
||||
|
||||
li a6, 0x40000
|
||||
li a7, 0xc
|
||||
sw a6, 8(a5)
|
||||
sw a7, 12(a5)
|
||||
|
||||
li a6, 0x50000
|
||||
li a7, 0x10
|
||||
sw a6, 16(a5)
|
||||
sw a7, 20(a5)
|
||||
|
||||
li a5, 0x40011000
|
||||
li a6, 0xff
|
||||
sw a6, 0(a5)
|
||||
li a6, 0x3
|
||||
sw a6, 8(a5)
|
||||
lw a6, 4(a5)
|
||||
|
||||
|
||||
# enable mie
|
||||
li x3,0x88
|
||||
csrw mstatus,x3
|
||||
|
||||
# enable fpu
|
||||
li x3, 0x2000
|
||||
csrs mstatus,x3
|
||||
|
||||
li x3,0x103f
|
||||
csrw 0x7C1,x3 # csrw mhcr,x3
|
||||
li x3,0x400c
|
||||
csrw 0x7C5,x3 # csrw mhint,x3
|
||||
|
||||
__to_main:
|
||||
jal main
|
||||
|
||||
|
||||
.global __exit
|
||||
__exit:
|
||||
fence.i
|
||||
fence
|
||||
li x4, 0x6000fff8
|
||||
addi x3, x0,0xFF
|
||||
slli x3, x3,0x4
|
||||
addi x3, x3, 0xf #0xFFF
|
||||
sw x3, 0(x4)
|
||||
|
||||
.global __fail
|
||||
__fail:
|
||||
fence.i
|
||||
fence
|
||||
li x4, 0x6000fff8
|
||||
addi x3, x0,0xEE
|
||||
slli x3, x3,0x4
|
||||
addi x3, x3,0xe #0xEEE
|
||||
sw x3, 0(x4)
|
||||
|
||||
.align 6
|
||||
.global trap_handler
|
||||
trap_handler:
|
||||
j __synchronous_exception
|
||||
.align 2
|
||||
j __fail
|
||||
|
||||
__synchronous_exception:
|
||||
sw x13,-4(x2)
|
||||
sw x14,-8(x2)
|
||||
sw x15,-12(x2)
|
||||
csrr x14,mcause
|
||||
andi x15,x14,0xff #cause
|
||||
srli x14,x14,0x1b #int
|
||||
andi x14,x14,0x10 #mask bit
|
||||
add x14,x14,x15 #{int,cause}
|
||||
|
||||
slli x14,x14,0x2 #offset
|
||||
la x15,vector_table
|
||||
add x15,x14,x15 #target pc
|
||||
lw x14, 0(x15) #get exception addr
|
||||
lw x13, -4(x2) #recover x16
|
||||
lw x15, -12(x2) #recover x15
|
||||
#addi x14,x14,-4
|
||||
jr x14
|
||||
|
||||
|
||||
.global vector_table
|
||||
.align 6
|
||||
vector_table: #totally 256 entries
|
||||
.rept 256
|
||||
.long __dummy
|
||||
.endr
|
||||
|
||||
.global __dummy
|
||||
__dummy:
|
||||
j __fail
|
||||
|
||||
.data
|
||||
.long 0
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
MEM1(RWX) : ORIGIN = 0x00000004, LENGTH = 0x40000
|
||||
MEM2(RWX) : ORIGIN = 0x20000000, LENGTH = 0xc0000
|
||||
}
|
||||
__kernel_stack = 0x200bfff8 ;
|
||||
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS {
|
||||
.text :
|
||||
{
|
||||
crt0.o (.text)
|
||||
*(.text*)
|
||||
. = ALIGN(0x10);
|
||||
} >MEM1
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
. = ALIGN(0x4);
|
||||
__erodata = .;
|
||||
} > MEM1
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.eh_frame*)
|
||||
. = ALIGN(0x4);
|
||||
__data_end__ = .;
|
||||
} >MEM2 AT > MEM1
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
. = ALIGN(0x4);
|
||||
__bss_end__ = .;
|
||||
*.(COMMON)
|
||||
} >MEM2
|
||||
}
|
||||
Loading…
Reference in New Issue