Correct blink and use sample blink code

fpga/blink/.gitignore

@@ -1,5 +1,5 @@
 *.svf 
 *.bit 
-*.cfg 
+blink.cfg 
 *.ys 
 *.json

fpga/blink/blink.v

@@ -1,25 +1,55 @@
-module rst_gen (
+// module rst_gen (
-	input 			clk_i,
+// 	input 			clk_i,
-	input 			rst_i,
+// 	input 			rst_i,
-	output			rst_o
+// 	output			rst_o
-);
+// );
 
-/* try to generate a reset */
+// /* try to generate a reset */
-reg [2:0]	rst_cpt;
+// reg [2:0]	rst_cpt;
-always @(posedge clk_i) begin
+// always @(posedge clk_i) begin
-	if (rst_i)
+// 	if (rst_i)
-		rst_cpt = 3'b0;
+// 		rst_cpt = 3'b0;
-	else begin
+// 	else begin
-		if (rst_cpt == 3'b100)
+// 		if (rst_cpt == 3'b100)
-			rst_cpt = rst_cpt;
+// 			rst_cpt = rst_cpt;
-		else
+// 		else
-			rst_cpt = rst_cpt + 3'b1;
+// 			rst_cpt = rst_cpt + 3'b1;
-	end
+// 	end
-end
+// end
 
-assign rst_o = !rst_cpt[2];
+// assign rst_o = !rst_cpt[2];
+
+// endmodule
+
+// module blink (
+//     input      clk_i,
+//     output reg led_o
+// );
+// localparam MAX = 2_500_000_0;
+// localparam WIDTH = $clog2(MAX);
+
+// wire rst_s;
+// wire clk_s;
+
+// assign clk_s = clk_i;
+// //pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));
+// rst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));
+
+// reg  [WIDTH-1:0] cpt_s;
+// wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
+
+// wire             end_s = cpt_s == MAX-1;
+
+// always @(posedge clk_s) begin
+//     cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;
+
+//     if (rst_s)
+//         led_o <= 1'b0;
+//     else if (end_s)
+//         led_o <= ~led_o;
+// end
+// endmodule
 
-endmodule
 
 module blink (
     input      clk_i,
@@ -28,24 +58,16 @@ module blink (
 localparam MAX = 2_500_000_0;
 localparam WIDTH = $clog2(MAX);
 
-wire rst_s;
 wire clk_s;
-
 assign clk_s = clk_i;
-//pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));
-rst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));
 
 reg  [WIDTH-1:0] cpt_s;
 wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
-
 wire             end_s = cpt_s == MAX-1;
 
 always @(posedge clk_s) begin
-    cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;
+	  cpt_s <= cpt_next_s;
-
+    if (end_s)
-    if (rst_s)
-        led_o <= 1'b0;
-    else if (end_s)
         led_o <= ~led_o;
 end
 endmodule

fpga/blink/cmsisdap.cfg

@@ -0,0 +1,28 @@
+#
+# Buspirate with OpenOCD support
+#
+# http://dangerousprototypes.com/bus-pirate-manual/
+#
+# http://www.fabienm.eu/flf/15-ecp5-board-kit/
+# https://github.com/Martoni/blp/tree/master/platforms/colorlight
+# https://github.com/HarmonInstruments/JTAG_SWD
+
+interface cmsis-dap
+transport select jtag
+
+adapter_khz 10000
+
+#jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
+
+#LFE5U-25F 0x41111043
+#LFE5U-45F 0x41112043
+jtag newtap ecp5 tap -irlen 8
+
+#init
+#scan_chain
+#
+#svf -tap ecp5.tap -quiet -progress blink.svf
+#exit
+
+# this depends on the cable, you are safe with this option
+#reset_config srst_only