colin
/
abstractaccelerator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Mention 1.1.1 release.

This commit is contained in:
Joseph Rahmeh 2019-08-10 13:23:53 -07:00
parent e7f57a0d5d
commit 40db638de6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -1,6 +1,6 @@
# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital # SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
This repository contains the SweRV Core<sup>TM</sup> 1.1 design RTL. The previous version can be found in [branch 1.0.](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) This repository contains the SweRV Core<sup>TM</sup> 1.1.1 design RTL. The previous version can be found in [branch 1.0](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) and [branch 1.1](https://github.com/chipsalliance/Cores-SweRV/tree/1.1)
The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M). The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
## License ## License