Removed duplicate declaration of finished for Verilator.

testbench/tb_top.sv

@@ -22,6 +22,7 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
 `ifndef VERILATOR
    logic                                reset_l;
    logic                                core_clk;
+   logic                                finished;
 `endif
    logic                                nmi_int;
 
@@ -100,7 +101,6 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
 
    logic        [31:0]                  cycleCnt       ;
    logic                                mailbox_data_val;
-   logic                                finished;
 
    wire                                 dma_hready_out;