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Cleanup release notes.

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Joseph Rahmeh 2020-02-19 07:07:31 -08:00
parent d0c6e56012
commit 480c765eb4
1 changed files with 15 additions and 15 deletions
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release-notes.md
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@ -15,36 +15,36 @@ is added to the SweRV core.
* Debug module failed to auto-increment register on system-bus access * Debug module failed to auto-increment register on system-bus access
of size 64-bit (reported by Codasip). of size 64-bit (reported by Codasip).
* The core_rst_n signal was incorrectly connected (reported by Codasip). * The core_rst_n signal was incorrectly connected (reported by Codasip).
* Moudule/instance renamed for tool compatibility. * Module/instance renamed for tool compatibility.
* The program counter was getting corrupted when the load/store unit * The program counter was getting corrupted when the load/store unit
indicated both a single-bit and a double-bit error in the same indicated both a single-bit and a double-bit error in the same
cycle. cycle.
* The MSTATUS control register was not being updated as expected when * The MSTATUS register was not being updated as expected when both a
both a non-maskable-interrupt and an MSTATUS-write happened in the non-maskable-interrupt and an MSTATUS-write happened in the same
same cycle. cycle.
* Write to SBDATA0 was not starting an system-bus write access when * Write to SBDATA0 was not starting a system-bus write access when
sbreadonaddr/sbreadondata is set. sbreadonaddr/sbreadondata is set.
* Minstret was incorrectly counting ecall/ebreak instructions * Minstret was incorrectly counting ecall/ebreak instructions.
* The dec_tlu_mpc_halted_only signal was not set for MPC halt after * The dec_tlu_mpc_halted_only signal was not set for MPC halt after
reset. reset.
* The MEPC control register was not being updated when a * The MEPC register was not being updated when a firmware-halt request
firmware-halt request was followed by a timer interrupt. was followed by a timer interrupt.
* The MINSTRETH control register was being incremented when * The MINSTRETH control register was being incremented when
performance counters were disabled. performance counters were disabled.
* Bus driver contained combinational logic from multiple clock * Bus driver contained combinational logic from multiple clock
domains that sometimes caused a glitch. domains that sometimes caused a glitch.
* System bus reads were always being made with 64-bit size for the * System bus reads were always being made with 64-bit size for the
AXI bus which is incorrect for IO access. AXI bus which is incorrect for IO access.
* DCCM single bit errors were counted for instruction that did not * DCCM single-bit errors were counted for instructions that did not
commit. commit.
* ICCM Single Bit Errors were double counted. * ICCM single bit errors were double-counted.
* Load/store unit was not detecting access faults when DCCM and PIC * Load/store unit was not detecting access faults when DCCM and PIC
memories are next to each other. memories are next to each other.
* Single bit ECC errors on data load were not always corrected in * Single-bit ECC errors on data load were not always corrected in
the DCCM. the DCCM.
* ECC single bit error were not always corrected in the DCCM for DMA * Single-bit ECC errors were not always corrected in the DCCM for DMA
access. accesses.
* Single bit Errors detected while reading ICCM through DMA were not * Single-bit errors detected while reading ICCM through DMA were not
being corrected in memory. being corrected in memory.
@ -61,7 +61,7 @@ is added to the SweRV core.
* Updated bus memory to be persistent and handle larger programs. * Updated bus memory to be persistent and handle larger programs.
* Makefile supports ability to run with source or pre-generated hex * Makefile supports ability to run with source or pre-generated hex
files. files.
* Makefile supports targets for coremarks benchmark (issue #25). * Makefile supports targets for CoreMarks benchmark (issue #25).
* Questa support in Makefile (Issue #19). * Questa support in Makefile (Issue #19).