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Format sv and v code.

This commit is contained in:
colin 2022-05-23 14:16:04 +00:00
parent 2f8715aeb6
commit 6bf845bb46
45 changed files with 21059 additions and 16680 deletions
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385
Flow/design/dbg/el2_dbg.sv
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@ -22,17 +22,17 @@
// Author :
//********************************************************************************
module el2_dbg
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
// outputs to the core for command and data interface
output logic [31:0] dbg_cmd_addr,
output logic [31:0] dbg_cmd_wrdata,
output logic dbg_cmd_valid,
output logic dbg_cmd_write, // 1: write command, 0: read_command
output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory
output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command
output logic [ 1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory
output logic [ 1:0] dbg_cmd_size, // size of the abstract mem access debug command
output logic dbg_core_rst_l, // core reset from dm
// inputs back from the core/dec
@ -54,7 +54,7 @@ import el2_pkg::*;
// inputs from the JTAG
input logic dmi_reg_en, // read or write
input logic [6:0] dmi_reg_addr, // address of DM register
input logic [ 6:0] dmi_reg_addr, // address of DM register
input logic dmi_reg_wr_en, // write instruction
input logic [31:0] dmi_reg_wdata, // write data
@ -65,20 +65,20 @@ import el2_pkg::*;
output logic sb_axi_awvalid,
input logic sb_axi_awready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
output logic [31:0] sb_axi_awaddr,
output logic [3:0] sb_axi_awregion,
output logic [7:0] sb_axi_awlen,
output logic [2:0] sb_axi_awsize,
output logic [1:0] sb_axi_awburst,
output logic [ 31:0] sb_axi_awaddr,
output logic [ 3:0] sb_axi_awregion,
output logic [ 7:0] sb_axi_awlen,
output logic [ 2:0] sb_axi_awsize,
output logic [ 1:0] sb_axi_awburst,
output logic sb_axi_awlock,
output logic [3:0] sb_axi_awcache,
output logic [2:0] sb_axi_awprot,
output logic [3:0] sb_axi_awqos,
output logic [ 3:0] sb_axi_awcache,
output logic [ 2:0] sb_axi_awprot,
output logic [ 3:0] sb_axi_awqos,
output logic sb_axi_wvalid,
input logic sb_axi_wready,
output logic [63:0] sb_axi_wdata,
output logic [7:0] sb_axi_wstrb,
output logic [ 7:0] sb_axi_wstrb,
output logic sb_axi_wlast,
input logic sb_axi_bvalid,
@ -89,20 +89,20 @@ import el2_pkg::*;
output logic sb_axi_arvalid,
input logic sb_axi_arready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
output logic [31:0] sb_axi_araddr,
output logic [3:0] sb_axi_arregion,
output logic [7:0] sb_axi_arlen,
output logic [2:0] sb_axi_arsize,
output logic [1:0] sb_axi_arburst,
output logic [ 31:0] sb_axi_araddr,
output logic [ 3:0] sb_axi_arregion,
output logic [ 7:0] sb_axi_arlen,
output logic [ 2:0] sb_axi_arsize,
output logic [ 1:0] sb_axi_arburst,
output logic sb_axi_arlock,
output logic [3:0] sb_axi_arcache,
output logic [2:0] sb_axi_arprot,
output logic [3:0] sb_axi_arqos,
output logic [ 3:0] sb_axi_arcache,
output logic [ 2:0] sb_axi_arprot,
output logic [ 3:0] sb_axi_arqos,
input logic sb_axi_rvalid,
output logic sb_axi_rready,
input logic [63:0] sb_axi_rdata,
input logic [1:0] sb_axi_rresp,
input logic [ 1:0] sb_axi_rresp,
input logic dbg_bus_clk_en,
@ -116,8 +116,30 @@ import el2_pkg::*;
);
typedef enum logic [3:0] {IDLE=4'h0, HALTING=4'h1, HALTED=4'h2, CORE_CMD_START=4'h3, CORE_CMD_WAIT=4'h4, SB_CMD_START=4'h5, SB_CMD_SEND=4'h6, SB_CMD_RESP=4'h7, CMD_DONE=4'h8, RESUMING=4'h9} state_t;
typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t;
typedef enum logic [3:0] {
IDLE = 4'h0,
HALTING = 4'h1,
HALTED = 4'h2,
CORE_CMD_START = 4'h3,
CORE_CMD_WAIT = 4'h4,
SB_CMD_START = 4'h5,
SB_CMD_SEND = 4'h6,
SB_CMD_RESP = 4'h7,
CMD_DONE = 4'h8,
RESUMING = 4'h9
} state_t;
typedef enum logic [3:0] {
SBIDLE = 4'h0,
WAIT_RD = 4'h1,
WAIT_WR = 4'h2,
CMD_RD = 4'h3,
CMD_WR = 4'h4,
CMD_WR_ADDR = 4'h5,
CMD_WR_DATA = 4'h6,
RSP_RD = 4'h7,
RSP_WR = 4'h8,
DONE = 4'h9
} sb_state_t;
state_t dbg_state;
state_t dbg_nxtstate;
@ -141,7 +163,14 @@ import el2_pkg::*;
logic abstractcs_busy_wren;
logic abstractcs_busy_din;
logic [2:0] abstractcs_error_din;
logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5, abstractcs_error_sel6;
logic
abstractcs_error_sel0,
abstractcs_error_sel1,
abstractcs_error_sel2,
abstractcs_error_sel3,
abstractcs_error_sel4,
abstractcs_error_sel5,
abstractcs_error_sel6;
logic dbg_sb_bus_error;
// abstractauto
logic abstractauto_reg_wren;
@ -165,13 +194,13 @@ import el2_pkg::*;
logic command_wren, command_regno_wren;
logic command_transfer_din;
logic command_postexec_din;
logic [31:0] command_din;
logic [3:0] dbg_cmd_addr_incr;
logic [31:0] dbg_cmd_curr_addr;
logic [31:0] dbg_cmd_next_addr;
logic [ 31:0] command_din;
logic [ 3:0] dbg_cmd_addr_incr;
logic [ 31:0] dbg_cmd_curr_addr;
logic [ 31:0] dbg_cmd_next_addr;
// needed to send the read data back for dmi reads
logic [31:0] dmi_reg_rdata_din;
logic [ 31:0] dmi_reg_rdata_din;
sb_state_t sb_state;
sb_state_t sb_nxtstate;
@ -185,7 +214,7 @@ import el2_pkg::*;
logic sbcs_sbbusyerror_din;
logic sbcs_sberror_wren;
logic [2:0] sbcs_sberror_din;
logic [ 2:0] sbcs_sberror_din;
logic sbcs_unaligned;
logic sbcs_illegal_size;
logic [19:15] sbcs_reg_int;
@ -194,18 +223,18 @@ import el2_pkg::*;
logic sbdata0_reg_wren0;
logic sbdata0_reg_wren1;
logic sbdata0_reg_wren;
logic [31:0] sbdata0_din;
logic [ 31:0] sbdata0_din;
logic sbdata1_reg_wren0;
logic sbdata1_reg_wren1;
logic sbdata1_reg_wren;
logic [31:0] sbdata1_din;
logic [ 31:0] sbdata1_din;
logic sbaddress0_reg_wren0;
logic sbaddress0_reg_wren1;
logic sbaddress0_reg_wren;
logic [31:0] sbaddress0_reg_din;
logic [3:0] sbaddress0_incr;
logic [ 31:0] sbaddress0_reg_din;
logic [ 3:0] sbaddress0_incr;
logic sbreadonaddr_access;
logic sbreadondata_access;
logic sbdata0wr_access;
@ -220,11 +249,11 @@ import el2_pkg::*;
logic sb_cmd_pending, sb_abmem_cmd_pending;
logic sb_abmem_cmd_write;
logic [2:0] sb_abmem_cmd_size;
logic [ 2:0] sb_abmem_cmd_size;
logic [31:0] sb_abmem_cmd_addr;
logic [31:0] sb_abmem_cmd_wdata;
logic [2:0] sb_cmd_size;
logic [ 2:0] sb_cmd_size;
logic [31:0] sb_cmd_addr;
logic [63:0] sb_cmd_wdata;
@ -245,7 +274,7 @@ import el2_pkg::*;
logic sb_read_pend;
logic [31:0] sb_axi_addr;
logic [63:0] sb_axi_wrdata;
logic [2:0] sb_axi_size;
logic [ 2:0] sb_axi_size;
logic dbg_dm_rst_l;
logic rst_l_sync;
@ -264,8 +293,16 @@ import el2_pkg::*;
// used for the system bus
assign sb_free_clken = dmi_reg_en | execute_command | sb_state_en | (sb_state != SBIDLE) | clk_override;
rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);
rvoclkhdr dbg_free_cgc (
.en(dbg_free_clken),
.l1clk(dbg_free_clk),
.*
);
rvoclkhdr sb_free_cgc (
.en(sb_free_clken),
.l1clk(sb_free_clk),
.*
);
// end clocking section
@ -274,7 +311,12 @@ import el2_pkg::*;
assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;
// synchronize the rst
rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l));
rvsyncss #(1) rstl_syncff (
.din (rst_l),
.dout (rst_l_sync),
.clk (free_clk),
.rst_l(dbg_rst_l)
);
// system bus register
// sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal
@ -288,12 +330,41 @@ import el2_pkg::*;
(sbcs_reg[21] & dmi_reg_en & ((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c) | (dmi_reg_addr == 7'h3d)));
assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one
rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),
.dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(1) sbcs_sbbusyerror_reg (
.din(sbcs_sbbusyerror_din),
.dout(sbcs_reg[22]),
.en(sbcs_sbbusyerror_wren),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
rvdffs #(1) sbcs_sbbusy_reg (
.din(sbcs_sbbusy_din),
.dout(sbcs_reg[21]),
.en(sbcs_sbbusy_wren),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
rvdffs #(1) sbcs_sbreadonaddr_reg (
.din(dmi_reg_wdata[20]),
.dout(sbcs_reg[20]),
.en(sbcs_wren),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
rvdffs #(5) sbcs_misc_reg (
.din({dmi_reg_wdata[19], ~dmi_reg_wdata[18], dmi_reg_wdata[17:15]}),
.dout(sbcs_reg_int[19:15]),
.en(sbcs_wren),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
rvdffs #(3) sbcs_error_reg (
.din(sbcs_sberror_din[2:0]),
.dout(sbcs_reg[14:12]),
.en(sbcs_sberror_wren),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |
((sbcs_reg[19:17] == 3'b010) & (|sbaddress0_reg[1:0])) |
@ -320,15 +391,33 @@ import el2_pkg::*;
assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |
({32{sbdata1_reg_wren1}} & sb_bus_rdata[63:32]);
rvdffe #(32) dbg_sbdata0_reg (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(32) dbg_sbdata1_reg (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(32) dbg_sbdata0_reg (
.*,
.din(sbdata0_din[31:0]),
.dout(sbdata0_reg[31:0]),
.en(sbdata0_reg_wren),
.rst_l(dbg_dm_rst_l)
);
rvdffe #(32) dbg_sbdata1_reg (
.*,
.din(sbdata1_din[31:0]),
.dout(sbdata1_reg[31:0]),
.en(sbdata1_reg_wren),
.rst_l(dbg_dm_rst_l)
);
// sbaddress
assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);
assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;
assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |
({32{sbaddress0_reg_wren1}} & (sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]}));
rvdffe #(32) dbg_sbaddress0_reg (.*, .din(sbaddress0_reg_din[31:0]), .dout(sbaddress0_reg[31:0]), .en(sbaddress0_reg_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(32) dbg_sbaddress0_reg (
.*,
.din(sbaddress0_reg_din[31:0]),
.dout(sbaddress0_reg[31:0]),
.en(sbaddress0_reg_wren),
.rst_l(dbg_dm_rst_l)
);
assign sbreadonaddr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39) & sbcs_reg[20]; // if readonaddr is set the next command will start upon writing of addr0
assign sbreadondata_access = dmi_reg_en & ~dmi_reg_wr_en & (dmi_reg_addr == 7'h3c) & sbcs_reg[15]; // if readondata is set the next command will start upon reading of data0
@ -342,9 +431,26 @@ import el2_pkg::*;
assign dmcontrol_reg[29] = '0;
assign dmcontrol_reg[27:2] = '0;
assign resumereq = dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q;
rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk));
rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdffs #(4) dmcontrolff (
.din({dmi_reg_wdata[31:30], dmi_reg_wdata[28], dmi_reg_wdata[1]}),
.dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}),
.en(dmcontrol_wren),
.rst_l(dbg_dm_rst_l),
.clk(dbg_free_clk)
);
rvdffs #(1) dmcontrol_dmactive_ff (
.din(dmi_reg_wdata[0]),
.dout(dmcontrol_reg[0]),
.en(dmcontrol_wren),
.rst_l(dbg_rst_l),
.clk(dbg_free_clk)
);
rvdff #(1) dmcontrol_wrenff (
.din (dmcontrol_wren),
.dout (dmcontrol_wren_Q),
.rst_l(dbg_dm_rst_l),
.clk (dbg_free_clk)
);
// dmstatus register bits that are implemented
// [19:18]-havereset,[17:16]-resume ack, [9:8]-halted, [3:0]-version
@ -370,9 +476,26 @@ import el2_pkg::*;
assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync;
assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);
rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdff #(1) dmstatus_halted_reg (.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), .dout(dmstatus_halted), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdffs #(1) dmstatus_haveresetn_reg (.din(1'b1), .dout(dmstatus_haveresetn), .en(dmstatus_haveresetn_wren), .rst_l(rst_l), .clk(dbg_free_clk));
rvdffs #(1) dmstatus_resumeack_reg (
.din(dmstatus_resumeack_din),
.dout(dmstatus_resumeack),
.en(dmstatus_resumeack_wren),
.rst_l(dbg_dm_rst_l),
.clk(dbg_free_clk)
);
rvdff #(1) dmstatus_halted_reg (
.din (dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only),
.dout (dmstatus_halted),
.rst_l(dbg_dm_rst_l),
.clk (dbg_free_clk)
);
rvdffs #(1) dmstatus_haveresetn_reg (
.din(1'b1),
.dout(dmstatus_haveresetn),
.en(dmstatus_haveresetn_wren),
.rst_l(rst_l),
.clk(dbg_free_clk)
);
// haltsum0 register
assign haltsum0_reg[31:1] = '0;
@ -410,12 +533,30 @@ import el2_pkg::*;
abstractcs_error_sel6 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C
abstractcs_reg[10:8]; //hold
rvdffs #(1) dmabstractcs_busy_reg (.din(abstractcs_busy_din), .dout(abstractcs_reg[12]), .en(abstractcs_busy_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdff #(3) dmabstractcs_error_reg (.din(abstractcs_error_din[2:0]), .dout(abstractcs_reg[10:8]), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdffs #(1) dmabstractcs_busy_reg (
.din(abstractcs_busy_din),
.dout(abstractcs_reg[12]),
.en(abstractcs_busy_wren),
.rst_l(dbg_dm_rst_l),
.clk(dbg_free_clk)
);
rvdff #(3) dmabstractcs_error_reg (
.din (abstractcs_error_din[2:0]),
.dout (abstractcs_reg[10:8]),
.rst_l(dbg_dm_rst_l),
.clk (dbg_free_clk)
);
// abstract auto reg
assign abstractauto_reg_wren = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h18) & ~abstractcs_reg[12];
rvdffs #(2) dbg_abstractauto_reg (.*, .din(dmi_reg_wdata[1:0]), .dout(abstractauto_reg[1:0]), .en(abstractauto_reg_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
rvdffs #(2) dbg_abstractauto_reg (
.*,
.din(dmi_reg_wdata[1:0]),
.dout(abstractauto_reg[1:0]),
.en(abstractauto_reg_wren),
.rst_l(dbg_dm_rst_l),
.clk(dbg_free_clk)
);
// command register - implemented all the bits in this register
// command[16] = 1: write, 0: read
@ -425,11 +566,36 @@ import el2_pkg::*;
assign command_regno_wren = command_wren | ((command_reg[31:24] == 8'h0) & command_reg[19] & (dbg_state == CMD_DONE) & ~(|abstractcs_reg[10:8])); // aarpostincrement
assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];
assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];
assign command_din[31:16] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16]};
assign command_din[31:16] = {
dmi_reg_wdata[31:24],
1'b0,
dmi_reg_wdata[22:19],
command_postexec_din,
command_transfer_din,
dmi_reg_wdata[16]
};
assign command_din[15:0] = command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0];
rvdff #(1) execute_commandff (.*, .din(execute_command_ns), .dout(execute_command), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l));
rvdffe #(16) dmcommand_reg (.*, .din(command_din[31:16]), .dout(command_reg[31:16]), .en(command_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(16) dmcommand_regno_reg (.*, .din(command_din[15:0]), .dout(command_reg[15:0]), .en(command_regno_wren), .rst_l(dbg_dm_rst_l));
rvdff #(1) execute_commandff (
.*,
.din (execute_command_ns),
.dout (execute_command),
.clk (dbg_free_clk),
.rst_l(dbg_dm_rst_l)
);
rvdffe #(16) dmcommand_reg (
.*,
.din(command_din[31:16]),
.dout(command_reg[31:16]),
.en(command_wren),
.rst_l(dbg_dm_rst_l)
);
rvdffe #(16) dmcommand_regno_reg (
.*,
.din(command_din[15:0]),
.dout(command_reg[15:0]),
.en(command_regno_wren),
.rst_l(dbg_dm_rst_l)
);
// data0 reg
assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
@ -440,7 +606,13 @@ import el2_pkg::*;
({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) |
({32{data0_reg_wren2}} & sb_bus_rdata[31:0]);
rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(32) dbg_data0_reg (
.*,
.din(data0_din[31:0]),
.dout(data0_reg[31:0]),
.en(data0_reg_wren),
.rst_l(dbg_dm_rst_l)
);
// data 1
assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
@ -450,10 +622,30 @@ import el2_pkg::*;
assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]) |
({32{data1_reg_wren1}} & dbg_cmd_next_addr[31:0]);
rvdffe #(32) dbg_data1_reg (.*, .din(data1_din[31:0]), .dout(data1_reg[31:0]), .en(data1_reg_wren), .rst_l(dbg_dm_rst_l));
rvdffe #(32) dbg_data1_reg (
.*,
.din(data1_din[31:0]),
.dout(data1_reg[31:0]),
.en(data1_reg_wren),
.rst_l(dbg_dm_rst_l)
);
rvdffs #(1) sb_abmem_cmd_doneff (.din(sb_abmem_cmd_done_in), .dout(sb_abmem_cmd_done), .en(sb_abmem_cmd_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
rvdffs #(1) sb_abmem_data_doneff (.din(sb_abmem_data_done_in), .dout(sb_abmem_data_done), .en(sb_abmem_data_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
rvdffs #(1) sb_abmem_cmd_doneff (
.din(sb_abmem_cmd_done_in),
.dout(sb_abmem_cmd_done),
.en(sb_abmem_cmd_done_en),
.clk(dbg_free_clk),
.rst_l(dbg_dm_rst_l),
.*
);
rvdffs #(1) sb_abmem_data_doneff (
.din(sb_abmem_data_done_in),
.dout(sb_abmem_data_done),
.en(sb_abmem_data_done_en),
.clk(dbg_free_clk),
.rst_l(dbg_dm_rst_l),
.*
);
// FSM to control the debug mode entry, command send/recieve, and Resume flow.
always_comb begin
@ -476,7 +668,7 @@ import el2_pkg::*;
dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H
dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
end
HALTING : begin
HALTING: begin
dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK
dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only; // core indicates halted
end
@ -504,9 +696,9 @@ import el2_pkg::*;
end
SB_CMD_SEND: begin
sb_abmem_cmd_done_in = 1'b1;
sb_abmem_data_done_in= 1'b1;
sb_abmem_data_done_in = 1'b1;
sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en;
sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en;
sb_abmem_data_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en;
dbg_nxtstate = SB_CMD_RESP;
dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en;
end
@ -522,15 +714,15 @@ import el2_pkg::*;
abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
abstractcs_busy_din = 1'b0;
sb_abmem_cmd_done_in = 1'b0;
sb_abmem_data_done_in= 1'b0;
sb_abmem_data_done_in = 1'b0;
sb_abmem_cmd_done_en = 1'b1;
sb_abmem_data_done_en= 1'b1;
sb_abmem_data_done_en = 1'b1;
end
RESUMING : begin
RESUMING: begin
dbg_nxtstate = IDLE;
dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register
end
default : begin
default: begin
dbg_nxtstate = IDLE;
dbg_state_en = 1'b0;
abstractcs_busy_wren = 1'b0;
@ -561,8 +753,23 @@ import el2_pkg::*;
({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);
rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l & rst_l), .clk(dbg_free_clk));
rvdffe #(32) dmi_rddata_reg (.din(dmi_reg_rdata_din[31:0]), .dout(dmi_reg_rdata[31:0]), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(clk), .*);
rvdffs #($bits(
state_t
)) dbg_state_reg (
.din(dbg_nxtstate),
.dout({dbg_state}),
.en(dbg_state_en),
.rst_l(dbg_dm_rst_l & rst_l),
.clk(dbg_free_clk)
);
rvdffe #(32) dmi_rddata_reg (
.din(dmi_reg_rdata_din[31:0]),
.dout(dmi_reg_rdata[31:0]),
.en(dmi_reg_en),
.rst_l(dbg_dm_rst_l),
.clk(clk),
.*
);
assign abmem_addr[31:0] = data1_reg[31:0];
assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region);
@ -582,7 +789,7 @@ import el2_pkg::*;
assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h2) ? (4'h1 << sb_abmem_cmd_size[1:0]) : 4'h1;
assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {16'b0, command_reg[15:0]};
assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0,dbg_cmd_addr_incr[3:0]};
assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0, dbg_cmd_addr_incr[3:0]};
// Ask DMA to stop taking bus trxns since debug request is done
assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT);
@ -621,19 +828,19 @@ import el2_pkg::*;
sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
end
CMD_RD : begin
CMD_RD: begin
sb_nxtstate = RSP_RD;
sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en;
end
CMD_WR : begin
CMD_WR: begin
sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA);
sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en;
end
CMD_WR_ADDR : begin
CMD_WR_ADDR: begin
sb_nxtstate = RSP_WR;
sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en;
end
CMD_WR_DATA : begin
CMD_WR_DATA: begin
sb_nxtstate = RSP_WR;
sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en;
end
@ -656,7 +863,7 @@ import el2_pkg::*;
sbcs_sbbusy_din = 1'b0;
sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command
end
default : begin
default: begin
sb_nxtstate = SBIDLE;
sb_state_en = 1'b0;
sbcs_sbbusy_wren = 1'b0;
@ -668,7 +875,15 @@ import el2_pkg::*;
endcase
end // always_comb begin
rvdffs #($bits(sb_state_t)) sb_state_reg (.din(sb_nxtstate), .dout({sb_state}), .en(sb_state_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #($bits(
sb_state_t
)) sb_state_reg (
.din(sb_nxtstate),
.dout({sb_state}),
.en(sb_state_en),
.rst_l(dbg_dm_rst_l),
.clk(sb_free_clk)
);
assign sb_abmem_cmd_write = command_reg[16];
assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]};

67
Flow/design/dec/el2_dec.sv
View File

@ -28,11 +28,10 @@
//********************************************************************************
module el2_dec
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in.
@ -98,7 +97,7 @@ import el2_pkg::*;
input logic dma_pmu_any_write, // DMA write
input logic [31:1] lsu_fir_addr, // Fast int address
input logic [1:0] lsu_fir_error, // Fast int lookup error
input logic [ 1:0] lsu_fir_error, // Fast int lookup error
input logic ifu_pmu_instr_aligned, // aligned instructions
input logic ifu_pmu_fetch_stall, // fetch unit stalled
@ -111,12 +110,12 @@ import el2_pkg::*;
input logic ifu_ic_error_start, // IC single bit error
input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
input logic [3:0] lsu_trigger_match_m,
input logic [ 3:0] lsu_trigger_match_m,
input logic dbg_cmd_valid, // debugger abstract command valid
input logic dbg_cmd_write, // command is a write
input logic [1:0] dbg_cmd_type, // command type
input logic [ 1:0] dbg_cmd_type, // command type
input logic [31:0] dbg_cmd_addr, // command address
input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i
input logic [ 1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i
input logic ifu_i0_icaf, // icache access fault
@ -129,9 +128,9 @@ import el2_pkg::*;
input el2_br_pkt_t i0_brp, // branch packet
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet
input logic lsu_single_ecc_error_incr, // LSU inc SB error counter
@ -184,7 +183,7 @@ import el2_pkg::*;
output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
// Debug start
// Debug start
input logic dbg_halt_req, // DM requests a halt
input logic dbg_resume_req, // DM requests a resume
input logic ifu_miss_state_idle, // I-side miss buffer empty
@ -208,7 +207,7 @@ import el2_pkg::*;
output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks
output logic dec_tlu_force_halt, // halt has been forced
// Debug end
// Debug end
// branch info from pipe0 for errors or counter updates
input logic [1:0] exu_i0_br_hist_r, // history
input logic exu_i0_br_error_r, // error
@ -237,8 +236,8 @@ import el2_pkg::*;
output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's
output logic [31:1] dec_i0_pc_d, // pc's at decode
output logic [3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable
output logic [3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable
output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable
output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable
output logic [31:0] dec_i0_result_r, // Result R-stage
@ -273,7 +272,9 @@ import el2_pkg::*;
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index
output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag
output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
output logic [$clog2(
pt.BTB_SIZE
)-1:0] dec_fa_error_index, // Fully associt btb error index
output logic dec_lsu_valid_raw_d,
@ -307,7 +308,7 @@ import el2_pkg::*;
output logic dec_tlu_i0_commit_cmt, // committed i0 instruction
input logic scan_mode // Flop scan mode control
);
);
logic dec_tlu_dec_clk_override; // to and from dec blocks
@ -382,11 +383,11 @@ import el2_pkg::*;
logic [31:0] dec_i0_inst_wb;
logic [31:1] dec_i0_pc_wb;
logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
logic [4:0] dec_tlu_exc_cause_wb1;
logic [ 4:0] dec_tlu_exc_cause_wb1;
logic [31:0] dec_tlu_mtval_wb1;
logic dec_tlu_i0_exc_valid_wb1;
logic [4:0] div_waddr_wb;
logic [ 4:0] div_waddr_wb;
logic dec_div_active;
logic dec_debug_valid_d;
@ -406,30 +407,40 @@ import el2_pkg::*;
el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
el2_dec_gpr_ctl #(.pt(pt)) arf (.*,
el2_dec_gpr_ctl #(
.pt(pt)
) arf (
.*,
// inputs
.raddr0(dec_i0_rs1_d[4:0]),
.raddr1(dec_i0_rs2_d[4:0]),
.wen0(dec_i0_wen_r), .waddr0(dec_i0_waddr_r[4:0]), .wd0(dec_i0_wdata_r[31:0]),
.wen1(dec_nonblock_load_wen), .waddr1(dec_nonblock_load_waddr[4:0]), .wd1(lsu_nonblock_load_data[31:0]),
.wen2(exu_div_wren), .waddr2(div_waddr_wb), .wd2(exu_div_result[31:0]),
.wen0(dec_i0_wen_r),
.waddr0(dec_i0_waddr_r[4:0]),
.wd0(dec_i0_wdata_r[31:0]),
.wen1(dec_nonblock_load_wen),
.waddr1(dec_nonblock_load_waddr[4:0]),
.wd1(lsu_nonblock_load_data[31:0]),
.wen2(exu_div_wren),
.waddr2(div_waddr_wb),
.wd2(exu_div_result[31:0]),
// outputs
.rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0])
.rd0(gpr_i0_rs1_d[31:0]),
.rd1(gpr_i0_rs2_d[31:0])
);
// Trigger
// Trigger
el2_dec_trigger #(.pt(pt)) dec_trigger (.*);
// trace
// trace
assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0];
assign trace_rv_trace_pkt.trace_rv_i_address_ip = { dec_i0_pc_wb[31:1], 1'b0};
assign trace_rv_trace_pkt.trace_rv_i_address_ip = {dec_i0_pc_wb[31:1], 1'b0};
assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
@ -439,7 +450,7 @@ import el2_pkg::*;
// end trace
// end trace
endmodule // el2_dec

649
Flow/design/dec/el2_dec_decode_ctl.sv
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File diff suppressed because it is too large Load Diff

39
Flow/design/dec/el2_dec_gpr_ctl.sv
View File

@ -14,23 +14,23 @@
// limitations under the License.
module el2_dec_gpr_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
) (
) (
input logic [4:0] raddr0, // logical read addresses
input logic [4:0] raddr1,
input logic wen0, // write enable
input logic [4:0] waddr0, // write address
input logic [ 4:0] waddr0, // write address
input logic [31:0] wd0, // write data
input logic wen1, // write enable
input logic [4:0] waddr1, // write address
input logic [ 4:0] waddr1, // write address
input logic [31:0] wd1, // write data
input logic wen2, // write enable
input logic [4:0] waddr2, // write address
input logic [ 4:0] waddr2, // write address
input logic [31:0] wd2, // write data
input logic clk,
@ -42,15 +42,20 @@ import el2_pkg::*;
input logic scan_mode
);
logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs
logic [31:1] [31:0] gpr_in;
logic [31:1] w0v,w1v,w2v;
logic [31:1][31:0] gpr_out; // 31 x 32 bit GPRs
logic [31:1][31:0] gpr_in;
logic [31:1] w0v, w1v, w2v;
logic [31:1] gpr_wr_en;
// GPR Write Enables
assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
for ( genvar j=1; j<32; j++ ) begin : gpr
rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0]));
for (genvar j = 1; j < 32; j++) begin : gpr
rvdffe #(32) gprff (
.*,
.en (gpr_wr_en[j]),
.din (gpr_in[j][31:0]),
.dout(gpr_out[j][31:0])
);
end : gpr
// the read out
@ -63,16 +68,16 @@ import el2_pkg::*;
gpr_in[31:1] = '0;
// GPR Read logic
for (int j=1; j<32; j++ ) begin
rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]);
rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]);
for (int j = 1; j < 32; j++) begin
rd0[31:0] |= ({32{(raddr0[4:0] == 5'(j))}} & gpr_out[j][31:0]);
rd1[31:0] |= ({32{(raddr1[4:0] == 5'(j))}} & gpr_out[j][31:0]);
end
// GPR Write logic
for (int j=1; j<32; j++ ) begin
w0v[j] = wen0 & (waddr0[4:0]== 5'(j) );
w1v[j] = wen1 & (waddr1[4:0]== 5'(j) );
w2v[j] = wen2 & (waddr2[4:0]== 5'(j) );
for (int j = 1; j < 32; j++) begin
w0v[j] = wen0 & (waddr0[4:0] == 5'(j));
w1v[j] = wen1 & (waddr1[4:0] == 5'(j));
w2v[j] = wen2 & (waddr2[4:0] == 5'(j));
gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |
({32{w1v[j]}} & wd1[31:0]) |
({32{w2v[j]}} & wd2[31:0]);

48
Flow/design/dec/el2_dec_ib_ctl.sv
View File

@ -14,15 +14,14 @@
// limitations under the License.
module el2_dec_ib_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic dbg_cmd_valid, // valid dbg cmd
input logic dbg_cmd_write, // dbg cmd is write
input logic [1:0] dbg_cmd_type, // dbg type
input logic [ 1:0] dbg_cmd_type, // dbg type
input logic [31:0] dbg_cmd_addr, // expand to 31:0
input el2_br_pkt_t i0_brp, // i0 branch packet from aligner
@ -66,11 +65,11 @@ import el2_pkg::*;
output logic dec_debug_fence_d // debug fence inst
);
);
logic debug_valid;
logic [4:0] dreg;
logic [ 4:0] dreg;
logic [11:0] dcsr;
logic [31:0] ib0, ib0_debug_in;
@ -83,8 +82,9 @@ import el2_pkg::*;
logic [34:0] ifu_i0_pcdata, pc0;
assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
ifu_i0_pc[31:1], ifu_i0_pc4 };
assign ifu_i0_pcdata[34:0] = {
ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf, ifu_i0_pc[31:1], ifu_i0_pc4
};
assign pc0[34:0] = ifu_i0_pcdata[34:0];
@ -98,34 +98,34 @@ import el2_pkg::*;
assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0];
// GPR accesses
// GPR accesses
// put reg to read on rs1
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
// put reg to read on rs1
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
// put write date on rs1
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
// put write date on rs1
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
// CSR accesses
// csr is of form rd, csr, rs1
// CSR accesses
// csr is of form rd, csr, rs1
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
// put write data on rs1
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
// put write data on rs1
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
// abstract memory command not done here
// abstract memory command not done here
assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2);
assign debug_read = debug_valid & ~dbg_cmd_write;
assign debug_write = debug_valid & dbg_cmd_write;
assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0]==2'h0);
assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0]==2'h0);
assign debug_read_csr = debug_read & (dbg_cmd_type[1:0]==2'h1);
assign debug_write_csr = debug_write & (dbg_cmd_type[1:0]==2'h1);
assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0] == 2'h0);
assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0] == 2'h0);
assign debug_read_csr = debug_read & (dbg_cmd_type[1:0] == 2'h1);
assign debug_write_csr = debug_write & (dbg_cmd_type[1:0] == 2'h1);
assign dreg[4:0] = dbg_cmd_addr[4:0];
assign dcsr[11:0] = dbg_cmd_addr[11:0];

1615
Flow/design/dec/el2_dec_tlu_ctl.sv
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File diff suppressed because it is too large Load Diff

15
Flow/design/dec/el2_dec_trigger.sv
View File

@ -23,10 +23,10 @@
//
//********************************************************************************
module el2_dec_trigger
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input el2_trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match
input logic [31:1] dec_i0_pc_d, // i0 pc
@ -37,10 +37,15 @@ import el2_pkg::*;
logic [3:0][31:0] dec_i0_match_data;
logic [3:0] dec_i0_trigger_data_match;
for (genvar i=0; i<4; i++) begin
for (genvar i = 0; i < 4; i++) begin
assign dec_i0_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select & trigger_pkt_any[i].execute}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i].tdata2[0]}); // select=0; do a PC match
rvmaskandmatch trigger_i0_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(dec_i0_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(dec_i0_trigger_data_match[i]));
rvmaskandmatch trigger_i0_match (
.mask (trigger_pkt_any[i].tdata2[31:0]),
.data (dec_i0_match_data[i][31:0]),
.masken(trigger_pkt_any[i].match),
.match (dec_i0_trigger_data_match[i])
);
assign dec_i0_trigger_match_d[i] = trigger_pkt_any[i].execute & trigger_pkt_any[i].m & dec_i0_trigger_data_match[i];
end

43
Flow/design/dmi/dmi_jtag_to_core_sync.v
View File

@ -23,42 +23,41 @@
//-------------------------------------------------------------------------------------
module dmi_jtag_to_core_sync (
// JTAG signals
input rd_en, // 1 bit Read Enable from JTAG
input wr_en, // 1 bit Write enable from JTAG
// JTAG signals
input rd_en, // 1 bit Read Enable from JTAG
input wr_en, // 1 bit Write enable from JTAG
// Processor Signals
input rst_n, // Core reset
input clk, // Core clock
// Processor Signals
input rst_n, // Core reset
input clk, // Core clock
output reg_en, // 1 bit Write interface bit to Processor
output reg_wr_en // 1 bit Write enable to Processor
output reg_en, // 1 bit Write interface bit to Processor
output reg_wr_en // 1 bit Write enable to Processor
);
wire c_rd_en;
wire c_wr_en;
reg [2:0] rden, wren;
wire c_rd_en;
wire c_wr_en;
reg [2:0] rden, wren;
// Outputs
assign reg_en = c_wr_en | c_rd_en;
assign reg_wr_en = c_wr_en;
// Outputs
assign reg_en = c_wr_en | c_rd_en;
assign reg_wr_en = c_wr_en;
// synchronizers
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
// synchronizers
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rden <= '0;
wren <= '0;
end
else begin
end else begin
rden <= {rden[1:0], rd_en};
wren <= {wren[1:0], wr_en};
end
end
end
assign c_rd_en = rden[1] & ~rden[2];
assign c_wr_en = wren[1] & ~wren[2];
assign c_rd_en = rden[1] & ~rden[2];
assign c_wr_en = wren[1] & ~wren[2];
endmodule

14
Flow/design/dmi/dmi_wrapper.v
View File

@ -21,7 +21,7 @@
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
module dmi_wrapper (
// JTAG signals
input trst_n, // JTAG reset
@ -54,7 +54,7 @@ module dmi_wrapper(
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
rvjtag_tap i_jtag_tap (
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
@ -73,17 +73,17 @@ module dmi_wrapper(
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync (
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.rst_n (core_rst_n),
.clk (core_clk),
.reg_en (reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);

239
Flow/design/dmi/rvjtag_tap.v
View File

@ -14,85 +14,84 @@
// limitations under the License
module rvjtag_tap #(
parameter AWIDTH = 7
)
(
input trst,
input tck,
input tms,
input tdi,
output reg tdo,
output tdoEnable,
parameter AWIDTH = 7
) (
input trst,
input tck,
input tms,
input tdi,
output reg tdo,
output tdoEnable,
output [31:0] wr_data,
output [AWIDTH-1:0] wr_addr,
output wr_en,
output rd_en,
output [ 31:0] wr_data,
output [AWIDTH-1:0] wr_addr,
output wr_en,
output rd_en,
input [31:0] rd_data,
input [1:0] rd_status,
input [31:0] rd_data,
input [ 1:0] rd_status,
output reg dmi_reset,
output reg dmi_hard_reset,
output reg dmi_reset,
output reg dmi_hard_reset,
input [2:0] idle,
input [1:0] dmi_stat,
/*
input [ 2:0] idle,
input [ 1:0] dmi_stat,
/*
-- revisionCode : 4'h0;
-- manufacturersIdCode : 11'h45;
-- deviceIdCode : 16'h0001;
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
*/
input [31:1] jtag_id,
input [3:0] version
input [31:1] jtag_id,
input [ 3:0] version
);
localparam USER_DR_LENGTH = AWIDTH + 34;
localparam USER_DR_LENGTH = AWIDTH + 34;
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
logic[3:0] state, nstate;
logic [4:0] ir;
wire jtag_reset;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire shift_ir;
wire pause_ir ;
wire update_ir ;
wire capture_ir;
wire[1:0] dr_en;
wire devid_sel;
wire [5:0] abits;
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
logic [3:0] state, nstate;
logic [4:0] ir;
wire jtag_reset;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire shift_ir;
wire pause_ir;
wire update_ir;
wire capture_ir;
wire [1:0] dr_en;
wire devid_sel;
wire [5:0] abits;
assign abits = AWIDTH[5:0];
assign abits = AWIDTH[5:0];
localparam TEST_LOGIC_RESET_STATE = 0;
localparam RUN_TEST_IDLE_STATE = 1;
localparam SELECT_DR_SCAN_STATE = 2;
localparam CAPTURE_DR_STATE = 3;
localparam SHIFT_DR_STATE = 4;
localparam EXIT1_DR_STATE = 5;
localparam PAUSE_DR_STATE = 6;
localparam EXIT2_DR_STATE = 7;
localparam UPDATE_DR_STATE = 8;
localparam SELECT_IR_SCAN_STATE = 9;
localparam CAPTURE_IR_STATE = 10;
localparam SHIFT_IR_STATE = 11;
localparam EXIT1_IR_STATE = 12;
localparam PAUSE_IR_STATE = 13;
localparam EXIT2_IR_STATE = 14;
localparam UPDATE_IR_STATE = 15;
localparam TEST_LOGIC_RESET_STATE = 0;
localparam RUN_TEST_IDLE_STATE = 1;
localparam SELECT_DR_SCAN_STATE = 2;
localparam CAPTURE_DR_STATE = 3;
localparam SHIFT_DR_STATE = 4;
localparam EXIT1_DR_STATE = 5;
localparam PAUSE_DR_STATE = 6;
localparam EXIT2_DR_STATE = 7;
localparam UPDATE_DR_STATE = 8;
localparam SELECT_IR_SCAN_STATE = 9;
localparam CAPTURE_IR_STATE = 10;
localparam SHIFT_IR_STATE = 11;
localparam EXIT1_IR_STATE = 12;
localparam PAUSE_IR_STATE = 13;
localparam EXIT2_IR_STATE = 14;
localparam UPDATE_IR_STATE = 15;
always_comb begin
always_comb begin
nstate = state;
case(state)
case (state)
TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
@ -111,60 +110,59 @@ always_comb begin
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
default: nstate = TEST_LOGIC_RESET_STATE;
endcase
end
end
always @ (posedge tck or negedge trst) begin
if(!trst) state <= TEST_LOGIC_RESET_STATE;
always @(posedge tck or negedge trst) begin
if (!trst) state <= TEST_LOGIC_RESET_STATE;
else state <= nstate;
end
end
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
assign shift_dr = state == SHIFT_DR_STATE;
assign pause_dr = state == PAUSE_DR_STATE;
assign update_dr = state == UPDATE_DR_STATE;
assign capture_dr = state == CAPTURE_DR_STATE;
assign shift_ir = state == SHIFT_IR_STATE;
assign pause_ir = state == PAUSE_IR_STATE;
assign update_ir = state == UPDATE_IR_STATE;
assign capture_ir = state == CAPTURE_IR_STATE;
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
assign shift_dr = state == SHIFT_DR_STATE;
assign pause_dr = state == PAUSE_DR_STATE;
assign update_dr = state == UPDATE_DR_STATE;
assign capture_dr = state == CAPTURE_DR_STATE;
assign shift_ir = state == SHIFT_IR_STATE;
assign pause_ir = state == PAUSE_IR_STATE;
assign update_ir = state == UPDATE_IR_STATE;
assign capture_ir = state == CAPTURE_IR_STATE;
assign tdoEnable = shift_dr | shift_ir;
assign tdoEnable = shift_dr | shift_ir;
///////////////////////////////////////////////////////
// IR register
///////////////////////////////////////////////////////
///////////////////////////////////////////////////////
// IR register
///////////////////////////////////////////////////////
always @ (negedge tck or negedge trst) begin
always @(negedge tck or negedge trst) begin
if (!trst) ir <= 5'b1;
else begin
if (jtag_reset) ir <= 5'b1;
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f : sr[4:0];
end
end
end
assign devid_sel = ir == 5'b00001;
assign dr_en[0] = ir == 5'b10000;
assign dr_en[1] = ir == 5'b10001;
assign devid_sel = ir == 5'b00001;
assign dr_en[0] = ir == 5'b10000;
assign dr_en[1] = ir == 5'b10001;
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
always @ (posedge tck or negedge trst) begin
if(!trst)begin
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
always @(posedge tck or negedge trst) begin
if (!trst) begin
sr <= '0;
end
else begin
end else begin
sr <= nsr;
end
end
end
// SR next value
always_comb begin
// SR next value
always_comb begin
nsr = sr;
case(1)
case (1)
shift_dr: begin
case(1)
case (1)
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
dr_en[0],
@ -174,49 +172,44 @@ always_comb begin
end
capture_dr: begin
nsr[0] = 1'b0;
case(1)
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
case (1)
dr_en[0]: nsr = {{USER_DR_LENGTH - 15{1'b0}}, idle, dmi_stat, abits, version};
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
devid_sel: nsr = {{USER_DR_LENGTH - 32{1'b0}}, jtag_id, 1'b1};
endcase
end
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
shift_ir: nsr = {{USER_DR_LENGTH - 5{1'b0}}, tdi, sr[4:1]};
capture_ir: nsr = {{USER_DR_LENGTH - 1{1'b0}}, 1'b1};
endcase
end
end
// TDO retiming
always @ (negedge tck ) tdo <= sr[0];
// TDO retiming
always @(negedge tck) tdo <= sr[0];
// DMI CS register
always @ (posedge tck or negedge trst) begin
if(!trst) begin
// DMI CS register
always @(posedge tck or negedge trst) begin
if (!trst) begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
else if (update_dr & dr_en[0]) begin
end else if (update_dr & dr_en[0]) begin
dmi_hard_reset <= sr[17];
dmi_reset <= sr[16];
end
else begin
end else begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
end
// DR register
always @ (posedge tck or negedge trst) begin
if(!trst)
dr <= '0;
else begin
if (update_dr & dr_en[1])
dr <= sr;
else
dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
end
end
assign {wr_addr, wr_data, wr_en, rd_en} = dr;
// DR register
always @(posedge tck or negedge trst) begin
if (!trst) dr <= '0;
else begin
if (update_dr & dr_en[1]) dr <= sr;
else dr <= {dr[USER_DR_LENGTH-1:2], 2'b0};
end
end
assign {wr_addr, wr_data, wr_en, rd_en} = dr;

453
Flow/design/el2_dma_ctrl.sv
View File

@ -22,8 +22,8 @@
//********************************************************************************
module el2_dma_ctrl #(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic clk,
input logic free_clk,
input logic rst_l,
@ -36,8 +36,8 @@ module el2_dma_ctrl #(
input logic [31:0] dbg_cmd_wrdata,
input logic dbg_cmd_valid,
input logic dbg_cmd_write, // 1: write command, 0: read_command
input logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory
input logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command
input logic [ 1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory
input logic [ 1:0] dbg_cmd_size, // size of the abstract mem access debug command
input logic dbg_dma_bubble, // Debug needs a bubble to send a valid
output logic dma_dbg_ready, // DMA is ready to accept debug request
@ -49,19 +49,19 @@ module el2_dma_ctrl #(
// Core side signals
output logic dma_dccm_req, // DMA dccm request (only one of dccm/iccm will be set)
output logic dma_iccm_req, // DMA iccm request
output logic [2:0] dma_mem_tag, // DMA Buffer entry number
output logic [ 2:0] dma_mem_tag, // DMA Buffer entry number
output logic [31:0] dma_mem_addr, // DMA request address
output logic [2:0] dma_mem_sz, // DMA request size
output logic [ 2:0] dma_mem_sz, // DMA request size
output logic dma_mem_write, // DMA write to dccm/iccm
output logic [63:0] dma_mem_wdata, // DMA write data
input logic dccm_dma_rvalid, // dccm data valid for DMA read
input logic dccm_dma_ecc_error, // ECC error on DMA read
input logic [2:0] dccm_dma_rtag, // Tag of the DMA req
input logic [ 2:0] dccm_dma_rtag, // Tag of the DMA req
input logic [63:0] dccm_dma_rdata, // dccm data for DMA read
input logic iccm_dma_rvalid, // iccm data valid for DMA read
input logic iccm_dma_ecc_error, // ECC error on DMA read
input logic [2:0] iccm_dma_rtag, // Tag of the DMA req
input logic [ 2:0] iccm_dma_rtag, // Tag of the DMA req
input logic [63:0] iccm_dma_rdata, // iccm data for DMA read
output logic dma_active, // DMA is busy
@ -81,32 +81,32 @@ module el2_dma_ctrl #(
input logic dma_axi_awvalid,
output logic dma_axi_awready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
input logic [31:0] dma_axi_awaddr,
input logic [2:0] dma_axi_awsize,
input logic [ 31:0] dma_axi_awaddr,
input logic [ 2:0] dma_axi_awsize,
input logic dma_axi_wvalid,
output logic dma_axi_wready,
input logic [63:0] dma_axi_wdata,
input logic [7:0] dma_axi_wstrb,
input logic [ 7:0] dma_axi_wstrb,
output logic dma_axi_bvalid,
input logic dma_axi_bready,
output logic [1:0] dma_axi_bresp,
output logic [ 1:0] dma_axi_bresp,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
// AXI Read Channels
input logic dma_axi_arvalid,
output logic dma_axi_arready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
input logic [31:0] dma_axi_araddr,
input logic [2:0] dma_axi_arsize,
input logic [ 31:0] dma_axi_araddr,
input logic [ 2:0] dma_axi_arsize,
output logic dma_axi_rvalid,
input logic dma_axi_rready,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
output logic [63:0] dma_axi_rdata,
output logic [1:0] dma_axi_rresp,
output logic [ 63:0] dma_axi_rdata,
output logic [ 1:0] dma_axi_rresp,
output logic dma_axi_rlast
);
@ -155,8 +155,8 @@ module el2_dma_ctrl #(
logic [DEPTH_PTR-1:0] RdPtr, NxtRdPtr;
logic WrPtrEn, RdPtrEn, RspPtrEn;
logic [1:0] dma_dbg_sz;
logic [1:0] dma_dbg_addr;
logic [ 1:0] dma_dbg_sz;
logic [ 1:0] dma_dbg_addr;
logic [31:0] dma_dbg_mem_rddata;
logic [31:0] dma_dbg_mem_wrdata;
logic dma_dbg_cmd_error;
@ -164,11 +164,11 @@ module el2_dma_ctrl #(
logic fifo_full, fifo_full_spec, fifo_empty;
logic dma_address_error, dma_alignment_error;
logic [3:0] num_fifo_vld;
logic [ 3:0] num_fifo_vld;
logic dma_mem_req;
logic [31:0] dma_mem_addr_int;
logic [2:0] dma_mem_sz_int;
logic [7:0] dma_mem_byteen;
logic [ 2:0] dma_mem_sz_int;
logic [ 7:0] dma_mem_byteen;
logic dma_mem_addr_in_dccm;
logic dma_mem_addr_in_iccm;
logic dma_mem_addr_in_pic;
@ -187,12 +187,12 @@ module el2_dma_ctrl #(
logic bus_rsp_valid, bus_rsp_sent;
logic bus_cmd_valid, bus_cmd_sent;
logic bus_cmd_write, bus_cmd_posted_write;
logic [7:0] bus_cmd_byteen;
logic [2:0] bus_cmd_sz;
logic [31:0] bus_cmd_addr;
logic [63:0] bus_cmd_wdata;
logic [pt.DMA_BUS_TAG-1:0] bus_cmd_tag;
logic [pt.DMA_BUS_ID-1:0] bus_cmd_mid;
logic [ 7:0] bus_cmd_byteen;
logic [ 2:0] bus_cmd_sz;
logic [ 31:0] bus_cmd_addr;
logic [ 63:0] bus_cmd_wdata;
logic [ pt.DMA_BUS_TAG-1:0] bus_cmd_tag;
logic [ pt.DMA_BUS_ID-1:0] bus_cmd_mid;
logic [pt.DMA_BUS_PRTY-1:0] bus_cmd_prty;
logic bus_posted_write_done;
@ -205,17 +205,17 @@ module el2_dma_ctrl #(
logic wrbuf_cmd_sent, wrbuf_rst, wrbuf_data_rst;
logic wrbuf_vld, wrbuf_data_vld;
logic [pt.DMA_BUS_TAG-1:0] wrbuf_tag;
logic [2:0] wrbuf_sz;
logic [31:0] wrbuf_addr;
logic [63:0] wrbuf_data;
logic [7:0] wrbuf_byteen;
logic [ 2:0] wrbuf_sz;
logic [ 31:0] wrbuf_addr;
logic [ 63:0] wrbuf_data;
logic [ 7:0] wrbuf_byteen;
logic rdbuf_en;
logic rdbuf_cmd_sent, rdbuf_rst;
logic rdbuf_vld;
logic [pt.DMA_BUS_TAG-1:0] rdbuf_tag;
logic [2:0] rdbuf_sz;
logic [31:0] rdbuf_addr;
logic [ 2:0] rdbuf_sz;
logic [ 31:0] rdbuf_addr;
logic axi_mstr_prty_in, axi_mstr_prty_en;
logic axi_mstr_priority;
@ -224,20 +224,20 @@ module el2_dma_ctrl #(
logic axi_rsp_valid, axi_rsp_sent;
logic axi_rsp_write;
logic [pt.DMA_BUS_TAG-1:0] axi_rsp_tag;
logic [1:0] axi_rsp_error;
logic [63:0] axi_rsp_rdata;
logic [ 1:0] axi_rsp_error;
logic [ 63:0] axi_rsp_rdata;
//------------------------LOGIC STARTS HERE---------------------------------
// FIFO inputs
assign fifo_addr_in[31:0] = dbg_cmd_valid ? dbg_cmd_addr[31:0] : bus_cmd_addr[31:0];
assign fifo_byteen_in[7:0] = {8{~dbg_cmd_valid}} & bus_cmd_byteen[7:0]; // Byte enable is used only for bus requests
assign fifo_sz_in[2:0] = dbg_cmd_valid ? {1'b0,dbg_cmd_size[1:0]} : bus_cmd_sz[2:0];
assign fifo_sz_in[2:0] = dbg_cmd_valid ? {1'b0, dbg_cmd_size[1:0]} : bus_cmd_sz[2:0];
assign fifo_write_in = dbg_cmd_valid ? dbg_cmd_write : bus_cmd_write;
assign fifo_posted_write_in = ~dbg_cmd_valid & bus_cmd_posted_write;
assign fifo_dbg_in = dbg_cmd_valid;
for (genvar i=0 ;i<DEPTH; i++) begin: GenFifo
for (genvar i = 0; i < DEPTH; i++) begin : GenFifo
assign fifo_cmd_en[i] = ((bus_cmd_sent & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1])) & (i == WrPtr[DEPTH_PTR-1:0]);
assign fifo_data_en[i] = (((bus_cmd_sent & fifo_write_in & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1] & dbg_cmd_write)) & (i == WrPtr[DEPTH_PTR-1:0])) |
((dma_address_error | dma_alignment_error) & (i == RdPtr[DEPTH_PTR-1:0])) |
@ -259,22 +259,122 @@ module el2_dma_ctrl #(
((dccm_dma_rvalid & (i == DEPTH_PTR'(dccm_dma_rtag[2:0]))) ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid & (i == DEPTH_PTR'(iccm_dma_rtag[2:0]))) ? iccm_dma_rdata[63:0] :
(dbg_cmd_valid ? {2{dma_dbg_mem_wrdata[31:0]}} : bus_cmd_wdata[63:0]));
rvdffsc #(1) fifo_valid_dff (.din(1'b1), .dout(fifo_valid[i]), .en(fifo_cmd_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffsc #(2) fifo_error_dff (.din(fifo_error_in[i]), .dout(fifo_error[i]), .en(fifo_error_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffsc #(1) fifo_error_bus_dff (.din(1'b1), .dout(fifo_error_bus[i]), .en(fifo_error_bus_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffsc #(1) fifo_rpend_dff (.din(1'b1), .dout(fifo_rpend[i]), .en(fifo_pend_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffsc #(1) fifo_done_dff (.din(1'b1), .dout(fifo_done[i]), .en(fifo_done_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffsc #(1) fifo_done_bus_dff (.din(1'b1), .dout(fifo_done_bus[i]), .en(fifo_done_bus_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
rvdffe #(32) fifo_addr_dff (.din(fifo_addr_in[31:0]), .dout(fifo_addr[i]), .en(fifo_cmd_en[i]), .*);
rvdffs #(3) fifo_sz_dff (.din(fifo_sz_in[2:0]), .dout(fifo_sz[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(8) fifo_byteen_dff (.din(fifo_byteen_in[7:0]), .dout(fifo_byteen[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(1) fifo_write_dff (.din(fifo_write_in), .dout(fifo_write[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(1) fifo_posted_write_dff (.din(fifo_posted_write_in), .dout(fifo_posted_write[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(1) fifo_dbg_dff (.din(fifo_dbg_in), .dout(fifo_dbg[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffe #(64) fifo_data_dff (.din(fifo_data_in[i]), .dout(fifo_data[i]), .en(fifo_data_en[i]), .*);
rvdffs #(pt.DMA_BUS_TAG) fifo_tag_dff(.din(bus_cmd_tag[pt.DMA_BUS_TAG-1:0]), .dout(fifo_tag[i][pt.DMA_BUS_TAG-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(pt.DMA_BUS_ID) fifo_mid_dff(.din(bus_cmd_mid[pt.DMA_BUS_ID-1:0]), .dout(fifo_mid[i][pt.DMA_BUS_ID-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffs #(pt.DMA_BUS_PRTY) fifo_prty_dff(.din(bus_cmd_prty[pt.DMA_BUS_PRTY-1:0]), .dout(fifo_prty[i][pt.DMA_BUS_PRTY-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
rvdffsc #(1) fifo_valid_dff (
.din(1'b1),
.dout(fifo_valid[i]),
.en(fifo_cmd_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffsc #(2) fifo_error_dff (
.din(fifo_error_in[i]),
.dout(fifo_error[i]),
.en(fifo_error_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffsc #(1) fifo_error_bus_dff (
.din(1'b1),
.dout(fifo_error_bus[i]),
.en(fifo_error_bus_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffsc #(1) fifo_rpend_dff (
.din(1'b1),
.dout(fifo_rpend[i]),
.en(fifo_pend_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffsc #(1) fifo_done_dff (
.din(1'b1),
.dout(fifo_done[i]),
.en(fifo_done_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffsc #(1) fifo_done_bus_dff (
.din(1'b1),
.dout(fifo_done_bus[i]),
.en(fifo_done_bus_en[i]),
.clear(fifo_reset[i]),
.clk(dma_free_clk),
.*
);
rvdffe #(32) fifo_addr_dff (
.din (fifo_addr_in[31:0]),
.dout(fifo_addr[i]),
.en (fifo_cmd_en[i]),
.*
);
rvdffs #(3) fifo_sz_dff (
.din (fifo_sz_in[2:0]),
.dout(fifo_sz[i]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(8) fifo_byteen_dff (
.din (fifo_byteen_in[7:0]),
.dout(fifo_byteen[i]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(1) fifo_write_dff (
.din (fifo_write_in),
.dout(fifo_write[i]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(1) fifo_posted_write_dff (
.din (fifo_posted_write_in),
.dout(fifo_posted_write[i]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(1) fifo_dbg_dff (
.din (fifo_dbg_in),
.dout(fifo_dbg[i]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffe #(64) fifo_data_dff (
.din (fifo_data_in[i]),
.dout(fifo_data[i]),
.en (fifo_data_en[i]),
.*
);
rvdffs #(pt.DMA_BUS_TAG) fifo_tag_dff (
.din (bus_cmd_tag[pt.DMA_BUS_TAG-1:0]),
.dout(fifo_tag[i][pt.DMA_BUS_TAG-1:0]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(pt.DMA_BUS_ID) fifo_mid_dff (
.din (bus_cmd_mid[pt.DMA_BUS_ID-1:0]),
.dout(fifo_mid[i][pt.DMA_BUS_ID-1:0]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
rvdffs #(pt.DMA_BUS_PRTY) fifo_prty_dff (
.din (bus_cmd_prty[pt.DMA_BUS_PRTY-1:0]),
.dout(fifo_prty[i][pt.DMA_BUS_PRTY-1:0]),
.en (fifo_cmd_en[i]),
.clk (dma_buffer_c1_clk),
.*
);
end
// Pointer logic
@ -286,17 +386,35 @@ module el2_dma_ctrl #(
assign RdPtrEn = dma_dccm_req | dma_iccm_req | (dma_address_error | dma_alignment_error | dma_dbg_cmd_error);
assign RspPtrEn = (dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en);
rvdffs #(DEPTH_PTR) WrPtr_dff(.din(NxtWrPtr[DEPTH_PTR-1:0]), .dout(WrPtr[DEPTH_PTR-1:0]), .en(WrPtrEn), .clk(dma_free_clk), .*);
rvdffs #(DEPTH_PTR) RdPtr_dff(.din(NxtRdPtr[DEPTH_PTR-1:0]), .dout(RdPtr[DEPTH_PTR-1:0]), .en(RdPtrEn), .clk(dma_free_clk), .*);
rvdffs #(DEPTH_PTR) RspPtr_dff(.din(NxtRspPtr[DEPTH_PTR-1:0]), .dout(RspPtr[DEPTH_PTR-1:0]), .en(RspPtrEn), .clk(dma_free_clk), .*);
rvdffs #(DEPTH_PTR) WrPtr_dff (
.din (NxtWrPtr[DEPTH_PTR-1:0]),
.dout(WrPtr[DEPTH_PTR-1:0]),
.en (WrPtrEn),
.clk (dma_free_clk),
.*
);
rvdffs #(DEPTH_PTR) RdPtr_dff (
.din (NxtRdPtr[DEPTH_PTR-1:0]),
.dout(RdPtr[DEPTH_PTR-1:0]),
.en (RdPtrEn),
.clk (dma_free_clk),
.*
);
rvdffs #(DEPTH_PTR) RspPtr_dff (
.din (NxtRspPtr[DEPTH_PTR-1:0]),
.dout(RspPtr[DEPTH_PTR-1:0]),
.en (RspPtrEn),
.clk (dma_free_clk),
.*
);
// Miscellaneous signals
assign fifo_full = fifo_full_spec_bus;
always_comb begin
num_fifo_vld[3:0] = {3'b0,bus_cmd_sent} - {3'b0,bus_rsp_sent};
for (int i=0; i<DEPTH; i++) begin
num_fifo_vld[3:0] += {3'b0,fifo_valid[i]};
num_fifo_vld[3:0] = {3'b0, bus_cmd_sent} - {3'b0, bus_rsp_sent};
for (int i = 0; i < DEPTH; i++) begin
num_fifo_vld[3:0] += {3'b0, fifo_valid[i]};
end
end
assign fifo_full_spec = (num_fifo_vld[3:0] >= DEPTH);
@ -318,7 +436,7 @@ module el2_dma_ctrl #(
//Dbg outputs
assign dma_dbg_ready = fifo_empty & dbg_dma_bubble;
assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & fifo_done[RspPtr]);
assign dma_dbg_cmd_fail = (|fifo_error[RspPtr] & dma_dbg_cmd_done) ;
assign dma_dbg_cmd_fail = (|fifo_error[RspPtr] & dma_dbg_cmd_done);
assign dma_dbg_sz[1:0] = fifo_sz[RspPtr][1:0];
assign dma_dbg_addr[1:0] = fifo_addr[RspPtr][1:0];
@ -347,7 +465,13 @@ module el2_dma_ctrl #(
assign dma_nack_count_d[2:0] = (dma_nack_count[2:0] >= dma_nack_count_csr[2:0]) ? ({3{~(dma_dccm_req | dma_iccm_req)}} & dma_nack_count[2:0]) :
(dma_mem_req & ~(dma_dccm_req | dma_iccm_req)) ? (dma_nack_count[2:0] + 1'b1) : 3'b0;
rvdffs #(3) nack_count_dff(.din(dma_nack_count_d[2:0]), .dout(dma_nack_count[2:0]), .en(dma_mem_req), .clk(dma_free_clk), .*);
rvdffs #(3) nack_count_dff (
.din (dma_nack_count_d[2:0]),
.dout(dma_nack_count[2:0]),
.en (dma_mem_req),
.clk (dma_free_clk),
.*
);
// Core outputs
assign dma_mem_req = fifo_valid[RdPtr] & ~fifo_rpend[RdPtr] & ~fifo_done[RdPtr] & ~(dma_address_error | dma_alignment_error | dma_dbg_cmd_error);
@ -369,53 +493,90 @@ module el2_dma_ctrl #(
assign dma_pmu_any_write = (dma_dccm_req | dma_iccm_req) & dma_mem_write;
// Address check dccm
if (pt.DCCM_ENABLE) begin: Gen_dccm_enable
rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)) addr_dccm_rangecheck (
if (pt.DCCM_ENABLE) begin : Gen_dccm_enable
rvrangecheck #(
.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)
) addr_dccm_rangecheck (
.addr(dma_mem_addr_int[31:0]),
.in_range(dma_mem_addr_in_dccm),
.in_region(dma_mem_addr_in_dccm_region_nc)
);
end else begin: Gen_dccm_disable
end else begin : Gen_dccm_disable
assign dma_mem_addr_in_dccm = '0;
assign dma_mem_addr_in_dccm_region_nc = '0;
end // else: !if(pt.ICCM_ENABLE)
// Address check iccm
if (pt.ICCM_ENABLE) begin: Gen_iccm_enable
rvrangecheck #(.CCM_SADR(pt.ICCM_SADR),
.CCM_SIZE(pt.ICCM_SIZE)) addr_iccm_rangecheck (
if (pt.ICCM_ENABLE) begin : Gen_iccm_enable
rvrangecheck #(
.CCM_SADR(pt.ICCM_SADR),
.CCM_SIZE(pt.ICCM_SIZE)
) addr_iccm_rangecheck (
.addr(dma_mem_addr_int[31:0]),
.in_range(dma_mem_addr_in_iccm),
.in_region(dma_mem_addr_in_iccm_region_nc)
);
end else begin: Gen_iccm_disable
end else begin : Gen_iccm_disable
assign dma_mem_addr_in_iccm = '0;
assign dma_mem_addr_in_iccm_region_nc = '0;
end // else: !if(pt.ICCM_ENABLE)
// PIC memory address check
rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)) addr_pic_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)
) addr_pic_rangecheck (
.addr(dma_mem_addr_int[31:0]),
.in_range(dma_mem_addr_in_pic),
.in_region(dma_mem_addr_in_pic_region_nc)
);
// Inputs
rvdff_fpga #(1) fifo_full_bus_ff (.din(fifo_full_spec), .dout(fifo_full_spec_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) dbg_dma_bubble_ff (.din(dbg_dma_bubble), .dout(dbg_dma_bubble_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff #(1) dma_dbg_cmd_doneff (.din(dma_dbg_cmd_done), .dout(dma_dbg_cmd_done_q), .clk(free_clk), .*);
rvdff_fpga #(1) fifo_full_bus_ff (
.din(fifo_full_spec),
.dout(fifo_full_spec_bus),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(1) dbg_dma_bubble_ff (
.din(dbg_dma_bubble),
.dout(dbg_dma_bubble_bus),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdff #(1) dma_dbg_cmd_doneff (
.din (dma_dbg_cmd_done),
.dout(dma_dbg_cmd_done_q),
.clk (free_clk),
.*
);
// Clock Gating logic
assign dma_buffer_c1_clken = (bus_cmd_valid & dma_bus_clk_en) | dbg_cmd_valid | clk_override;
assign dma_free_clken = (bus_cmd_valid | bus_rsp_valid | dbg_cmd_valid | dma_dbg_cmd_done | dma_dbg_cmd_done_q | (|fifo_valid[DEPTH-1:0]) | clk_override);
rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
rvoclkhdr dma_buffer_c1cgc (
.en(dma_buffer_c1_clken),
.l1clk(dma_buffer_c1_clk),
.*
);
rvoclkhdr dma_free_cgc (
.en(dma_free_clken),
.l1clk(dma_free_clk),
.*
);
rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);
rvclkhdr dma_bus_cgc (
.en(dma_bus_clk_en),
.l1clk(dma_bus_clk),
.*
);
// Write channel buffer
assign wrbuf_en = dma_axi_awvalid & dma_axi_awready;
@ -424,23 +585,127 @@ module el2_dma_ctrl #(
assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en;
assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;
rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff (.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_data_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(pt.DMA_BUS_TAG)) wrbuf_tagff (.din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(3)) wrbuf_szff (.din(dma_axi_awsize[2:0]), .dout(wrbuf_sz[2:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(dma_axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & dma_bus_clk_en), .*);
rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(dma_axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & dma_bus_clk_en), .*);
rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff (.din(dma_axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(
.WIDTH(1)
) wrbuf_vldff (
.din(1'b1),
.dout(wrbuf_vld),
.en(wrbuf_en),
.clear(wrbuf_rst),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffsc_fpga #(
.WIDTH(1)
) wrbuf_data_vldff (
.din(1'b1),
.dout(wrbuf_data_vld),
.en(wrbuf_data_en),
.clear(wrbuf_data_rst),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(pt.DMA_BUS_TAG)
) wrbuf_tagff (
.din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]),
.dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]),
.en(wrbuf_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(3)
) wrbuf_szff (
.din(dma_axi_awsize[2:0]),
.dout(wrbuf_sz[2:0]),
.en(wrbuf_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(32)
) wrbuf_addrff (
.din (dma_axi_awaddr[31:0]),
.dout(wrbuf_addr[31:0]),
.en (wrbuf_en & dma_bus_clk_en),
.*
);
rvdffe #(
.WIDTH(64)
) wrbuf_dataff (
.din (dma_axi_wdata[63:0]),
.dout(wrbuf_data[63:0]),
.en (wrbuf_data_en & dma_bus_clk_en),
.*
);
rvdffs_fpga #(
.WIDTH(8)
) wrbuf_byteenff (
.din(dma_axi_wstrb[7:0]),
.dout(wrbuf_byteen[7:0]),
.en(wrbuf_data_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
// Read channel buffer
assign rdbuf_en = dma_axi_arvalid & dma_axi_arready;
assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write;
assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en;
rvdffsc_fpga #(.WIDTH(1)) rdbuf_vldff (.din(1'b1), .dout(rdbuf_vld), .en(rdbuf_en), .clear(rdbuf_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(pt.DMA_BUS_TAG)) rdbuf_tagff (.din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(3)) rdbuf_szff (.din(dma_axi_arsize[2:0]), .dout(rdbuf_sz[2:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) rdbuf_addrff (.din(dma_axi_araddr[31:0]), .dout(rdbuf_addr[31:0]), .en(rdbuf_en & dma_bus_clk_en), .*);
rvdffsc_fpga #(
.WIDTH(1)
) rdbuf_vldff (
.din(1'b1),
.dout(rdbuf_vld),
.en(rdbuf_en),
.clear(rdbuf_rst),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(pt.DMA_BUS_TAG)
) rdbuf_tagff (
.din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]),
.dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]),
.en(rdbuf_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(3)
) rdbuf_szff (
.din(dma_axi_arsize[2:0]),
.dout(rdbuf_sz[2:0]),
.en(rdbuf_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(32)
) rdbuf_addrff (
.din (dma_axi_araddr[31:0]),
.dout(rdbuf_addr[31:0]),
.en (rdbuf_en & dma_bus_clk_en),
.*
);
assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent);
assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent);
@ -463,7 +728,17 @@ module el2_dma_ctrl #(
assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld);
assign axi_mstr_prty_in = ~axi_mstr_priority;
assign axi_mstr_prty_en = bus_cmd_sent;
rvdffs_fpga #(.WIDTH(1)) mstr_prtyff(.din(axi_mstr_prty_in), .dout(axi_mstr_priority), .en(axi_mstr_prty_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(
.WIDTH(1)
) mstr_prtyff (
.din(axi_mstr_prty_in),
.dout(axi_mstr_priority),
.en(axi_mstr_prty_en),
.clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.*
);
assign axi_rsp_valid = fifo_valid[RspPtr] & ~fifo_dbg[RspPtr] & fifo_done_bus[RspPtr];
assign axi_rsp_rdata[63:0] = fifo_data[RspPtr];

60
Flow/design/el2_mem.sv
View File

@ -16,11 +16,10 @@
//********************************************************************************
module el2_mem
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
@ -30,10 +29,10 @@ import el2_pkg::*;
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
@ -41,10 +40,10 @@ import el2_pkg::*;
output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef pt.DCCM_ENABLE
//`ifdef pt.DCCM_ENABLE
input el2_dccm_ext_in_pkt_t [pt.DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
//`endif
//`endif
//ICCM ports
input el2_ccm_ext_in_pkt_t [pt.ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
@ -81,12 +80,12 @@ import el2_pkg::*;
input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
output logic [25:0] ictag_debug_rd_data, // Debug icache tag.
output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic [ pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
@ -95,45 +94,54 @@ import el2_pkg::*;
);
logic active_clk;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
rvoclkhdr active_cg (
.en(1'b1),
.l1clk(active_clk),
.*
);
// DCCM Instantiation
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
el2_lsu_dccm_mem #(.pt(pt)) dccm (
if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
el2_lsu_dccm_mem #(
.pt(pt)
) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
end else begin : Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( pt.ICACHE_ENABLE ) begin: icache
el2_ifu_ic_mem #(.pt(pt)) icm (
if (pt.ICACHE_ENABLE) begin : icache
el2_ifu_ic_mem #(
.pt(pt)
) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
end else begin
assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ;
end // else: !if( pt.ICACHE_ENABLE )
end // else: !if( pt.ICACHE_ENABLE )
if (pt.ICCM_ENABLE) begin : iccm
el2_ifu_iccm_mem #(.pt(pt)) iccm (.*,
if (pt.ICCM_ENABLE) begin : iccm
el2_ifu_iccm_mem #(
.pt(pt)
) iccm (
.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
end else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
end
endmodule

659
Flow/design/el2_pic_ctrl.sv
View File

@ -21,9 +21,8 @@
//********************************************************************************
module el2_pic_ctrl #(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Core clock
input logic free_clk, // free clock
@ -31,117 +30,117 @@ module el2_pic_ctrl #(
input logic clk_override, // Clock over-ride for gating
input logic io_clk_override, // PIC IO Clock over-ride for gating
input logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req, // Interrupt requests
input logic [31:0] picm_rdaddr, // Address of the register
input logic [31:0] picm_wraddr, // Address of the register
input logic [31:0] picm_wr_data, // Data to be written to the register
input logic [ 31:0] picm_rdaddr, // Address of the register
input logic [ 31:0] picm_wraddr, // Address of the register
input logic [ 31:0] picm_wr_data, // Data to be written to the register
input logic picm_wren, // Write enable to the register
input logic picm_rden, // Read enable for the register
input logic picm_mken, // Read the Mask for the register
input logic [3:0] meicurpl, // Current Priority Level
input logic [3:0] meipt, // Current Priority Threshold
input logic [ 3:0] meicurpl, // Current Priority Level
input logic [ 3:0] meipt, // Current Priority Threshold
output logic mexintpend, // External Inerrupt request to the core
output logic [7:0] claimid, // Claim Id of the requested interrupt
output logic [3:0] pl, // Priority level of the requested interrupt
output logic [ 7:0] claimid, // Claim Id of the requested interrupt
output logic [ 3:0] pl, // Priority level of the requested interrupt
output logic [31:0] picm_rd_data, // Read data of the register
output logic mhwakeup, // Wake-up interrupt request
input logic scan_mode // scan mode
);
localparam NUM_LEVELS = $clog2(pt.PIC_TOTAL_INT_PLUS1);
localparam INTPRIORITY_BASE_ADDR = pt.PIC_BASE_ADDR ;
localparam INTPEND_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00001000 ;
localparam INTENABLE_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00002000 ;
localparam EXT_INTR_PIC_CONFIG = pt.PIC_BASE_ADDR + 32'h00003000 ;
localparam EXT_INTR_GW_CONFIG = pt.PIC_BASE_ADDR + 32'h00004000 ;
localparam EXT_INTR_GW_CLEAR = pt.PIC_BASE_ADDR + 32'h00005000 ;
localparam NUM_LEVELS = $clog2(pt.PIC_TOTAL_INT_PLUS1);
localparam INTPRIORITY_BASE_ADDR = pt.PIC_BASE_ADDR;
localparam INTPEND_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00001000;
localparam INTENABLE_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00002000;
localparam EXT_INTR_PIC_CONFIG = pt.PIC_BASE_ADDR + 32'h00003000;
localparam EXT_INTR_GW_CONFIG = pt.PIC_BASE_ADDR + 32'h00004000;
localparam EXT_INTR_GW_CLEAR = pt.PIC_BASE_ADDR + 32'h00005000;
localparam INTPEND_SIZE = (pt.PIC_TOTAL_INT_PLUS1 < 32) ? 32 :
localparam INTPEND_SIZE = (pt.PIC_TOTAL_INT_PLUS1 < 32) ? 32 :
(pt.PIC_TOTAL_INT_PLUS1 < 64) ? 64 :
(pt.PIC_TOTAL_INT_PLUS1 < 128) ? 128 :
(pt.PIC_TOTAL_INT_PLUS1 < 256) ? 256 :
(pt.PIC_TOTAL_INT_PLUS1 < 512) ? 512 : 1024 ;
localparam INT_GRPS = INTPEND_SIZE / 32 ;
localparam INTPRIORITY_BITS = 4 ;
localparam ID_BITS = 8 ;
localparam int GW_CONFIG[pt.PIC_TOTAL_INT_PLUS1-1:0] = '{default:0} ;
localparam INT_GRPS = INTPEND_SIZE / 32;
localparam INTPRIORITY_BITS = 4;
localparam ID_BITS = 8;
localparam int GW_CONFIG[pt.PIC_TOTAL_INT_PLUS1-1:0] = '{default: 0};
localparam INT_ENABLE_GRPS = (pt.PIC_TOTAL_INT_PLUS1 - 1) / 4 ;
localparam INT_ENABLE_GRPS = (pt.PIC_TOTAL_INT_PLUS1 - 1) / 4;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_clk_enable ;
logic [INT_ENABLE_GRPS:0] intenable_clk_enable_grp ;
logic [INT_ENABLE_GRPS:0] gw_clk ;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_clk_enable;
logic [ INT_ENABLE_GRPS:0] intenable_clk_enable_grp;
logic [ INT_ENABLE_GRPS:0] gw_clk;
logic addr_intpend_base_match;
logic addr_intpend_base_match;
logic raddr_config_pic_match ;
logic raddr_intenable_base_match;
logic raddr_intpriority_base_match;
logic raddr_config_gw_base_match ;
logic raddr_config_pic_match;
logic raddr_intenable_base_match;
logic raddr_intpriority_base_match;
logic raddr_config_gw_base_match;
logic waddr_config_pic_match ;
logic waddr_intpriority_base_match;
logic waddr_intenable_base_match;
logic waddr_config_gw_base_match ;
logic addr_clear_gw_base_match ;
logic waddr_config_pic_match;
logic waddr_intpriority_base_match;
logic waddr_intenable_base_match;
logic waddr_config_gw_base_match;
logic addr_clear_gw_base_match;
logic mexintpend_in;
logic mhwakeup_in ;
logic intpend_reg_read ;
logic mexintpend_in;
logic mhwakeup_in;
logic intpend_reg_read;
logic [31:0] picm_rd_data_in, intpend_rd_out;
logic intenable_rd_out ;
logic [INTPRIORITY_BITS-1:0] intpriority_rd_out;
logic [1:0] gw_config_rd_out;
logic [31:0] picm_rd_data_in, intpend_rd_out;
logic intenable_rd_out;
logic [ INTPRIORITY_BITS-1:0] intpriority_rd_out;
logic [ 1:0] gw_config_rd_out;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpriority_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpriority_reg_inv;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] [1:0] gw_config_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0][INTPRIORITY_BITS-1:0] intpriority_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0][INTPRIORITY_BITS-1:0] intpriority_reg_inv;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0][ 1:0] gw_config_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_clear_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_we;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_re;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_clear_reg_we;
logic [INTPEND_SIZE-1:0] intpend_reg_extended;
logic [ INTPEND_SIZE-1:0] intpend_reg_extended;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpend_w_prior_en;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] [ID_BITS-1:0] intpend_id;
logic [INTPRIORITY_BITS-1:0] maxint;
logic [INTPRIORITY_BITS-1:0] selected_int_priority;
logic [INT_GRPS-1:0] [31:0] intpend_rd_part_out ;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0][INTPRIORITY_BITS-1:0] intpend_w_prior_en;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0][ ID_BITS-1:0] intpend_id;
logic [ INTPRIORITY_BITS-1:0] maxint;
logic [ INTPRIORITY_BITS-1:0] selected_int_priority;
logic [ INT_GRPS-1:0][ 31:0] intpend_rd_part_out;
logic config_reg;
logic intpriord;
logic config_reg_we ;
logic config_reg_re ;
logic config_reg_in ;
logic prithresh_reg_write , prithresh_reg_read;
logic intpriority_reg_read ;
logic intenable_reg_read ;
logic gw_config_reg_read ;
logic picm_wren_ff , picm_rden_ff ;
logic [31:0] picm_raddr_ff;
logic [31:0] picm_waddr_ff;
logic [31:0] picm_wr_data_ff;
logic [3:0] mask;
logic picm_mken_ff;
logic [ID_BITS-1:0] claimid_in ;
logic [INTPRIORITY_BITS-1:0] pl_in ;
logic [INTPRIORITY_BITS-1:0] pl_in_q ;
logic config_reg;
logic intpriord;
logic config_reg_we;
logic config_reg_re;
logic config_reg_in;
logic prithresh_reg_write, prithresh_reg_read;
logic intpriority_reg_read;
logic intenable_reg_read;
logic gw_config_reg_read;
logic picm_wren_ff, picm_rden_ff;
logic [ 31:0] picm_raddr_ff;
logic [ 31:0] picm_waddr_ff;
logic [ 31:0] picm_wr_data_ff;
logic [ 3:0] mask;
logic picm_mken_ff;
logic [ ID_BITS-1:0] claimid_in;
logic [ INTPRIORITY_BITS-1:0] pl_in;
logic [ INTPRIORITY_BITS-1:0] pl_in_q;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_sync;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_gw;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_sync;
logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_gw;
logic picm_bypass_ff;
// clkens
// clkens
logic pic_raddr_c1_clken;
logic pic_waddr_c1_clken;
logic pic_data_c1_clken;
@ -149,15 +148,15 @@ logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_gw;
logic pic_int_c1_clken;
logic gw_config_c1_clken;
// clocks
// clocks
logic pic_raddr_c1_clk;
logic pic_data_c1_clk;
logic pic_pri_c1_clk;
logic pic_int_c1_clk;
logic gw_config_c1_clk;
// ---- Clock gating section ------
// c1 clock enables
// ---- Clock gating section ------
// c1 clock enables
assign pic_raddr_c1_clken = picm_mken | picm_rden | clk_override;
assign pic_data_c1_clken = picm_wren | clk_override;
assign pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | clk_override;
@ -165,46 +164,96 @@ logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_gw;
assign gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | clk_override;
// C1 - 1 clock pulse for data
rvoclkhdr pic_addr_c1_cgc ( .en(pic_raddr_c1_clken), .l1clk(pic_raddr_c1_clk), .* );
rvoclkhdr pic_data_c1_cgc ( .en(pic_data_c1_clken), .l1clk(pic_data_c1_clk), .* );
rvoclkhdr pic_pri_c1_cgc ( .en(pic_pri_c1_clken), .l1clk(pic_pri_c1_clk), .* );
rvoclkhdr pic_int_c1_cgc ( .en(pic_int_c1_clken), .l1clk(pic_int_c1_clk), .* );
rvoclkhdr gw_config_c1_cgc ( .en(gw_config_c1_clken), .l1clk(gw_config_c1_clk), .* );
rvoclkhdr pic_addr_c1_cgc (
.en(pic_raddr_c1_clken),
.l1clk(pic_raddr_c1_clk),
.*
);
rvoclkhdr pic_data_c1_cgc (
.en(pic_data_c1_clken),
.l1clk(pic_data_c1_clk),
.*
);
rvoclkhdr pic_pri_c1_cgc (
.en(pic_pri_c1_clken),
.l1clk(pic_pri_c1_clk),
.*
);
rvoclkhdr pic_int_c1_cgc (
.en(pic_int_c1_clken),
.l1clk(pic_int_c1_clk),
.*
);
rvoclkhdr gw_config_c1_cgc (
.en(gw_config_c1_clken),
.l1clk(gw_config_c1_clk),
.*
);
// ------ end clock gating section ------------------------
// ------ end clock gating section ------------------------
assign raddr_intenable_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign raddr_intpriority_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign raddr_config_gw_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;
assign raddr_config_pic_match = (picm_raddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]) ;
assign raddr_intenable_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign raddr_intpriority_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign raddr_config_gw_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;
assign raddr_config_pic_match = (picm_raddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]);
assign addr_intpend_base_match = (picm_raddr_ff[31:6] == INTPEND_BASE_ADDR[31:6]) ;
assign addr_intpend_base_match = (picm_raddr_ff[31:6] == INTPEND_BASE_ADDR[31:6]);
assign waddr_config_pic_match = (picm_waddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]) ;
assign addr_clear_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS+2]) ;
assign waddr_intpriority_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign waddr_intenable_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign waddr_config_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;
assign waddr_config_pic_match = (picm_waddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]);
assign addr_clear_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS+2]) ;
assign waddr_intpriority_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign waddr_intenable_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;
assign waddr_config_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;
assign picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff[31:0] == picm_waddr_ff[31:0] ); // pic writes and reads to same address together
rvdff #(32) picm_radd_flop (.*, .din (picm_rdaddr), .dout(picm_raddr_ff), .clk(pic_raddr_c1_clk));
rvdff #(32) picm_wadd_flop (.*, .din (picm_wraddr), .dout(picm_waddr_ff), .clk(pic_data_c1_clk));
rvdff #(1) picm_wre_flop (.*, .din (picm_wren), .dout(picm_wren_ff), .clk(free_clk));
rvdff #(1) picm_rde_flop (.*, .din (picm_rden), .dout(picm_rden_ff), .clk(free_clk));
rvdff #(1) picm_mke_flop (.*, .din (picm_mken), .dout(picm_mken_ff), .clk(free_clk));
rvdff #(32) picm_dat_flop (.*, .din (picm_wr_data[31:0]), .dout(picm_wr_data_ff[31:0]), .clk(pic_data_c1_clk));
rvdff #(32) picm_radd_flop (
.*,
.din (picm_rdaddr),
.dout(picm_raddr_ff),
.clk (pic_raddr_c1_clk)
);
rvdff #(32) picm_wadd_flop (
.*,
.din (picm_wraddr),
.dout(picm_waddr_ff),
.clk (pic_data_c1_clk)
);
rvdff #(1) picm_wre_flop (
.*,
.din (picm_wren),
.dout(picm_wren_ff),
.clk (free_clk)
);
rvdff #(1) picm_rde_flop (
.*,
.din (picm_rden),
.dout(picm_rden_ff),
.clk (free_clk)
);
rvdff #(1) picm_mke_flop (
.*,
.din (picm_mken),
.dout(picm_mken_ff),
.clk (free_clk)
);
rvdff #(32) picm_dat_flop (
.*,
.din (picm_wr_data[31:0]),
.dout(picm_wr_data_ff[31:0]),
.clk (pic_data_c1_clk)
);
//rvsyncss #(pt.PIC_TOTAL_INT_PLUS1-1) sync_inst
//(
// .clk (free_clk),
// .dout(extintsrc_req_sync[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .din (extintsrc_req[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .*) ;
//
//assign extintsrc_req_sync[0] = extintsrc_req[0];
/*
//rvsyncss #(pt.PIC_TOTAL_INT_PLUS1-1) sync_inst
//(
// .clk (free_clk),
// .dout(extintsrc_req_sync[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .din (extintsrc_req[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .*) ;
//
//assign extintsrc_req_sync[0] = extintsrc_req[0];
/*
genvar p ;
for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP
if (p==INT_ENABLE_GRPS) begin : LAST_GRP
@ -219,29 +268,37 @@ end
genvar i ;
genvar p ;
for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP
wire grp_clk, grp_clken;
genvar i;
genvar p;
for (p = 0; p <= INT_ENABLE_GRPS; p++) begin : IO_CLK_GRP
wire grp_clk, grp_clken;
assign grp_clken = |intenable_clk_enable[(p==INT_ENABLE_GRPS?pt.PIC_TOTAL_INT_PLUS1-1:p*4+3) : p*4] | io_clk_override;
rvclkhdr intenable_c1_cgc( .en(grp_clken), .l1clk(grp_clk), .* );
rvclkhdr intenable_c1_cgc (
.en(grp_clken),
.l1clk(grp_clk),
.*
);
for(genvar i= (p==0 ? 1: 0); i< (p==INT_ENABLE_GRPS ? pt.PIC_TOTAL_INT_PLUS1-p*4 :4); i++) begin : GW
el2_configurable_gw gw_inst(
for (
genvar i = (p == 0 ? 1 : 0);
i < (p == INT_ENABLE_GRPS ? pt.PIC_TOTAL_INT_PLUS1 - p * 4 : 4);
i++
) begin : GW
el2_configurable_gw gw_inst (
.*,
.gw_clk(grp_clk),
.rawclk(clk),
.clken (grp_clken),
.extintsrc_req(extintsrc_req[i+p*4]) ,
.meigwctrl_polarity(gw_config_reg[i+p*4][0]) ,
.meigwctrl_type(gw_config_reg[i+p*4][1]) ,
.meigwclr(gw_clear_reg_we[i+p*4]) ,
.clken(grp_clken),
.extintsrc_req(extintsrc_req[i+p*4]),
.meigwctrl_polarity(gw_config_reg[i+p*4][0]),
.meigwctrl_type(gw_config_reg[i+p*4][1]),
.meigwclr(gw_clear_reg_we[i+p*4]),
.extintsrc_req_config(extintsrc_req_gw[i+p*4])
);
end
end
end
@ -250,9 +307,9 @@ end
for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
for (i = 0; i < pt.PIC_TOTAL_INT_PLUS1; i++) begin : SETREG
if (i > 0 ) begin : NON_ZERO_INT
if (i > 0) begin : NON_ZERO_INT
assign intpriority_reg_we[i] = waddr_intpriority_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff;
assign intpriority_reg_re[i] = raddr_intpriority_base_match & (picm_raddr_ff[NUM_LEVELS+1:2] == i) & picm_rden_ff;
@ -264,13 +321,31 @@ for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
assign gw_clear_reg_we[i] = addr_clear_gw_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff ;
rvdffs #(INTPRIORITY_BITS) intpriority_ff (.*, .en( intpriority_reg_we[i]), .din (picm_wr_data_ff[INTPRIORITY_BITS-1:0]), .dout(intpriority_reg[i]), .clk(pic_pri_c1_clk));
rvdffs #(1) intenable_ff (.*, .en( intenable_reg_we[i]), .din (picm_wr_data_ff[0]), .dout(intenable_reg[i]), .clk(pic_int_c1_clk));
rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk));
rvdffs #(INTPRIORITY_BITS) intpriority_ff (
.*,
.en (intpriority_reg_we[i]),
.din (picm_wr_data_ff[INTPRIORITY_BITS-1:0]),
.dout(intpriority_reg[i]),
.clk (pic_pri_c1_clk)
);
rvdffs #(1) intenable_ff (
.*,
.en (intenable_reg_we[i]),
.din (picm_wr_data_ff[0]),
.dout(intenable_reg[i]),
.clk (pic_int_c1_clk)
);
rvdffs #(2) gw_config_ff (
.*,
.en (gw_config_reg_we[i]),
.din (picm_wr_data_ff[1:0]),
.dout(gw_config_reg[i]),
.clk (gw_config_c1_clk)
);
assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ;
/*
/*
rvsyncss_fpga #(1) sync_inst
(
.gw_clk (gw_clk[i/4]),
@ -316,189 +391,247 @@ for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
end
assign intpriority_reg_inv[i] = intpriord ? ~intpriority_reg[i] : intpriority_reg[i] ;
assign intpriority_reg_inv[i] = intpriord ? ~intpriority_reg[i] : intpriority_reg[i];
assign intpend_w_prior_en[i] = {INTPRIORITY_BITS{(extintsrc_req_gw[i] & intenable_reg[i])}} & intpriority_reg_inv[i] ;
assign intpend_id[i] = i ;
end
assign intpend_id[i] = i;
end
assign pl_in[INTPRIORITY_BITS-1:0] = selected_int_priority[INTPRIORITY_BITS-1:0] ;
assign pl_in[INTPRIORITY_BITS-1:0] = selected_int_priority[INTPRIORITY_BITS-1:0];
//if (pt.PIC_2CYCLE == 1) begin : genblock
//end
//else begin : genblock
//end
//if (pt.PIC_2CYCLE == 1) begin : genblock
//end
//else begin : genblock
//end
genvar l, m , j, k;
genvar l, m, j, k;
if (pt.PIC_2CYCLE == 1) begin : genblock
if (pt.PIC_2CYCLE == 1) begin : genblock
logic [NUM_LEVELS/2:0] [pt.PIC_TOTAL_INT_PLUS1+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en;
logic [NUM_LEVELS/2:0] [pt.PIC_TOTAL_INT_PLUS1+2:0] [ID_BITS-1:0] level_intpend_id;
logic [NUM_LEVELS/2:0][pt.PIC_TOTAL_INT_PLUS1+2:0][ID_BITS-1:0] level_intpend_id;
logic [NUM_LEVELS:NUM_LEVELS/2] [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en;
logic [NUM_LEVELS:NUM_LEVELS/2] [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] [ID_BITS-1:0] levelx_intpend_id;
assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {4'b0,4'b0,4'b0,intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {8'b0,8'b0,8'b0,intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {
4'b0, 4'b0, 4'b0, intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]
};
assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {
8'b0, 8'b0, 8'b0, intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]
};
logic [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0] [INTPRIORITY_BITS-1:0] l2_intpend_w_prior_en_ff;
logic [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0] [ID_BITS-1:0] l2_intpend_id_ff;
logic [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0][ID_BITS-1:0] l2_intpend_id_ff;
assign levelx_intpend_w_prior_en[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {{1*INTPRIORITY_BITS{1'b0}},l2_intpend_w_prior_en_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]} ;
assign levelx_intpend_id[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {{1*ID_BITS{1'b1}},l2_intpend_id_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]} ;
/// Do the prioritization of the interrupts here ////////////
for (l=0; l<NUM_LEVELS/2 ; l++) begin : TOP_LEVEL
for (m=0; m<=(pt.PIC_TOTAL_INT_PLUS1)/(2**(l+1)) ; m++) begin : COMPARE
if ( m == (pt.PIC_TOTAL_INT_PLUS1)/(2**(l+1))) begin
assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
assign level_intpend_id[l+1][m+1] = '0 ;
assign levelx_intpend_w_prior_en[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {
{1 * INTPRIORITY_BITS{1'b0}},
l2_intpend_w_prior_en_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]
};
assign levelx_intpend_id[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {
{1 * ID_BITS{1'b1}}, l2_intpend_id_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]
};
/// Do the prioritization of the interrupts here ////////////
for (l = 0; l < NUM_LEVELS / 2; l++) begin : TOP_LEVEL
for (m = 0; m <= (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (l + 1)); m++) begin : COMPARE
if (m == (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (l + 1))) begin
assign level_intpend_w_prior_en[l+1][m+1] = '0;
assign level_intpend_id[l+1][m+1] = '0;
end
el2_cmp_and_mux #(.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
el2_cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)
) cmp_l1 (
.a_id(level_intpend_id[l][2*m]),
.a_priority(level_intpend_w_prior_en[l][2*m]),
.b_id(level_intpend_id[l][2*m+1]),
.b_priority(level_intpend_w_prior_en[l][2*m+1]),
.out_id(level_intpend_id[l+1][m]),
.out_priority(level_intpend_w_prior_en[l+1][m])) ;
.out_priority(level_intpend_w_prior_en[l+1][m])
);
end
end
for (i=0; i<=pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2) ; i++) begin : MIDDLE_FLOPS
rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (.*, .din (level_intpend_w_prior_en[NUM_LEVELS/2][i]), .dout(l2_intpend_w_prior_en_ff[i]), .clk(free_clk));
rvdff #(ID_BITS) level2_intpend_id_reg (.*, .din (level_intpend_id[NUM_LEVELS/2][i]), .dout(l2_intpend_id_ff[i]), .clk(free_clk));
for (i = 0; i <= pt.PIC_TOTAL_INT_PLUS1 / 2 ** (NUM_LEVELS / 2); i++) begin : MIDDLE_FLOPS
rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (
.*,
.din (level_intpend_w_prior_en[NUM_LEVELS/2][i]),
.dout(l2_intpend_w_prior_en_ff[i]),
.clk (free_clk)
);
rvdff #(ID_BITS) level2_intpend_id_reg (
.*,
.din (level_intpend_id[NUM_LEVELS/2][i]),
.dout(l2_intpend_id_ff[i]),
.clk (free_clk)
);
end
for (j=NUM_LEVELS/2; j<NUM_LEVELS ; j++) begin : BOT_LEVELS
for (k=0; k<=(pt.PIC_TOTAL_INT_PLUS1)/(2**(j+1)) ; k++) begin : COMPARE
if ( k == (pt.PIC_TOTAL_INT_PLUS1)/(2**(j+1))) begin
assign levelx_intpend_w_prior_en[j+1][k+1] = '0 ;
assign levelx_intpend_id[j+1][k+1] = '0 ;
for (j = NUM_LEVELS / 2; j < NUM_LEVELS; j++) begin : BOT_LEVELS
for (k = 0; k <= (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (j + 1)); k++) begin : COMPARE
if (k == (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (j + 1))) begin
assign levelx_intpend_w_prior_en[j+1][k+1] = '0;
assign levelx_intpend_id[j+1][k+1] = '0;
end
el2_cmp_and_mux #(.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS))
cmp_l1 (
el2_cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)
) cmp_l1 (
.a_id(levelx_intpend_id[j][2*k]),
.a_priority(levelx_intpend_w_prior_en[j][2*k]),
.b_id(levelx_intpend_id[j][2*k+1]),
.b_priority(levelx_intpend_w_prior_en[j][2*k+1]),
.out_id(levelx_intpend_id[j+1][k]),
.out_priority(levelx_intpend_w_prior_en[j+1][k])) ;
.out_priority(levelx_intpend_w_prior_en[j+1][k])
);
end
end
assign claimid_in[ID_BITS-1:0] = levelx_intpend_id[NUM_LEVELS][0] ; // This is the last level output
assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en[NUM_LEVELS][0] ;
end
else begin : genblock
assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en[NUM_LEVELS][0];
end else begin : genblock
logic [NUM_LEVELS:0] [pt.PIC_TOTAL_INT_PLUS1+1:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en;
logic [NUM_LEVELS:0] [pt.PIC_TOTAL_INT_PLUS1+1:0] [ID_BITS-1:0] level_intpend_id;
logic [NUM_LEVELS:0][pt.PIC_TOTAL_INT_PLUS1+1:0][ID_BITS-1:0] level_intpend_id;
assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {{2*INTPRIORITY_BITS{1'b0}},intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {{2*ID_BITS{1'b1}},intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {
{2 * INTPRIORITY_BITS{1'b0}}, intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]
};
assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {
{2 * ID_BITS{1'b1}}, intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]
};
/// Do the prioritization of the interrupts here ////////////
// genvar l, m , j, k; already declared outside ifdef
for (l=0; l<NUM_LEVELS ; l++) begin : LEVEL
for (m=0; m<=(pt.PIC_TOTAL_INT_PLUS1)/(2**(l+1)) ; m++) begin : COMPARE
if ( m == (pt.PIC_TOTAL_INT_PLUS1)/(2**(l+1))) begin
assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
assign level_intpend_id[l+1][m+1] = '0 ;
/// Do the prioritization of the interrupts here ////////////
// genvar l, m , j, k; already declared outside ifdef
for (l = 0; l < NUM_LEVELS; l++) begin : LEVEL
for (m = 0; m <= (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (l + 1)); m++) begin : COMPARE
if (m == (pt.PIC_TOTAL_INT_PLUS1) / (2 ** (l + 1))) begin
assign level_intpend_w_prior_en[l+1][m+1] = '0;
assign level_intpend_id[l+1][m+1] = '0;
end
el2_cmp_and_mux #(.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
el2_cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)
) cmp_l1 (
.a_id(level_intpend_id[l][2*m]),
.a_priority(level_intpend_w_prior_en[l][2*m]),
.b_id(level_intpend_id[l][2*m+1]),
.b_priority(level_intpend_w_prior_en[l][2*m+1]),
.out_id(level_intpend_id[l+1][m]),
.out_priority(level_intpend_w_prior_en[l+1][m])) ;
.out_priority(level_intpend_w_prior_en[l+1][m])
);
end
end
assign claimid_in[ID_BITS-1:0] = level_intpend_id[NUM_LEVELS][0] ; // This is the last level output
assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en[NUM_LEVELS][0] ;
assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en[NUM_LEVELS][0];
end
end
///////////////////////////////////////////////////////////////////////
// Config Reg`
///////////////////////////////////////////////////////////////////////
assign config_reg_we = waddr_config_pic_match & picm_wren_ff;
assign config_reg_re = raddr_config_pic_match & picm_rden_ff;
///////////////////////////////////////////////////////////////////////
// Config Reg`
///////////////////////////////////////////////////////////////////////
assign config_reg_we = waddr_config_pic_match & picm_wren_ff;
assign config_reg_re = raddr_config_pic_match & picm_rden_ff;
assign config_reg_in = picm_wr_data_ff[0] ; //
rvdffs #(1) config_reg_ff (.*, .clk(free_clk), .en(config_reg_we), .din (config_reg_in), .dout(config_reg));
assign config_reg_in = picm_wr_data_ff[0]; //
rvdffs #(1) config_reg_ff (
.*,
.clk (free_clk),
.en (config_reg_we),
.din (config_reg_in),
.dout(config_reg)
);
assign intpriord = config_reg ;
assign intpriord = config_reg;
//////////////////////////////////////////////////////////////////////////
// Send the interrupt to the core if it is above the thresh-hold
//////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
/// ClaimId Reg and Corresponding PL
///////////////////////////////////////////////////////////
//
assign pl_in_q[INTPRIORITY_BITS-1:0] = intpriord ? ~pl_in : pl_in ;
rvdff #(ID_BITS) claimid_ff (.*, .din (claimid_in[ID_BITS-1:00]), .dout(claimid[ID_BITS-1:00]), .clk(free_clk));
rvdff #(INTPRIORITY_BITS) pl_ff (.*, .din (pl_in_q[INTPRIORITY_BITS-1:0]), .dout(pl[INTPRIORITY_BITS-1:0]), .clk(free_clk));
//////////////////////////////////////////////////////////////////////////
// Send the interrupt to the core if it is above the thresh-hold
//////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
/// ClaimId Reg and Corresponding PL
///////////////////////////////////////////////////////////
//
assign pl_in_q[INTPRIORITY_BITS-1:0] = intpriord ? ~pl_in : pl_in;
rvdff #(ID_BITS) claimid_ff (
.*,
.din (claimid_in[ID_BITS-1:00]),
.dout(claimid[ID_BITS-1:00]),
.clk (free_clk)
);
rvdff #(INTPRIORITY_BITS) pl_ff (
.*,
.din (pl_in_q[INTPRIORITY_BITS-1:0]),
.dout(pl[INTPRIORITY_BITS-1:0]),
.clk (free_clk)
);
logic [INTPRIORITY_BITS-1:0] meipt_inv , meicurpl_inv ;
assign meipt_inv[INTPRIORITY_BITS-1:0] = intpriord ? ~meipt[INTPRIORITY_BITS-1:0] : meipt[INTPRIORITY_BITS-1:0] ;
assign meicurpl_inv[INTPRIORITY_BITS-1:0] = intpriord ? ~meicurpl[INTPRIORITY_BITS-1:0] : meicurpl[INTPRIORITY_BITS-1:0] ;
assign mexintpend_in = (( selected_int_priority[INTPRIORITY_BITS-1:0] > meipt_inv[INTPRIORITY_BITS-1:0]) &
logic [INTPRIORITY_BITS-1:0] meipt_inv, meicurpl_inv;
assign meipt_inv[INTPRIORITY_BITS-1:0] = intpriord ? ~meipt[INTPRIORITY_BITS-1:0] : meipt[INTPRIORITY_BITS-1:0] ;
assign meicurpl_inv[INTPRIORITY_BITS-1:0] = intpriord ? ~meicurpl[INTPRIORITY_BITS-1:0] : meicurpl[INTPRIORITY_BITS-1:0] ;
assign mexintpend_in = (( selected_int_priority[INTPRIORITY_BITS-1:0] > meipt_inv[INTPRIORITY_BITS-1:0]) &
( selected_int_priority[INTPRIORITY_BITS-1:0] > meicurpl_inv[INTPRIORITY_BITS-1:0]) );
rvdff #(1) mexintpend_ff (.*, .clk(free_clk), .din (mexintpend_in), .dout(mexintpend));
rvdff #(1) mexintpend_ff (
.*,
.clk (free_clk),
.din (mexintpend_in),
.dout(mexintpend)
);
assign maxint[INTPRIORITY_BITS-1:0] = intpriord ? 0 : 15 ;
assign mhwakeup_in = ( pl_in_q[INTPRIORITY_BITS-1:0] == maxint) ;
rvdff #(1) wake_up_ff (.*, .clk(free_clk), .din (mhwakeup_in), .dout(mhwakeup));
assign maxint[INTPRIORITY_BITS-1:0] = intpriord ? 0 : 15;
assign mhwakeup_in = (pl_in_q[INTPRIORITY_BITS-1:0] == maxint);
rvdff #(1) wake_up_ff (
.*,
.clk (free_clk),
.din (mhwakeup_in),
.dout(mhwakeup)
);
//////////////////////////////////////////////////////////////////////////
// Reads of register.
// 1- intpending
//////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////
// Reads of register.
// 1- intpending
//////////////////////////////////////////////////////////////////////////
assign intpend_reg_read = addr_intpend_base_match & picm_rden_ff ;
assign intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff;
assign intenable_reg_read = raddr_intenable_base_match & picm_rden_ff;
assign gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff;
assign intpend_reg_read = addr_intpend_base_match & picm_rden_ff;
assign intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff;
assign intenable_reg_read = raddr_intenable_base_match & picm_rden_ff;
assign gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff;
assign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT_PLUS1{1'b0}},extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign intpend_reg_extended[INTPEND_SIZE-1:0] = {
{INTPEND_SIZE - pt.PIC_TOTAL_INT_PLUS1{1'b0}}, extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]
};
for (i=0; i<(INT_GRPS); i++) begin
for (i = 0; i < (INT_GRPS); i++) begin
assign intpend_rd_part_out[i] = (({32{intpend_reg_read & picm_raddr_ff[5:2] == i}}) & intpend_reg_extended[((32*i)+31):(32*i)]) ;
end
always_comb begin : INTPEND_RD
intpend_rd_out = '0 ;
for (int i=0; i<INT_GRPS; i++) begin
intpend_rd_out |= intpend_rd_part_out[i] ;
intpend_rd_out = '0;
for (int i = 0; i < INT_GRPS; i++) begin
intpend_rd_out |= intpend_rd_part_out[i];
end
end
always_comb begin : INTEN_RD
intenable_rd_out = '0 ;
intpriority_rd_out = '0 ;
gw_config_rd_out = '0 ;
for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
intenable_rd_out = '0;
intpriority_rd_out = '0;
gw_config_rd_out = '0;
for (int i = 0; i < pt.PIC_TOTAL_INT_PLUS1; i++) begin
if (intenable_reg_re[i]) begin
intenable_rd_out = intenable_reg[i] ;
intenable_rd_out = intenable_reg[i];
end
if (intpriority_reg_re[i]) begin
intpriority_rd_out = intpriority_reg[i] ;
intpriority_rd_out = intpriority_reg[i];
end
if (gw_config_reg_re[i]) begin
gw_config_rd_out = gw_config_reg[i] ;
gw_config_rd_out = gw_config_reg[i];
end
end
end
@ -515,38 +648,38 @@ assign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT
({32{picm_mken_ff & mask[0]}} & 32'b0 ) ;
assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0];
logic [14:0] address;
logic [14:0] address;
assign address[14:0] = picm_raddr_ff[14:0];
assign address[14:0] = picm_raddr_ff[14:0];
`include "pic_map_auto.h"
`include "pic_map_auto.h"
endmodule
module el2_cmp_and_mux #(parameter ID_BITS=8,
INTPRIORITY_BITS = 4)
(
input logic [ID_BITS-1:0] a_id,
module el2_cmp_and_mux #(
parameter ID_BITS = 8,
INTPRIORITY_BITS = 4
) (
input logic [ ID_BITS-1:0] a_id,
input logic [INTPRIORITY_BITS-1:0] a_priority,
input logic [ID_BITS-1:0] b_id,
input logic [ ID_BITS-1:0] b_id,
input logic [INTPRIORITY_BITS-1:0] b_priority,
output logic [ID_BITS-1:0] out_id,
output logic [ ID_BITS-1:0] out_id,
output logic [INTPRIORITY_BITS-1:0] out_priority
);
);
logic a_is_lt_b ;
logic a_is_lt_b;
assign a_is_lt_b = ( a_priority[INTPRIORITY_BITS-1:0] < b_priority[INTPRIORITY_BITS-1:0] ) ;
assign a_is_lt_b = (a_priority[INTPRIORITY_BITS-1:0] < b_priority[INTPRIORITY_BITS-1:0]);
assign out_id[ID_BITS-1:0] = a_is_lt_b ? b_id[ID_BITS-1:0] :
a_id[ID_BITS-1:0] ;
assign out_priority[INTPRIORITY_BITS-1:0] = a_is_lt_b ? b_priority[INTPRIORITY_BITS-1:0] :
assign out_id[ID_BITS-1:0] = a_is_lt_b ? b_id[ID_BITS-1:0] : a_id[ID_BITS-1:0];
assign out_priority[INTPRIORITY_BITS-1:0] = a_is_lt_b ? b_priority[INTPRIORITY_BITS-1:0] :
a_priority[INTPRIORITY_BITS-1:0] ;
endmodule // cmp_and_mux
@ -556,25 +689,33 @@ module el2_configurable_gw (
input logic rawclk,
input logic clken,
input logic rst_l,
input logic extintsrc_req ,
input logic meigwctrl_polarity ,
input logic meigwctrl_type ,
input logic meigwclr ,
input logic extintsrc_req,
input logic meigwctrl_polarity,
input logic meigwctrl_type,
input logic meigwclr,
output logic extintsrc_req_config
);
);
logic gw_int_pending_in, gw_int_pending, extintsrc_req_sync;
rvsyncss_fpga #(1) sync_inst (
.dout (extintsrc_req_sync),
.dout(extintsrc_req_sync),
.din (extintsrc_req),
.*) ;
.*
);
assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ;
rvdff_fpga #(1) int_pend_ff (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (gw_int_pending_in), .dout(gw_int_pending));
rvdff_fpga #(1) int_pend_ff (
.*,
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(gw_int_pending_in),
.dout(gw_int_pending)
);
assign extintsrc_req_config = meigwctrl_type ? ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending) : (extintsrc_req_sync ^ meigwctrl_polarity) ;

362
Flow/design/el2_swerv.sv
View File

@ -21,11 +21,10 @@
//
//********************************************************************************
module el2_swerv
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk,
input logic rst_l,
input logic dbg_rst_l,
@ -76,10 +75,10 @@ import el2_pkg::*;
// DCCM ports
output logic dccm_wren,
output logic dccm_rden,
output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
output logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
output logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
output logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
output logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
@ -90,8 +89,8 @@ import el2_pkg::*;
output logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
output logic iccm_wren,
output logic iccm_rden,
output logic [2:0] iccm_wr_size,
output logic [77:0] iccm_wr_data,
output logic [ 2:0] iccm_wr_size,
output logic [ 77:0] iccm_wr_data,
output logic iccm_buf_correct_ecc,
output logic iccm_correction_state,
@ -99,7 +98,7 @@ import el2_pkg::*;
input logic [77:0] iccm_rd_data_ecc,
// ICache , ITAG ports
output logic [31:1] ic_rw_addr,
output logic [ 31:1] ic_rw_addr,
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
output logic ic_rd_en,
@ -107,7 +106,7 @@ import el2_pkg::*;
output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
input logic [25:0] ictag_debug_rd_data, // Debug icache tag.
output logic [70:0] ic_debug_wr_data, // Debug wr cache.
input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
@ -116,7 +115,7 @@ import el2_pkg::*;
output logic ic_sel_premux_data, // Select premux data
output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
output logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
output logic ic_debug_rd_en, // Icache debug rd
output logic ic_debug_wr_en, // Icache debug wr
output logic ic_debug_tag_array, // Debug tag array
@ -132,46 +131,46 @@ import el2_pkg::*;
output logic lsu_axi_awvalid,
input logic lsu_axi_awready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
output logic [31:0] lsu_axi_awaddr,
output logic [3:0] lsu_axi_awregion,
output logic [7:0] lsu_axi_awlen,
output logic [2:0] lsu_axi_awsize,
output logic [1:0] lsu_axi_awburst,
output logic [ 31:0] lsu_axi_awaddr,
output logic [ 3:0] lsu_axi_awregion,
output logic [ 7:0] lsu_axi_awlen,
output logic [ 2:0] lsu_axi_awsize,
output logic [ 1:0] lsu_axi_awburst,
output logic lsu_axi_awlock,
output logic [3:0] lsu_axi_awcache,
output logic [2:0] lsu_axi_awprot,
output logic [3:0] lsu_axi_awqos,
output logic [ 3:0] lsu_axi_awcache,
output logic [ 2:0] lsu_axi_awprot,
output logic [ 3:0] lsu_axi_awqos,
output logic lsu_axi_wvalid,
input logic lsu_axi_wready,
output logic [63:0] lsu_axi_wdata,
output logic [7:0] lsu_axi_wstrb,
output logic [ 7:0] lsu_axi_wstrb,
output logic lsu_axi_wlast,
input logic lsu_axi_bvalid,
output logic lsu_axi_bready,
input logic [1:0] lsu_axi_bresp,
input logic [ 1:0] lsu_axi_bresp,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
// AXI Read Channels
output logic lsu_axi_arvalid,
input logic lsu_axi_arready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
output logic [31:0] lsu_axi_araddr,
output logic [3:0] lsu_axi_arregion,
output logic [7:0] lsu_axi_arlen,
output logic [2:0] lsu_axi_arsize,
output logic [1:0] lsu_axi_arburst,
output logic [ 31:0] lsu_axi_araddr,
output logic [ 3:0] lsu_axi_arregion,
output logic [ 7:0] lsu_axi_arlen,
output logic [ 2:0] lsu_axi_arsize,
output logic [ 1:0] lsu_axi_arburst,
output logic lsu_axi_arlock,
output logic [3:0] lsu_axi_arcache,
output logic [2:0] lsu_axi_arprot,
output logic [3:0] lsu_axi_arqos,
output logic [ 3:0] lsu_axi_arcache,
output logic [ 2:0] lsu_axi_arprot,
output logic [ 3:0] lsu_axi_arqos,
input logic lsu_axi_rvalid,
output logic lsu_axi_rready,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
input logic [63:0] lsu_axi_rdata,
input logic [1:0] lsu_axi_rresp,
input logic [ 63:0] lsu_axi_rdata,
input logic [ 1:0] lsu_axi_rresp,
input logic lsu_axi_rlast,
//-------------------------- IFU AXI signals--------------------------
@ -179,46 +178,46 @@ import el2_pkg::*;
output logic ifu_axi_awvalid,
input logic ifu_axi_awready,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
output logic [31:0] ifu_axi_awaddr,
output logic [3:0] ifu_axi_awregion,
output logic [7:0] ifu_axi_awlen,
output logic [2:0] ifu_axi_awsize,
output logic [1:0] ifu_axi_awburst,
output logic [ 31:0] ifu_axi_awaddr,
output logic [ 3:0] ifu_axi_awregion,
output logic [ 7:0] ifu_axi_awlen,
output logic [ 2:0] ifu_axi_awsize,
output logic [ 1:0] ifu_axi_awburst,
output logic ifu_axi_awlock,
output logic [3:0] ifu_axi_awcache,
output logic [2:0] ifu_axi_awprot,
output logic [3:0] ifu_axi_awqos,
output logic [ 3:0] ifu_axi_awcache,
output logic [ 2:0] ifu_axi_awprot,
output logic [ 3:0] ifu_axi_awqos,
output logic ifu_axi_wvalid,
input logic ifu_axi_wready,
output logic [63:0] ifu_axi_wdata,
output logic [7:0] ifu_axi_wstrb,
output logic [ 7:0] ifu_axi_wstrb,
output logic ifu_axi_wlast,
input logic ifu_axi_bvalid,
output logic ifu_axi_bready,
input logic [1:0] ifu_axi_bresp,
input logic [ 1:0] ifu_axi_bresp,
input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
// AXI Read Channels
output logic ifu_axi_arvalid,
input logic ifu_axi_arready,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
output logic [31:0] ifu_axi_araddr,
output logic [3:0] ifu_axi_arregion,
output logic [7:0] ifu_axi_arlen,
output logic [2:0] ifu_axi_arsize,
output logic [1:0] ifu_axi_arburst,
output logic [ 31:0] ifu_axi_araddr,
output logic [ 3:0] ifu_axi_arregion,
output logic [ 7:0] ifu_axi_arlen,
output logic [ 2:0] ifu_axi_arsize,
output logic [ 1:0] ifu_axi_arburst,
output logic ifu_axi_arlock,
output logic [3:0] ifu_axi_arcache,
output logic [2:0] ifu_axi_arprot,
output logic [3:0] ifu_axi_arqos,
output logic [ 3:0] ifu_axi_arcache,
output logic [ 2:0] ifu_axi_arprot,
output logic [ 3:0] ifu_axi_arqos,
input logic ifu_axi_rvalid,
output logic ifu_axi_rready,
input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
input logic [63:0] ifu_axi_rdata,
input logic [1:0] ifu_axi_rresp,
input logic [ 63:0] ifu_axi_rdata,
input logic [ 1:0] ifu_axi_rresp,
input logic ifu_axi_rlast,
//-------------------------- SB AXI signals--------------------------
@ -226,46 +225,46 @@ import el2_pkg::*;
output logic sb_axi_awvalid,
input logic sb_axi_awready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
output logic [31:0] sb_axi_awaddr,
output logic [3:0] sb_axi_awregion,
output logic [7:0] sb_axi_awlen,
output logic [2:0] sb_axi_awsize,
output logic [1:0] sb_axi_awburst,
output logic [ 31:0] sb_axi_awaddr,
output logic [ 3:0] sb_axi_awregion,
output logic [ 7:0] sb_axi_awlen,
output logic [ 2:0] sb_axi_awsize,
output logic [ 1:0] sb_axi_awburst,
output logic sb_axi_awlock,
output logic [3:0] sb_axi_awcache,
output logic [2:0] sb_axi_awprot,
output logic [3:0] sb_axi_awqos,
output logic [ 3:0] sb_axi_awcache,
output logic [ 2:0] sb_axi_awprot,
output logic [ 3:0] sb_axi_awqos,
output logic sb_axi_wvalid,
input logic sb_axi_wready,
output logic [63:0] sb_axi_wdata,
output logic [7:0] sb_axi_wstrb,
output logic [ 7:0] sb_axi_wstrb,
output logic sb_axi_wlast,
input logic sb_axi_bvalid,
output logic sb_axi_bready,
input logic [1:0] sb_axi_bresp,
input logic [ 1:0] sb_axi_bresp,
input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
// AXI Read Channels
output logic sb_axi_arvalid,
input logic sb_axi_arready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
output logic [31:0] sb_axi_araddr,
output logic [3:0] sb_axi_arregion,
output logic [7:0] sb_axi_arlen,
output logic [2:0] sb_axi_arsize,
output logic [1:0] sb_axi_arburst,
output logic [ 31:0] sb_axi_araddr,
output logic [ 3:0] sb_axi_arregion,
output logic [ 7:0] sb_axi_arlen,
output logic [ 2:0] sb_axi_arsize,
output logic [ 1:0] sb_axi_arburst,
output logic sb_axi_arlock,
output logic [3:0] sb_axi_arcache,
output logic [2:0] sb_axi_arprot,
output logic [3:0] sb_axi_arqos,
output logic [ 3:0] sb_axi_arcache,
output logic [ 2:0] sb_axi_arprot,
output logic [ 3:0] sb_axi_arqos,
input logic sb_axi_rvalid,
output logic sb_axi_rready,
input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
input logic [63:0] sb_axi_rdata,
input logic [1:0] sb_axi_rresp,
input logic [ 63:0] sb_axi_rdata,
input logic [ 1:0] sb_axi_rresp,
input logic sb_axi_rlast,
//-------------------------- DMA AXI signals--------------------------
@ -273,49 +272,49 @@ import el2_pkg::*;
input logic dma_axi_awvalid,
output logic dma_axi_awready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
input logic [31:0] dma_axi_awaddr,
input logic [2:0] dma_axi_awsize,
input logic [2:0] dma_axi_awprot,
input logic [7:0] dma_axi_awlen,
input logic [1:0] dma_axi_awburst,
input logic [ 31:0] dma_axi_awaddr,
input logic [ 2:0] dma_axi_awsize,
input logic [ 2:0] dma_axi_awprot,
input logic [ 7:0] dma_axi_awlen,
input logic [ 1:0] dma_axi_awburst,
input logic dma_axi_wvalid,
output logic dma_axi_wready,
input logic [63:0] dma_axi_wdata,
input logic [7:0] dma_axi_wstrb,
input logic [ 7:0] dma_axi_wstrb,
input logic dma_axi_wlast,
output logic dma_axi_bvalid,
input logic dma_axi_bready,
output logic [1:0] dma_axi_bresp,
output logic [ 1:0] dma_axi_bresp,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
// AXI Read Channels
input logic dma_axi_arvalid,
output logic dma_axi_arready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
input logic [31:0] dma_axi_araddr,
input logic [2:0] dma_axi_arsize,
input logic [2:0] dma_axi_arprot,
input logic [7:0] dma_axi_arlen,
input logic [1:0] dma_axi_arburst,
input logic [ 31:0] dma_axi_araddr,
input logic [ 2:0] dma_axi_arsize,
input logic [ 2:0] dma_axi_arprot,
input logic [ 7:0] dma_axi_arlen,
input logic [ 1:0] dma_axi_arburst,
output logic dma_axi_rvalid,
input logic dma_axi_rready,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
output logic [63:0] dma_axi_rdata,
output logic [1:0] dma_axi_rresp,
output logic [ 63:0] dma_axi_rdata,
output logic [ 1:0] dma_axi_rresp,
output logic dma_axi_rlast,
//// AHB LITE BUS
output logic [31:0] haddr,
output logic [2:0] hburst,
output logic [ 2:0] hburst,
output logic hmastlock,
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
output logic [ 3:0] hprot,
output logic [ 2:0] hsize,
output logic [ 1:0] htrans,
output logic hwrite,
input logic [63:0] hrdata,
@ -324,11 +323,11 @@ import el2_pkg::*;
// LSU AHB Master
output logic [31:0] lsu_haddr,
output logic [2:0] lsu_hburst,
output logic [ 2:0] lsu_hburst,
output logic lsu_hmastlock,
output logic [3:0] lsu_hprot,
output logic [2:0] lsu_hsize,
output logic [1:0] lsu_htrans,
output logic [ 3:0] lsu_hprot,
output logic [ 2:0] lsu_hsize,
output logic [ 1:0] lsu_htrans,
output logic lsu_hwrite,
output logic [63:0] lsu_hwdata,
@ -338,11 +337,11 @@ import el2_pkg::*;
//System Bus Debug Master
output logic [31:0] sb_haddr,
output logic [2:0] sb_hburst,
output logic [ 2:0] sb_hburst,
output logic sb_hmastlock,
output logic [3:0] sb_hprot,
output logic [2:0] sb_hsize,
output logic [1:0] sb_htrans,
output logic [ 3:0] sb_hprot,
output logic [ 2:0] sb_hsize,
output logic [ 1:0] sb_htrans,
output logic sb_hwrite,
output logic [63:0] sb_hwdata,
@ -353,11 +352,11 @@ import el2_pkg::*;
// DMA Slave
input logic dma_hsel,
input logic [31:0] dma_haddr,
input logic [2:0] dma_hburst,
input logic [ 2:0] dma_hburst,
input logic dma_hmastlock,
input logic [3:0] dma_hprot,
input logic [2:0] dma_hsize,
input logic [1:0] dma_htrans,
input logic [ 3:0] dma_hprot,
input logic [ 2:0] dma_hsize,
input logic [ 1:0] dma_htrans,
input logic dma_hwrite,
input logic [63:0] dma_hwdata,
input logic dma_hreadyin,
@ -372,7 +371,7 @@ import el2_pkg::*;
input logic dma_bus_clk_en,
input logic dmi_reg_en, // read or write
input logic [6:0] dmi_reg_addr, // address of DM register
input logic [ 6:0] dmi_reg_addr, // address of DM register
input logic dmi_reg_wr_en, // write instruction
input logic [31:0] dmi_reg_wdata, // write data
output logic [31:0] dmi_reg_rdata,
@ -516,7 +515,7 @@ import el2_pkg::*;
logic dma_axi_rready_int;
// Icache debug
// Icache debug
logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data
logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid
el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
@ -791,7 +790,7 @@ import el2_pkg::*;
logic [15:0] ifu_i0_cinst;
// fast interrupt
// fast interrupt
logic [31:2] dec_tlu_meihap;
logic dec_extint_stall;
@ -820,33 +819,55 @@ import el2_pkg::*;
assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;
rvoclkhdr free_cg2 ( .clk(clk), .en(1'b1), .l1clk(free_l2clk), .* );
rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );
rvoclkhdr free_cg2 (
.clk(clk),
.en(1'b1),
.l1clk(free_l2clk),
.*
);
rvoclkhdr active_cg2 (
.clk(clk),
.en(active_state),
.l1clk(active_l2clk),
.*
);
// all other clock headers are 1st level
rvoclkhdr free_cg1 ( .clk(free_l2clk), .en(1'b1), .l1clk(free_clk), .* );
rvoclkhdr active_cg1 ( .clk(active_l2clk), .en(1'b1), .l1clk(active_clk), .* );
// all other clock headers are 1st level
rvoclkhdr free_cg1 (
.clk(free_l2clk),
.en(1'b1),
.l1clk(free_clk),
.*
);
rvoclkhdr active_cg1 (
.clk(active_l2clk),
.en(1'b1),
.l1clk(active_clk),
.*
);
assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];
el2_dbg #(.pt(pt)) dbg (
el2_dbg #(
.pt(pt)
) dbg (
.rst_l(core_rst_l),
.clk(free_l2clk),
.clk_override(dec_tlu_misc_clk_override),
// AXI signals
.sb_axi_awready(sb_axi_awready_int),
.sb_axi_wready(sb_axi_wready_int),
.sb_axi_bvalid(sb_axi_bvalid_int),
.sb_axi_bresp(sb_axi_bresp_int[1:0]),
.sb_axi_wready (sb_axi_wready_int),
.sb_axi_bvalid (sb_axi_bvalid_int),
.sb_axi_bresp (sb_axi_bresp_int[1:0]),
.sb_axi_arready(sb_axi_arready_int),
.sb_axi_rvalid(sb_axi_rvalid_int),
.sb_axi_rdata(sb_axi_rdata_int[63:0]),
.sb_axi_rresp(sb_axi_rresp_int[1:0]),
.sb_axi_rvalid (sb_axi_rvalid_int),
.sb_axi_rdata (sb_axi_rdata_int[63:0]),
.sb_axi_rresp (sb_axi_rresp_int[1:0]),
.*
);
@ -854,14 +875,16 @@ import el2_pkg::*;
assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
// fetch
el2_ifu #(.pt(pt)) ifu (
.clk(active_l2clk),
.rst_l(core_rst_l),
.dec_tlu_flush_err_wb (dec_tlu_flush_err_r ),
.dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ),
.dec_tlu_fence_i_wb (dec_tlu_fence_i_r ),
.dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ),
.dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ),
el2_ifu #(
.pt(pt)
) ifu (
.clk (active_l2clk),
.rst_l (core_rst_l),
.dec_tlu_flush_err_wb (dec_tlu_flush_err_r),
.dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r),
.dec_tlu_fence_i_wb (dec_tlu_fence_i_r),
.dec_tlu_flush_leak_one_wb(dec_tlu_flush_leak_one_r),
.dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r),
// AXI signals
.ifu_axi_arready(ifu_axi_arready_int),
@ -874,20 +897,26 @@ import el2_pkg::*;
);
el2_dec #(.pt(pt)) dec (
el2_dec #(
.pt(pt)
) dec (
.clk(active_l2clk),
.dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
.rst_l(core_rst_l),
.*
);
el2_exu #(.pt(pt)) exu (
.clk(active_l2clk),
el2_exu #(
.pt(pt)
) exu (
.clk (active_l2clk),
.rst_l(core_rst_l),
.*
);
el2_lsu #(.pt(pt)) lsu (
el2_lsu #(
.pt(pt)
) lsu (
.clk(active_l2clk),
.rst_l(core_rst_l),
.clk_override(dec_tlu_lsu_clk_override),
@ -912,20 +941,25 @@ import el2_pkg::*;
);
el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst (
el2_pic_ctrl #(
.pt(pt)
) pic_ctrl_inst (
.clk(free_l2clk),
.clk_override(dec_tlu_pic_clk_override),
.io_clk_override(dec_tlu_picio_clk_override),
.picm_mken (picm_mken),
.extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),
.picm_mken(picm_mken),
.extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1], 1'b0}),
.pl(pic_pl[3:0]),
.claimid(pic_claimid[7:0]),
.meicurpl(dec_tlu_meicurpl[3:0]),
.meipt(dec_tlu_meipt[3:0]),
.rst_l(core_rst_l),
.*);
.*
);
el2_dma_ctrl #(.pt(pt)) dma_ctrl (
el2_dma_ctrl #(
.pt(pt)
) dma_ctrl (
.clk(free_l2clk),
.rst_l(core_rst_l),
.clk_override(dec_tlu_misc_clk_override),
@ -949,11 +983,13 @@ import el2_pkg::*;
.*
);
if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
if (pt.BUILD_AHB_LITE == 1) begin : Gen_AXI_To_AHB
// AXI4 -> AHB Gasket for LSU
axi4_to_ahb #(.pt(pt),
.TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
axi4_to_ahb #(
.pt (pt),
.TAG(pt.LSU_BUS_TAG)
) lsu_axi4_to_ahb (
.clk(free_l2clk),
.free_clk(free_clk),
@ -972,9 +1008,9 @@ import el2_pkg::*;
.axi_wvalid(lsu_axi_wvalid),
.axi_wready(lsu_axi_wready_ahb),
.axi_wdata(lsu_axi_wdata[63:0]),
.axi_wstrb(lsu_axi_wstrb[7:0]),
.axi_wlast(lsu_axi_wlast),
.axi_wdata (lsu_axi_wdata[63:0]),
.axi_wstrb (lsu_axi_wstrb[7:0]),
.axi_wlast (lsu_axi_wlast),
.axi_bvalid(lsu_axi_bvalid_ahb),
.axi_bready(lsu_axi_bready),
@ -1008,13 +1044,15 @@ import el2_pkg::*;
.ahb_hrdata(lsu_hrdata[63:0]),
.ahb_hready(lsu_hready),
.ahb_hresp(lsu_hresp),
.ahb_hresp (lsu_hresp),
.*
);
axi4_to_ahb #(.pt(pt),
.TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
axi4_to_ahb #(
.pt (pt),
.TAG(pt.IFU_BUS_TAG)
) ifu_axi4_to_ahb (
.clk(free_l2clk),
.free_clk(free_clk),
.rst_l(core_rst_l),
@ -1034,7 +1072,7 @@ import el2_pkg::*;
.ahb_hrdata(hrdata[63:0]),
.ahb_hready(hready),
.ahb_hresp(hresp),
.ahb_hresp (hresp),
// AXI Write Channels
.axi_awvalid(ifu_axi_awvalid),
@ -1046,9 +1084,9 @@ import el2_pkg::*;
.axi_wvalid(ifu_axi_wvalid),
.axi_wready(ifu_axi_wready_ahb),
.axi_wdata(ifu_axi_wdata[63:0]),
.axi_wstrb(ifu_axi_wstrb[7:0]),
.axi_wlast(ifu_axi_wlast),
.axi_wdata (ifu_axi_wdata[63:0]),
.axi_wstrb (ifu_axi_wstrb[7:0]),
.axi_wlast (ifu_axi_wlast),
.axi_bvalid(ifu_axi_bvalid_ahb),
.axi_bready(1'b1),
@ -1073,8 +1111,10 @@ import el2_pkg::*;
);
// AXI4 -> AHB Gasket for System Bus
axi4_to_ahb #(.pt(pt),
.TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (
axi4_to_ahb #(
.pt (pt),
.TAG(pt.SB_BUS_TAG)
) sb_axi4_to_ahb (
.clk(free_l2clk),
.free_clk(free_clk),
.rst_l(dbg_rst_l),
@ -1092,9 +1132,9 @@ import el2_pkg::*;
.axi_wvalid(sb_axi_wvalid),
.axi_wready(sb_axi_wready_ahb),
.axi_wdata(sb_axi_wdata[63:0]),
.axi_wstrb(sb_axi_wstrb[7:0]),
.axi_wlast(sb_axi_wlast),
.axi_wdata (sb_axi_wdata[63:0]),
.axi_wstrb (sb_axi_wstrb[7:0]),
.axi_wlast (sb_axi_wlast),
.axi_bvalid(sb_axi_bvalid_ahb),
.axi_bready(sb_axi_bready),
@ -1127,14 +1167,16 @@ import el2_pkg::*;
.ahb_hrdata(sb_hrdata[63:0]),
.ahb_hready(sb_hready),
.ahb_hresp(sb_hresp),
.ahb_hresp (sb_hresp),
.*
);
//AHB -> AXI4 Gasket for DMA
ahb_to_axi4 #(.pt(pt),
.TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (
ahb_to_axi4 #(
.pt (pt),
.TAG(pt.DMA_BUS_TAG)
) dma_ahb_to_axi4 (
.clk(free_l2clk),
.rst_l(core_rst_l),
.clk_override(dec_tlu_bus_clk_override),
@ -1152,9 +1194,9 @@ import el2_pkg::*;
.axi_wvalid(dma_axi_wvalid_ahb),
.axi_wready(dma_axi_wready),
.axi_wdata(dma_axi_wdata_ahb[63:0]),
.axi_wstrb(dma_axi_wstrb_ahb[7:0]),
.axi_wlast(dma_axi_wlast_ahb),
.axi_wdata (dma_axi_wdata_ahb[63:0]),
.axi_wstrb (dma_axi_wstrb_ahb[7:0]),
.axi_wlast (dma_axi_wlast_ahb),
.axi_bvalid(dma_axi_bvalid),
.axi_bready(dma_axi_bready_ahb),
@ -1259,7 +1301,7 @@ import el2_pkg::*;
assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;
if (pt.BUILD_AHB_LITE == 1) begin
if (pt.BUILD_AHB_LITE == 1) begin
end // if (pt.BUILD_AHB_LITE == 1)

405
Flow/design/el2_swerv_wrapper.sv
View File

@ -21,11 +21,10 @@
//
//********************************************************************************
module el2_swerv_wrapper
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
import el2_pkg::*;
#(
`include "el2_param.vh"
) (
input logic clk,
input logic rst_l,
input logic dbg_rst_l,
@ -39,7 +38,7 @@ import el2_pkg::*;
output logic [31:0] trace_rv_i_address_ip,
output logic trace_rv_i_valid_ip,
output logic trace_rv_i_exception_ip,
output logic [4:0] trace_rv_i_ecause_ip,
output logic [ 4:0] trace_rv_i_ecause_ip,
output logic trace_rv_i_interrupt_ip,
output logic [31:0] trace_rv_i_tval_ip,
@ -50,46 +49,46 @@ import el2_pkg::*;
output logic lsu_axi_awvalid,
input logic lsu_axi_awready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
output logic [31:0] lsu_axi_awaddr,
output logic [3:0] lsu_axi_awregion,
output logic [7:0] lsu_axi_awlen,
output logic [2:0] lsu_axi_awsize,
output logic [1:0] lsu_axi_awburst,
output logic [ 31:0] lsu_axi_awaddr,
output logic [ 3:0] lsu_axi_awregion,
output logic [ 7:0] lsu_axi_awlen,
output logic [ 2:0] lsu_axi_awsize,
output logic [ 1:0] lsu_axi_awburst,
output logic lsu_axi_awlock,
output logic [3:0] lsu_axi_awcache,
output logic [2:0] lsu_axi_awprot,
output logic [3:0] lsu_axi_awqos,
output logic [ 3:0] lsu_axi_awcache,
output logic [ 2:0] lsu_axi_awprot,
output logic [ 3:0] lsu_axi_awqos,
output logic lsu_axi_wvalid,
input logic lsu_axi_wready,
output logic [63:0] lsu_axi_wdata,
output logic [7:0] lsu_axi_wstrb,
output logic [ 7:0] lsu_axi_wstrb,
output logic lsu_axi_wlast,
input logic lsu_axi_bvalid,
output logic lsu_axi_bready,
input logic [1:0] lsu_axi_bresp,
input logic [ 1:0] lsu_axi_bresp,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
// AXI Read Channels
output logic lsu_axi_arvalid,
input logic lsu_axi_arready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
output logic [31:0] lsu_axi_araddr,
output logic [3:0] lsu_axi_arregion,
output logic [7:0] lsu_axi_arlen,
output logic [2:0] lsu_axi_arsize,
output logic [1:0] lsu_axi_arburst,
output logic [ 31:0] lsu_axi_araddr,
output logic [ 3:0] lsu_axi_arregion,
output logic [ 7:0] lsu_axi_arlen,
output logic [ 2:0] lsu_axi_arsize,
output logic [ 1:0] lsu_axi_arburst,
output logic lsu_axi_arlock,
output logic [3:0] lsu_axi_arcache,
output logic [2:0] lsu_axi_arprot,
output logic [3:0] lsu_axi_arqos,
output logic [ 3:0] lsu_axi_arcache,
output logic [ 2:0] lsu_axi_arprot,
output logic [ 3:0] lsu_axi_arqos,
input logic lsu_axi_rvalid,
output logic lsu_axi_rready,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
input logic [63:0] lsu_axi_rdata,
input logic [1:0] lsu_axi_rresp,
input logic [ 63:0] lsu_axi_rdata,
input logic [ 1:0] lsu_axi_rresp,
input logic lsu_axi_rlast,
//-------------------------- IFU AXI signals--------------------------
@ -97,46 +96,46 @@ import el2_pkg::*;
output logic ifu_axi_awvalid,
input logic ifu_axi_awready,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
output logic [31:0] ifu_axi_awaddr,
output logic [3:0] ifu_axi_awregion,
output logic [7:0] ifu_axi_awlen,
output logic [2:0] ifu_axi_awsize,
output logic [1:0] ifu_axi_awburst,
output logic [ 31:0] ifu_axi_awaddr,
output logic [ 3:0] ifu_axi_awregion,
output logic [ 7:0] ifu_axi_awlen,
output logic [ 2:0] ifu_axi_awsize,
output logic [ 1:0] ifu_axi_awburst,
output logic ifu_axi_awlock,
output logic [3:0] ifu_axi_awcache,
output logic [2:0] ifu_axi_awprot,
output logic [3:0] ifu_axi_awqos,
output logic [ 3:0] ifu_axi_awcache,
output logic [ 2:0] ifu_axi_awprot,
output logic [ 3:0] ifu_axi_awqos,
output logic ifu_axi_wvalid,
input logic ifu_axi_wready,
output logic [63:0] ifu_axi_wdata,
output logic [7:0] ifu_axi_wstrb,
output logic [ 7:0] ifu_axi_wstrb,
output logic ifu_axi_wlast,
input logic ifu_axi_bvalid,
output logic ifu_axi_bready,
input logic [1:0] ifu_axi_bresp,
input logic [ 1:0] ifu_axi_bresp,
input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
// AXI Read Channels
output logic ifu_axi_arvalid,
input logic ifu_axi_arready,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
output logic [31:0] ifu_axi_araddr,
output logic [3:0] ifu_axi_arregion,
output logic [7:0] ifu_axi_arlen,
output logic [2:0] ifu_axi_arsize,
output logic [1:0] ifu_axi_arburst,
output logic [ 31:0] ifu_axi_araddr,
output logic [ 3:0] ifu_axi_arregion,
output logic [ 7:0] ifu_axi_arlen,
output logic [ 2:0] ifu_axi_arsize,
output logic [ 1:0] ifu_axi_arburst,
output logic ifu_axi_arlock,
output logic [3:0] ifu_axi_arcache,
output logic [2:0] ifu_axi_arprot,
output logic [3:0] ifu_axi_arqos,
output logic [ 3:0] ifu_axi_arcache,
output logic [ 2:0] ifu_axi_arprot,
output logic [ 3:0] ifu_axi_arqos,
input logic ifu_axi_rvalid,
output logic ifu_axi_rready,
input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
input logic [63:0] ifu_axi_rdata,
input logic [1:0] ifu_axi_rresp,
input logic [ 63:0] ifu_axi_rdata,
input logic [ 1:0] ifu_axi_rresp,
input logic ifu_axi_rlast,
//-------------------------- SB AXI signals--------------------------
@ -144,46 +143,46 @@ import el2_pkg::*;
output logic sb_axi_awvalid,
input logic sb_axi_awready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
output logic [31:0] sb_axi_awaddr,
output logic [3:0] sb_axi_awregion,
output logic [7:0] sb_axi_awlen,
output logic [2:0] sb_axi_awsize,
output logic [1:0] sb_axi_awburst,
output logic [ 31:0] sb_axi_awaddr,
output logic [ 3:0] sb_axi_awregion,
output logic [ 7:0] sb_axi_awlen,
output logic [ 2:0] sb_axi_awsize,
output logic [ 1:0] sb_axi_awburst,
output logic sb_axi_awlock,
output logic [3:0] sb_axi_awcache,
output logic [2:0] sb_axi_awprot,
output logic [3:0] sb_axi_awqos,
output logic [ 3:0] sb_axi_awcache,
output logic [ 2:0] sb_axi_awprot,
output logic [ 3:0] sb_axi_awqos,
output logic sb_axi_wvalid,
input logic sb_axi_wready,
output logic [63:0] sb_axi_wdata,
output logic [7:0] sb_axi_wstrb,
output logic [ 7:0] sb_axi_wstrb,
output logic sb_axi_wlast,
input logic sb_axi_bvalid,
output logic sb_axi_bready,
input logic [1:0] sb_axi_bresp,
input logic [ 1:0] sb_axi_bresp,
input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
// AXI Read Channels
output logic sb_axi_arvalid,
input logic sb_axi_arready,
output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
output logic [31:0] sb_axi_araddr,
output logic [3:0] sb_axi_arregion,
output logic [7:0] sb_axi_arlen,
output logic [2:0] sb_axi_arsize,
output logic [1:0] sb_axi_arburst,
output logic [ 31:0] sb_axi_araddr,
output logic [ 3:0] sb_axi_arregion,
output logic [ 7:0] sb_axi_arlen,
output logic [ 2:0] sb_axi_arsize,
output logic [ 1:0] sb_axi_arburst,
output logic sb_axi_arlock,
output logic [3:0] sb_axi_arcache,
output logic [2:0] sb_axi_arprot,
output logic [3:0] sb_axi_arqos,
output logic [ 3:0] sb_axi_arcache,
output logic [ 2:0] sb_axi_arprot,
output logic [ 3:0] sb_axi_arqos,
input logic sb_axi_rvalid,
output logic sb_axi_rready,
input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
input logic [63:0] sb_axi_rdata,
input logic [1:0] sb_axi_rresp,
input logic [ 63:0] sb_axi_rdata,
input logic [ 1:0] sb_axi_rresp,
input logic sb_axi_rlast,
//-------------------------- DMA AXI signals--------------------------
@ -191,50 +190,50 @@ import el2_pkg::*;
input logic dma_axi_awvalid,
output logic dma_axi_awready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
input logic [31:0] dma_axi_awaddr,
input logic [2:0] dma_axi_awsize,
input logic [2:0] dma_axi_awprot,
input logic [7:0] dma_axi_awlen,
input logic [1:0] dma_axi_awburst,
input logic [ 31:0] dma_axi_awaddr,
input logic [ 2:0] dma_axi_awsize,
input logic [ 2:0] dma_axi_awprot,
input logic [ 7:0] dma_axi_awlen,
input logic [ 1:0] dma_axi_awburst,
input logic dma_axi_wvalid,
output logic dma_axi_wready,
input logic [63:0] dma_axi_wdata,
input logic [7:0] dma_axi_wstrb,
input logic [ 7:0] dma_axi_wstrb,
input logic dma_axi_wlast,
output logic dma_axi_bvalid,
input logic dma_axi_bready,
output logic [1:0] dma_axi_bresp,
output logic [ 1:0] dma_axi_bresp,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
// AXI Read Channels
input logic dma_axi_arvalid,
output logic dma_axi_arready,
input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
input logic [31:0] dma_axi_araddr,
input logic [2:0] dma_axi_arsize,
input logic [2:0] dma_axi_arprot,
input logic [7:0] dma_axi_arlen,
input logic [1:0] dma_axi_arburst,
input logic [ 31:0] dma_axi_araddr,
input logic [ 2:0] dma_axi_arsize,
input logic [ 2:0] dma_axi_arprot,
input logic [ 7:0] dma_axi_arlen,
input logic [ 1:0] dma_axi_arburst,
output logic dma_axi_rvalid,
input logic dma_axi_rready,
output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
output logic [63:0] dma_axi_rdata,
output logic [1:0] dma_axi_rresp,
output logic [ 63:0] dma_axi_rdata,
output logic [ 1:0] dma_axi_rresp,
output logic dma_axi_rlast,
`endif
`ifdef RV_BUILD_AHB_LITE
//// AHB LITE BUS
output logic [31:0] haddr,
output logic [2:0] hburst,
output logic [ 2:0] hburst,
output logic hmastlock,
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
output logic [ 3:0] hprot,
output logic [ 2:0] hsize,
output logic [ 1:0] htrans,
output logic hwrite,
input logic [63:0] hrdata,
@ -243,11 +242,11 @@ import el2_pkg::*;
// LSU AHB Master
output logic [31:0] lsu_haddr,
output logic [2:0] lsu_hburst,
output logic [ 2:0] lsu_hburst,
output logic lsu_hmastlock,
output logic [3:0] lsu_hprot,
output logic [2:0] lsu_hsize,
output logic [1:0] lsu_htrans,
output logic [ 3:0] lsu_hprot,
output logic [ 2:0] lsu_hsize,
output logic [ 1:0] lsu_htrans,
output logic lsu_hwrite,
output logic [63:0] lsu_hwdata,
@ -256,11 +255,11 @@ import el2_pkg::*;
input logic lsu_hresp,
// Debug Syster Bus AHB
output logic [31:0] sb_haddr,
output logic [2:0] sb_hburst,
output logic [ 2:0] sb_hburst,
output logic sb_hmastlock,
output logic [3:0] sb_hprot,
output logic [2:0] sb_hsize,
output logic [1:0] sb_htrans,
output logic [ 3:0] sb_hprot,
output logic [ 2:0] sb_hsize,
output logic [ 1:0] sb_htrans,
output logic sb_hwrite,
output logic [63:0] sb_hwdata,
@ -271,11 +270,11 @@ import el2_pkg::*;
// DMA Slave
input logic dma_hsel,
input logic [31:0] dma_haddr,
input logic [2:0] dma_hburst,
input logic [ 2:0] dma_hburst,
input logic dma_hmastlock,
input logic [3:0] dma_hprot,
input logic [2:0] dma_hsize,
input logic [1:0] dma_htrans,
input logic [ 3:0] dma_hprot,
input logic [ 2:0] dma_hsize,
input logic [ 1:0] dma_htrans,
input logic dma_hwrite,
input logic [63:0] dma_hwdata,
input logic dma_hreadyin,
@ -353,8 +352,8 @@ import el2_pkg::*;
// Icache & Itag ports
logic [31:1] ic_rw_addr;
logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write
logic ic_rd_en ;
logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en; // Which way to write
logic ic_rd_en;
logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
@ -405,11 +404,11 @@ import el2_pkg::*;
//// AHB LITE BUS
logic [31:0] haddr;
logic [2:0] hburst;
logic [ 2:0] hburst;
logic hmastlock;
logic [3:0] hprot;
logic [2:0] hsize;
logic [1:0] htrans;
logic [ 3:0] hprot;
logic [ 2:0] hsize;
logic [ 1:0] htrans;
logic hwrite;
logic [63:0] hrdata;
@ -418,11 +417,11 @@ import el2_pkg::*;
// LSU AHB Master
logic [31:0] lsu_haddr;
logic [2:0] lsu_hburst;
logic [ 2:0] lsu_hburst;
logic lsu_hmastlock;
logic [3:0] lsu_hprot;
logic [2:0] lsu_hsize;
logic [1:0] lsu_htrans;
logic [ 3:0] lsu_hprot;
logic [ 2:0] lsu_hsize;
logic [ 1:0] lsu_htrans;
logic lsu_hwrite;
logic [63:0] lsu_hwdata;
@ -431,11 +430,11 @@ import el2_pkg::*;
logic lsu_hresp;
// Debug Syster Bus AHB
logic [31:0] sb_haddr;
logic [2:0] sb_hburst;
logic [ 2:0] sb_hburst;
logic sb_hmastlock;
logic [3:0] sb_hprot;
logic [2:0] sb_hsize;
logic [1:0] sb_htrans;
logic [ 3:0] sb_hprot;
logic [ 2:0] sb_hsize;
logic [ 1:0] sb_htrans;
logic sb_hwrite;
logic [63:0] sb_hwdata;
@ -446,11 +445,11 @@ import el2_pkg::*;
// DMA Slave
logic dma_hsel;
logic [31:0] dma_haddr;
logic [2:0] dma_hburst;
logic [ 2:0] dma_hburst;
logic dma_hmastlock;
logic [3:0] dma_hprot;
logic [2:0] dma_hsize;
logic [1:0] dma_htrans;
logic [ 3:0] dma_hprot;
logic [ 2:0] dma_hsize;
logic [ 1:0] dma_htrans;
logic dma_hwrite;
logic [63:0] dma_hwdata;
logic dma_hreadyin;
@ -493,46 +492,46 @@ import el2_pkg::*;
wire lsu_axi_awvalid;
wire lsu_axi_awready;
wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
wire [31:0] lsu_axi_awaddr;
wire [3:0] lsu_axi_awregion;
wire [7:0] lsu_axi_awlen;
wire [2:0] lsu_axi_awsize;
wire [1:0] lsu_axi_awburst;
wire [ 31:0] lsu_axi_awaddr;
wire [ 3:0] lsu_axi_awregion;
wire [ 7:0] lsu_axi_awlen;
wire [ 2:0] lsu_axi_awsize;
wire [ 1:0] lsu_axi_awburst;
wire lsu_axi_awlock;
wire [3:0] lsu_axi_awcache;
wire [2:0] lsu_axi_awprot;
wire [3:0] lsu_axi_awqos;
wire [ 3:0] lsu_axi_awcache;
wire [ 2:0] lsu_axi_awprot;
wire [ 3:0] lsu_axi_awqos;
wire lsu_axi_wvalid;
wire lsu_axi_wready;
wire [63:0] lsu_axi_wdata;
wire [7:0] lsu_axi_wstrb;
wire [ 63:0] lsu_axi_wdata;
wire [ 7:0] lsu_axi_wstrb;
wire lsu_axi_wlast;
wire lsu_axi_bvalid;
wire lsu_axi_bready;
wire [1:0] lsu_axi_bresp;
wire [ 1:0] lsu_axi_bresp;
wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
// AXI Read Channels
wire lsu_axi_arvalid;
wire lsu_axi_arready;
wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
wire [31:0] lsu_axi_araddr;
wire [3:0] lsu_axi_arregion;
wire [7:0] lsu_axi_arlen;
wire [2:0] lsu_axi_arsize;
wire [1:0] lsu_axi_arburst;
wire [ 31:0] lsu_axi_araddr;
wire [ 3:0] lsu_axi_arregion;
wire [ 7:0] lsu_axi_arlen;
wire [ 2:0] lsu_axi_arsize;
wire [ 1:0] lsu_axi_arburst;
wire lsu_axi_arlock;
wire [3:0] lsu_axi_arcache;
wire [2:0] lsu_axi_arprot;
wire [3:0] lsu_axi_arqos;
wire [ 3:0] lsu_axi_arcache;
wire [ 2:0] lsu_axi_arprot;
wire [ 3:0] lsu_axi_arqos;
wire lsu_axi_rvalid;
wire lsu_axi_rready;
wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
wire [63:0] lsu_axi_rdata;
wire [1:0] lsu_axi_rresp;
wire [ 63:0] lsu_axi_rdata;
wire [ 1:0] lsu_axi_rresp;
wire lsu_axi_rlast;
//-------------------------- IFU AXI signals--------------------------
@ -540,93 +539,93 @@ import el2_pkg::*;
wire ifu_axi_awvalid;
wire ifu_axi_awready;
wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
wire [31:0] ifu_axi_awaddr;
wire [3:0] ifu_axi_awregion;
wire [7:0] ifu_axi_awlen;
wire [2:0] ifu_axi_awsize;
wire [1:0] ifu_axi_awburst;
wire [ 31:0] ifu_axi_awaddr;
wire [ 3:0] ifu_axi_awregion;
wire [ 7:0] ifu_axi_awlen;
wire [ 2:0] ifu_axi_awsize;
wire [ 1:0] ifu_axi_awburst;
wire ifu_axi_awlock;
wire [3:0] ifu_axi_awcache;
wire [2:0] ifu_axi_awprot;
wire [3:0] ifu_axi_awqos;
wire [ 3:0] ifu_axi_awcache;
wire [ 2:0] ifu_axi_awprot;
wire [ 3:0] ifu_axi_awqos;
wire ifu_axi_wvalid;
wire ifu_axi_wready;
wire [63:0] ifu_axi_wdata;
wire [7:0] ifu_axi_wstrb;
wire [ 63:0] ifu_axi_wdata;
wire [ 7:0] ifu_axi_wstrb;
wire ifu_axi_wlast;
wire ifu_axi_bvalid;
wire ifu_axi_bready;
wire [1:0] ifu_axi_bresp;
wire [ 1:0] ifu_axi_bresp;
wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
// AXI Read Channels
wire ifu_axi_arvalid;
wire ifu_axi_arready;
wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
wire [31:0] ifu_axi_araddr;
wire [3:0] ifu_axi_arregion;
wire [7:0] ifu_axi_arlen;
wire [2:0] ifu_axi_arsize;
wire [1:0] ifu_axi_arburst;
wire [ 31:0] ifu_axi_araddr;
wire [ 3:0] ifu_axi_arregion;
wire [ 7:0] ifu_axi_arlen;
wire [ 2:0] ifu_axi_arsize;
wire [ 1:0] ifu_axi_arburst;
wire ifu_axi_arlock;
wire [3:0] ifu_axi_arcache;
wire [2:0] ifu_axi_arprot;
wire [3:0] ifu_axi_arqos;
wire [ 3:0] ifu_axi_arcache;
wire [ 2:0] ifu_axi_arprot;
wire [ 3:0] ifu_axi_arqos;
wire ifu_axi_rvalid;
wire ifu_axi_rready;
wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
wire [63:0] ifu_axi_rdata;
wire [1:0] ifu_axi_rresp;
wire [ 63:0] ifu_axi_rdata;
wire [ 1:0] ifu_axi_rresp;
wire ifu_axi_rlast;
//-------------------------- SB AXI signals--------------------------
// AXI Write Channels
wire sb_axi_awvalid;
wire sb_axi_awready;
wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;
wire [31:0] sb_axi_awaddr;
wire [3:0] sb_axi_awregion;
wire [7:0] sb_axi_awlen;
wire [2:0] sb_axi_awsize;
wire [1:0] sb_axi_awburst;
wire [ pt.SB_BUS_TAG-1:0] sb_axi_awid;
wire [ 31:0] sb_axi_awaddr;
wire [ 3:0] sb_axi_awregion;
wire [ 7:0] sb_axi_awlen;
wire [ 2:0] sb_axi_awsize;
wire [ 1:0] sb_axi_awburst;
wire sb_axi_awlock;
wire [3:0] sb_axi_awcache;
wire [2:0] sb_axi_awprot;
wire [3:0] sb_axi_awqos;
wire [ 3:0] sb_axi_awcache;
wire [ 2:0] sb_axi_awprot;
wire [ 3:0] sb_axi_awqos;
wire sb_axi_wvalid;
wire sb_axi_wready;
wire [63:0] sb_axi_wdata;
wire [7:0] sb_axi_wstrb;
wire [ 63:0] sb_axi_wdata;
wire [ 7:0] sb_axi_wstrb;
wire sb_axi_wlast;
wire sb_axi_bvalid;
wire sb_axi_bready;
wire [1:0] sb_axi_bresp;
wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;
wire [ 1:0] sb_axi_bresp;
wire [ pt.SB_BUS_TAG-1:0] sb_axi_bid;
// AXI Read Channels
wire sb_axi_arvalid;
wire sb_axi_arready;
wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;
wire [31:0] sb_axi_araddr;
wire [3:0] sb_axi_arregion;
wire [7:0] sb_axi_arlen;
wire [2:0] sb_axi_arsize;
wire [1:0] sb_axi_arburst;
wire [ pt.SB_BUS_TAG-1:0] sb_axi_arid;
wire [ 31:0] sb_axi_araddr;
wire [ 3:0] sb_axi_arregion;
wire [ 7:0] sb_axi_arlen;
wire [ 2:0] sb_axi_arsize;
wire [ 1:0] sb_axi_arburst;
wire sb_axi_arlock;
wire [3:0] sb_axi_arcache;
wire [2:0] sb_axi_arprot;
wire [3:0] sb_axi_arqos;
wire [ 3:0] sb_axi_arcache;
wire [ 2:0] sb_axi_arprot;
wire [ 3:0] sb_axi_arqos;
wire sb_axi_rvalid;
wire sb_axi_rready;
wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;
wire [63:0] sb_axi_rdata;
wire [1:0] sb_axi_rresp;
wire [ pt.SB_BUS_TAG-1:0] sb_axi_rid;
wire [ 63:0] sb_axi_rdata;
wire [ 1:0] sb_axi_rresp;
wire sb_axi_rlast;
//-------------------------- DMA AXI signals--------------------------
@ -634,39 +633,39 @@ import el2_pkg::*;
wire dma_axi_awvalid;
wire dma_axi_awready;
wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
wire [31:0] dma_axi_awaddr;
wire [2:0] dma_axi_awsize;
wire [2:0] dma_axi_awprot;
wire [7:0] dma_axi_awlen;
wire [1:0] dma_axi_awburst;
wire [ 31:0] dma_axi_awaddr;
wire [ 2:0] dma_axi_awsize;
wire [ 2:0] dma_axi_awprot;
wire [ 7:0] dma_axi_awlen;
wire [ 1:0] dma_axi_awburst;
wire dma_axi_wvalid;
wire dma_axi_wready;
wire [63:0] dma_axi_wdata;
wire [7:0] dma_axi_wstrb;
wire [ 63:0] dma_axi_wdata;
wire [ 7:0] dma_axi_wstrb;
wire dma_axi_wlast;
wire dma_axi_bvalid;
wire dma_axi_bready;
wire [1:0] dma_axi_bresp;
wire [ 1:0] dma_axi_bresp;
wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
// AXI Read Channels
wire dma_axi_arvalid;
wire dma_axi_arready;
wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
wire [31:0] dma_axi_araddr;
wire [2:0] dma_axi_arsize;
wire [2:0] dma_axi_arprot;
wire [7:0] dma_axi_arlen;
wire [1:0] dma_axi_arburst;
wire [ 31:0] dma_axi_araddr;
wire [ 2:0] dma_axi_arsize;
wire [ 2:0] dma_axi_arprot;
wire [ 7:0] dma_axi_arlen;
wire [ 1:0] dma_axi_arburst;
wire dma_axi_rvalid;
wire dma_axi_rready;
wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
wire [63:0] dma_axi_rdata;
wire [1:0] dma_axi_rresp;
wire [ 63:0] dma_axi_rdata;
wire [ 1:0] dma_axi_rresp;
wire dma_axi_rlast;
// AXI
@ -679,20 +678,24 @@ import el2_pkg::*;
`endif // `ifdef RV_BUILD_AHB_LITE
logic dmi_reg_en;
logic [6:0] dmi_reg_addr;
logic [ 6:0] dmi_reg_addr;
logic dmi_reg_wr_en;
logic [31:0] dmi_reg_wdata;
logic [31:0] dmi_reg_rdata;
// Instantiate the el2_swerv core
el2_swerv #(.pt(pt)) swerv (
el2_swerv #(
.pt(pt)
) swerv (
.clk(clk),
.*
);
// Instantiate the mem
el2_mem #(.pt(pt)) mem (
.clk(active_l2clk),
el2_mem #(
.pt(pt)
) mem (
.clk (active_l2clk),
.rst_l(core_rst_l),
.*
);
@ -716,7 +719,7 @@ import el2_pkg::*;
.reg_wr_addr (dmi_reg_addr), // Write address to Processor
.reg_en (dmi_reg_en), // Write interface bit to Processor
.reg_wr_en (dmi_reg_wr_en), // Write enable to Processor
.dmi_hard_reset ()
.dmi_hard_reset()
);
endmodule

204
Flow/design/exu/el2_exu.sv
View File

@ -15,17 +15,16 @@
module el2_exu
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Top level clock
input logic rst_l, // Reset
input logic scan_mode, // Scan control
input logic [1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse
input logic [1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse
input logic [ 1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse
input logic [ 1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse
input logic [31:0] dbg_cmd_wrdata, // Debug data to primary I0 RS1
input el2_alu_pkt_t i0_ap, // DEC alu {valid,predecodes}
@ -104,7 +103,7 @@ import el2_pkg::*;
output logic [31:0] exu_div_result, // Divide result
output logic exu_div_wren // Divide write enable to GPR
);
);
@ -133,20 +132,20 @@ import el2_pkg::*;
el2_predict_pkt_t i0_predict_newp_d;
logic flush_in_d;
logic [31:0] alu_result_x;
logic [ 31:0] alu_result_x;
logic mul_valid_x;
logic [31:0] mul_result_x;
logic [ 31:0] mul_result_x;
el2_predict_pkt_t i0_pp_r;
logic i0_flush_upper_d;
logic [31:1] i0_flush_path_d;
logic [ 31:1] i0_flush_path_d;
el2_predict_pkt_t i0_predict_p_d;
logic i0_pred_correct_upper_d;
logic i0_flush_upper_x;
logic [31:1] i0_flush_path_x;
logic [ 31:1] i0_flush_path_x;
el2_predict_pkt_t i0_predict_p_x;
logic i0_pred_correct_upper_x;
logic i0_branch_x;
@ -157,30 +156,101 @@ import el2_pkg::*;
rvdffpcie #(31) i_flush_path_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_flush_path_d[31:1] ), .dout( i0_flush_path_x[31:1] ) );
rvdffe #(32) i_csr_rs1_x_ff (.*, .clk(clk), .en ( x_data_en_q1 ), .din ( i0_rs1_d[31:0] ), .dout( exu_csr_rs1_x[31:0] ) );
rvdffppe #($bits(el2_predict_pkt_t)) i_predictpacket_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_predict_p_d ), .dout( i0_predict_p_x ) );
rvdffe #(PREDPIPESIZE) i_predpipe_x_ff (.*, .clk(clk), .en ( x_data_en_q2 ), .din ( predpipe_d ), .dout( predpipe_x ) );
rvdffe #(PREDPIPESIZE) i_predpipe_r_ff (.*, .clk(clk), .en ( r_data_en_q2 ), .din ( predpipe_x ), .dout( predpipe_r ) );
rvdffpcie #(31) i_flush_path_x_ff (
.*,
.clk (clk),
.en (x_data_en),
.din (i0_flush_path_d[31:1]),
.dout(i0_flush_path_x[31:1])
);
rvdffe #(32) i_csr_rs1_x_ff (
.*,
.clk (clk),
.en (x_data_en_q1),
.din (i0_rs1_d[31:0]),
.dout(exu_csr_rs1_x[31:0])
);
rvdffppe #($bits(
el2_predict_pkt_t
)) i_predictpacket_x_ff (
.*,
.clk (clk),
.en (x_data_en),
.din (i0_predict_p_d),
.dout(i0_predict_p_x)
);
rvdffe #(PREDPIPESIZE) i_predpipe_x_ff (
.*,
.clk (clk),
.en (x_data_en_q2),
.din (predpipe_d),
.dout(predpipe_x)
);
rvdffe #(PREDPIPESIZE) i_predpipe_r_ff (
.*,
.clk (clk),
.en (r_data_en_q2),
.din (predpipe_x),
.dout(predpipe_r)
);
rvdffe #(4+pt.BHT_GHR_SIZE) i_x_ff (.*, .clk(clk), .en ( x_ctl_en ), .din ({i0_valid_d,i0_taken_d,i0_flush_upper_d,i0_pred_correct_upper_d,ghr_x_ns[pt.BHT_GHR_SIZE-1:0]} ),
.dout({i0_valid_x,i0_taken_x,i0_flush_upper_x,i0_pred_correct_upper_x,ghr_x[pt.BHT_GHR_SIZE-1:0]} ) );
rvdffe #(4 + pt.BHT_GHR_SIZE) i_x_ff (
.*,
.clk(clk),
.en(x_ctl_en),
.din({
i0_valid_d,
i0_taken_d,
i0_flush_upper_d,
i0_pred_correct_upper_d,
ghr_x_ns[pt.BHT_GHR_SIZE-1:0]
}),
.dout({
i0_valid_x,
i0_taken_x,
i0_flush_upper_x,
i0_pred_correct_upper_x,
ghr_x[pt.BHT_GHR_SIZE-1:0]
})
);
rvdffppe #($bits(el2_predict_pkt_t)+1) i_r_ff0 (.*, .clk(clk), .en ( r_ctl_en ), .din ({i0_pred_correct_upper_x, i0_predict_p_x}),
.dout({i0_pred_correct_upper_r, i0_pp_r }) );
rvdffppe #($bits(
el2_predict_pkt_t
) + 1) i_r_ff0 (
.*,
.clk (clk),
.en (r_ctl_en),
.din ({i0_pred_correct_upper_x, i0_predict_p_x}),
.dout({i0_pred_correct_upper_r, i0_pp_r})
);
rvdffpcie #(31) i_flush_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( i0_flush_path_x[31:1] ), .dout( i0_flush_path_upper_r[31:1]) );
rvdffpcie #(31) i_npc_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( pred_correct_npc_x[31:1] ), .dout( pred_correct_npc_r[31:1] ) );
rvdffpcie #(31) i_flush_r_ff (
.*,
.clk (clk),
.en (r_data_en),
.din (i0_flush_path_x[31:1]),
.dout(i0_flush_path_upper_r[31:1])
);
rvdffpcie #(31) i_npc_r_ff (
.*,
.clk (clk),
.en (r_data_en),
.din (pred_correct_npc_x[31:1]),
.dout(pred_correct_npc_r[31:1])
);
rvdffie #(pt.BHT_GHR_SIZE+2,1) i_misc_ff (.*, .clk(clk), .din ({ghr_d_ns[pt.BHT_GHR_SIZE-1:0], mul_p.valid, dec_i0_branch_d}),
.dout({ghr_d[pt.BHT_GHR_SIZE-1:0] , mul_valid_x, i0_branch_x}) );
rvdffie #(pt.BHT_GHR_SIZE + 2, 1) i_misc_ff (
.*,
.clk (clk),
.din ({ghr_d_ns[pt.BHT_GHR_SIZE-1:0], mul_p.valid, dec_i0_branch_d}),
.dout({ghr_d[pt.BHT_GHR_SIZE-1:0], mul_valid_x, i0_branch_x})
);
assign predpipe_d[PREDPIPESIZE-1:0]
= {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};
assign predpipe_d[PREDPIPESIZE-1:0] = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};
assign i0_rs1_bypass_en_d = dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1] | dec_i0_rs1_bypass_en_d[2] | dec_i0_rs1_bypass_en_d[3];
@ -230,44 +300,56 @@ import el2_pkg::*;
el2_exu_alu_ctl #(.pt(pt)) i_alu (.*,
.enable ( x_data_en ), // I
.pp_in ( i0_predict_newp_d ), // I
.valid_in ( dec_i0_alu_decode_d ), // I
.flush_upper_x ( i0_flush_upper_x ), // I
.flush_lower_r ( dec_tlu_flush_lower_r ), // I
.a_in ( i0_rs1_d[31:0] ), // I
.b_in ( i0_rs2_d[31:0] ), // I
.pc_in ( dec_i0_pc_d[31:1] ), // I
.brimm_in ( dec_i0_br_immed_d[12:1] ), // I
.ap ( i0_ap ), // I
.csr_ren_in ( dec_csr_ren_d ), // I
.csr_rddata_in ( dec_csr_rddata_d[31:0] ), // I
.result_ff ( alu_result_x[31:0] ), // O
.flush_upper_out ( i0_flush_upper_d ), // O
.flush_final_out ( exu_flush_final ), // O
.flush_path_out ( i0_flush_path_d[31:1] ), // O
.predict_p_out ( i0_predict_p_d ), // O
.pred_correct_out ( i0_pred_correct_upper_d ), // O
.pc_ff ( exu_i0_pc_x[31:1] )); // O
el2_exu_alu_ctl #(
.pt(pt)
) i_alu (
.*,
.enable (x_data_en), // I
.pp_in (i0_predict_newp_d), // I
.valid_in (dec_i0_alu_decode_d), // I
.flush_upper_x (i0_flush_upper_x), // I
.flush_lower_r (dec_tlu_flush_lower_r), // I
.a_in (i0_rs1_d[31:0]), // I
.b_in (i0_rs2_d[31:0]), // I
.pc_in (dec_i0_pc_d[31:1]), // I
.brimm_in (dec_i0_br_immed_d[12:1]), // I
.ap (i0_ap), // I
.csr_ren_in (dec_csr_ren_d), // I
.csr_rddata_in (dec_csr_rddata_d[31:0]), // I
.result_ff (alu_result_x[31:0]), // O
.flush_upper_out (i0_flush_upper_d), // O
.flush_final_out (exu_flush_final), // O
.flush_path_out (i0_flush_path_d[31:1]), // O
.predict_p_out (i0_predict_p_d), // O
.pred_correct_out(i0_pred_correct_upper_d), // O
.pc_ff (exu_i0_pc_x[31:1])
); // O
el2_exu_mul_ctl #(.pt(pt)) i_mul (.*,
.mul_p ( mul_p & {$bits(el2_mul_pkt_t){mul_p.valid}} ), // I
.rs1_in ( muldiv_rs1_d[31:0] & {32{mul_p.valid}} ), // I
.rs2_in ( i0_rs2_d[31:0] & {32{mul_p.valid}} ), // I
.result_x ( mul_result_x[31:0] )); // O
el2_exu_mul_ctl #(
.pt(pt)
) i_mul (
.*,
.mul_p (mul_p & {$bits(el2_mul_pkt_t) {mul_p.valid}}), // I
.rs1_in (muldiv_rs1_d[31:0] & {32{mul_p.valid}}), // I
.rs2_in (i0_rs2_d[31:0] & {32{mul_p.valid}}), // I
.result_x(mul_result_x[31:0])
); // O
el2_exu_div_ctl #(.pt(pt)) i_div (.*,
.cancel ( dec_div_cancel ), // I
.dp ( div_p ), // I
.dividend ( muldiv_rs1_d[31:0] ), // I
.divisor ( i0_rs2_d[31:0] ), // I
.finish_dly ( exu_div_wren ), // O
.out ( exu_div_result[31:0] )); // O
el2_exu_div_ctl #(
.pt(pt)
) i_div (
.*,
.cancel (dec_div_cancel), // I
.dp (div_p), // I
.dividend (muldiv_rs1_d[31:0]), // I
.divisor (i0_rs2_d[31:0]), // I
.finish_dly(exu_div_wren), // O
.out (exu_div_result[31:0])
); // O
@ -290,7 +372,7 @@ import el2_pkg::*;
assign i0_valid_d = i0_predict_p_d.valid & dec_i0_alu_decode_d & ~dec_tlu_flush_lower_r;
assign i0_taken_d = (i0_predict_p_d.ataken & dec_i0_alu_decode_d);
if(pt.BTB_ENABLE==1) begin
if (pt.BTB_ENABLE == 1) begin
// maintain GHR at D
assign ghr_d_ns[pt.BHT_GHR_SIZE-1:0]
= ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt.BHT_GHR_SIZE-2:0], i0_taken_d}) |
@ -340,7 +422,7 @@ if(pt.BTB_ENABLE==1) begin
exu_mp_btag[pt.BTB_BTAG_SIZE-1:0]} = final_predpipe_mp[PREDPIPESIZE-pt.BHT_GHR_SIZE-1:0];
assign exu_mp_eghr[pt.BHT_GHR_SIZE-1:0] = final_predpipe_mp[PREDPIPESIZE-1:pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+pt.BTB_BTAG_SIZE+1]; // mp ghr for bht write
end // if (pt.BTB_ENABLE==1)
end // if (pt.BTB_ENABLE==1)
else begin
assign ghr_d_ns = '0;
assign ghr_x_ns = '0;
@ -358,7 +440,7 @@ else begin
assign exu_i0_br_middle_r = '0;
assign exu_i0_br_fghr_r = '0;
assign exu_i0_br_way_r = '0;
end // else: !if(pt.BTB_ENABLE==1)
end // else: !if(pt.BTB_ENABLE==1)
assign exu_flush_path_final[31:1] = ( {31{ dec_tlu_flush_lower_r }} & dec_tlu_flush_path_r[31:1] ) |
( {31{~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1] );

218
Flow/design/exu/el2_exu_alu_ctl.sv
View File

@ -15,11 +15,10 @@
module el2_exu_alu_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Top level clock
input logic rst_l, // Reset
input logic scan_mode, // Scan control
@ -45,12 +44,12 @@ import el2_pkg::*;
output logic [31:1] pc_ff, // flopped PC
output logic pred_correct_out, // NPC control
output el2_predict_pkt_t predict_p_out // Predicted branch structure
);
);
logic [31:0] zba_a_in;
logic [31:0] aout;
logic cout,ov,neg;
logic cout, ov, neg;
logic [31:0] lout;
logic [31:0] sout;
logic sel_shift;
@ -62,7 +61,7 @@ import el2_pkg::*;
logic target_mispredict;
logic eq, ne, lt, ge;
logic any_jal;
logic [1:0] newhist;
logic [ 1:0] newhist;
logic sel_pc;
logic [31:0] csr_write_data;
logic [31:0] result;
@ -105,8 +104,7 @@ import el2_pkg::*;
if (pt.BITMANIP_ZBB == 1)
begin
if (pt.BITMANIP_ZBB == 1) begin
assign ap_clz = ap.clz;
assign ap_ctz = ap.ctz;
assign ap_cpop = ap.cpop;
@ -114,9 +112,7 @@ import el2_pkg::*;
assign ap_sext_h = ap.sext_h;
assign ap_min = ap.min;
assign ap_max = ap.max;
end
else
begin
end else begin
assign ap_clz = 1'b0;
assign ap_ctz = 1'b0;
assign ap_cpop = 1'b0;
@ -127,16 +123,13 @@ import el2_pkg::*;
end
if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )
begin
if ((pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1)) begin
assign ap_rol = ap.rol;
assign ap_ror = ap.ror;
assign ap_rev8 = ap.grev & (b_in[4:0] == 5'b11000);
assign ap_orc_b = ap.gorc & (b_in[4:0] == 5'b00111);
assign ap_zbb = ap.zbb;
end
else
begin
end else begin
assign ap_rol = 1'b0;
assign ap_ror = 1'b0;
assign ap_rev8 = 1'b0;
@ -145,15 +138,12 @@ import el2_pkg::*;
end
if (pt.BITMANIP_ZBS == 1)
begin
if (pt.BITMANIP_ZBS == 1) begin
assign ap_bset = ap.bset;
assign ap_bclr = ap.bclr;
assign ap_binv = ap.binv;
assign ap_bext = ap.bext;
end
else
begin
end else begin
assign ap_bset = 1'b0;
assign ap_bclr = 1'b0;
assign ap_binv = 1'b0;
@ -161,12 +151,9 @@ import el2_pkg::*;
end
if (pt.BITMANIP_ZBP == 1)
begin
if (pt.BITMANIP_ZBP == 1) begin
assign ap_packu = ap.packu;
end
else
begin
end else begin
assign ap_packu = 1'b0;
end
@ -175,23 +162,18 @@ import el2_pkg::*;
begin
assign ap_pack = ap.pack;
assign ap_packh = ap.packh;
end
else
begin
end else begin
assign ap_pack = 1'b0;
assign ap_packh = 1'b0;
end
if (pt.BITMANIP_ZBA == 1)
begin
if (pt.BITMANIP_ZBA == 1) begin
assign ap_sh1add = ap.sh1add;
assign ap_sh2add = ap.sh2add;
assign ap_sh3add = ap.sh3add;
assign ap_zba = ap.zba;
end
else
begin
end else begin
assign ap_sh1add = 1'b0;
assign ap_sh2add = 1'b0;
assign ap_sh3add = 1'b0;
@ -206,8 +188,20 @@ import el2_pkg::*;
rvdffpcie #(31) i_pc_ff (.*, .clk(clk), .en(enable), .din(pc_in[31:1]), .dout(pc_ff[31:1])); // any PC is run through here - doesn't have to be alu
rvdffe #(32) i_result_ff (.*, .clk(clk), .en(enable & valid_in), .din(result[31:0]), .dout(result_ff[31:0]));
rvdffpcie #(31) i_pc_ff (
.*,
.clk (clk),
.en (enable),
.din (pc_in[31:1]),
.dout(pc_ff[31:1])
); // any PC is run through here - doesn't have to be alu
rvdffe #(32) i_result_ff (
.*,
.clk (clk),
.en (enable & valid_in),
.din (result[31:0]),
.dout(result_ff[31:0])
);
@ -246,15 +240,13 @@ import el2_pkg::*;
logic [31:0] bm;
assign bm[31:0] = ( ap.sub ) ? ~b_in[31:0] : b_in[31:0];
assign bm[31:0] = (ap.sub) ? ~b_in[31:0] : b_in[31:0];
assign {cout, aout[31:0]} = {1'b0, zba_a_in[31:0]} + {1'b0, bm[31:0]} + {32'b0, ap.sub};
assign ov = (~a_in[31] & ~bm[31] & aout[31]) |
( a_in[31] & bm[31] & ~aout[31] );
assign ov = (~a_in[31] & ~bm[31] & aout[31]) | (a_in[31] & bm[31] & ~aout[31]);
assign lt = (~ap.unsign & (neg ^ ov)) |
( ap.unsign & ~cout);
assign lt = (~ap.unsign & (neg ^ ov)) | (ap.unsign & ~cout);
assign eq = (a_in[31:0] == b_in[31:0]);
assign ne = ~eq;
@ -277,7 +269,7 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : ROL,ROR * * * * * * * * * * * * * * * * * *
// * * * * * * * * * * * * * * * * * * BitManip : ZBEXT * * * * * * * * * * * * * * * * * *
logic [5:0] shift_amount;
logic [ 5:0] shift_amount;
logic [31:0] shift_mask;
logic [62:0] shift_extend;
logic [62:0] shift_long;
@ -291,7 +283,7 @@ import el2_pkg::*;
( { 6{ap_bext}} & {1'b0,b_in[4:0]} );
assign shift_mask[31:0] = ( 32'hffffffff << ({5{ap.sll}} & b_in[4:0]) );
assign shift_mask[31:0] = (32'hffffffff << ({5{ap.sll}} & b_in[4:0]));
assign shift_extend[31:0] = a_in[31:0];
@ -302,7 +294,7 @@ import el2_pkg::*;
( {31{ap_ror}} & a_in[30:0] );
assign shift_long[62:0] = ( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused
assign shift_long[62:0] = (shift_extend[62:0] >> shift_amount[4:0]); // 62-32 unused
assign sout[31:0] = shift_long[31:0] & shift_mask[31:0];
@ -314,15 +306,45 @@ import el2_pkg::*;
logic bitmanip_clz_ctz_sel;
logic [31:0] bitmanip_a_reverse_ff;
logic [31:0] bitmanip_lzd_in;
logic [5:0] bitmanip_dw_lzd_enc;
logic [5:0] bitmanip_clz_ctz_result;
logic [ 5:0] bitmanip_dw_lzd_enc;
logic [ 5:0] bitmanip_clz_ctz_result;
assign bitmanip_clz_ctz_sel = ap_clz | ap_ctz;
assign bitmanip_a_reverse_ff[31:0] = {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7],
a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15],
a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23],
a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]};
assign bitmanip_a_reverse_ff[31:0] = {
a_in[0],
a_in[1],
a_in[2],
a_in[3],
a_in[4],
a_in[5],
a_in[6],
a_in[7],
a_in[8],
a_in[9],
a_in[10],
a_in[11],
a_in[12],
a_in[13],
a_in[14],
a_in[15],
a_in[16],
a_in[17],
a_in[18],
a_in[19],
a_in[20],
a_in[21],
a_in[22],
a_in[23],
a_in[24],
a_in[25],
a_in[26],
a_in[27],
a_in[28],
a_in[29],
a_in[30],
a_in[31]
};
assign bitmanip_lzd_in[31:0] = ( {32{ap_clz}} & a_in[31:0] ) |
( {32{ap_ctz}} & bitmanip_a_reverse_ff[31:0]);
@ -331,19 +353,16 @@ import el2_pkg::*;
integer i;
logic found;
always_comb
begin
always_comb begin
bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0];
bitmanip_dw_lzd_enc[5:0]= 6'b0;
bitmanip_dw_lzd_enc[5:0] = 6'b0;
found = 1'b0;
for (int i=0; i<32 && found==0; i++) begin
for (int i = 0; i < 32 && found == 0; i++) begin
if (bitmanip_lzd_os[31] == 1'b0) begin
bitmanip_dw_lzd_enc[5:0]= bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1;
end
else
found=1'b1;
end else found = 1'b1;
end
end
@ -362,13 +381,11 @@ import el2_pkg::*;
integer bitmanip_cpop_i;
always_comb
begin
always_comb begin
bitmanip_cpop[5:0] = 6'b0;
for (bitmanip_cpop_i=0; bitmanip_cpop_i<32; bitmanip_cpop_i++)
begin
bitmanip_cpop[5:0] = bitmanip_cpop[5:0] + {5'b0,a_in[bitmanip_cpop_i]};
for (bitmanip_cpop_i = 0; bitmanip_cpop_i < 32; bitmanip_cpop_i++) begin
bitmanip_cpop[5:0] = bitmanip_cpop[5:0] + {5'b0, a_in[bitmanip_cpop_i]};
end // FOR bitmanip_cpop_i
end // ALWAYS_COMB
@ -412,8 +429,8 @@ import el2_pkg::*;
logic [31:0] bitmanip_packh_result;
assign bitmanip_pack_result[31:0] = {32{ap_pack}} & {b_in[15:0], a_in[15:0]};
assign bitmanip_packu_result[31:0] = {32{ap_packu}} & {b_in[31:16],a_in[31:16]};
assign bitmanip_packh_result[31:0] = {32{ap_packh}} & {16'b0,b_in[7:0],a_in[7:0]};
assign bitmanip_packu_result[31:0] = {32{ap_packu}} & {b_in[31:16], a_in[31:16]};
assign bitmanip_packh_result[31:0] = {32{ap_packh}} & {16'b0, b_in[7:0], a_in[7:0]};
@ -425,27 +442,27 @@ import el2_pkg::*;
assign bitmanip_rev8_result[31:0] = {32{ap_rev8}} & {a_in[7:0],a_in[15:8],a_in[23:16],a_in[31:24]};
// uint32_t gorc32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 31; ORC.B ORC16
// if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1); 1 0
// if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2); 1 0
// if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4); 1 0
// if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8); 0 0
// if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16); 0 1
// return x;
// }
// uint32_t gorc32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 31; ORC.B ORC16
// if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1); 1 0
// if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2); 1 0
// if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4); 1 0
// if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8); 0 0
// if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16); 0 1
// return x;
// }
// BEFORE 31 , 30 , 29 , 28 , 27 , 26, 25, 24
// shamt[0] b = a31|a30,a31|a30,a29|a28,a29|a28, a27|a26,a27|a26,a25|a24,a25|a24
// shamt[1] c = b31|b29,b30|b28,b31|b29,b30|b28, b27|b25,b26|b24,b27|b25,b26|b24
// shamt[2] d = c31|c27,c30|c26,c29|c25,c28|c24, c31|c27,c30|c26,c29|c25,c28|c24
//
// Expand d31 = c31 | c27;
// = b31 | b29 | b27 | b25;
// = a31|a30 | a29|a28 | a27|a26 | a25|a24
// BEFORE 31 , 30 , 29 , 28 , 27 , 26, 25, 24
// shamt[0] b = a31|a30,a31|a30,a29|a28,a29|a28, a27|a26,a27|a26,a25|a24,a25|a24
// shamt[1] c = b31|b29,b30|b28,b31|b29,b30|b28, b27|b25,b26|b24,b27|b25,b26|b24
// shamt[2] d = c31|c27,c30|c26,c29|c25,c28|c24, c31|c27,c30|c26,c29|c25,c28|c24
//
// Expand d31 = c31 | c27;
// = b31 | b29 | b27 | b25;
// = a31|a30 | a29|a28 | a27|a26 | a25|a24
assign bitmanip_orc_b_result[31:0] = {32{ap_orc_b}} & { {8{| a_in[31:24]}}, {8{| a_in[23:16]}}, {8{| a_in[15:8]}}, {8{| a_in[7:0]}} };
@ -456,7 +473,7 @@ import el2_pkg::*;
logic [31:0] bitmanip_sb_1hot;
logic [31:0] bitmanip_sb_data;
assign bitmanip_sb_1hot[31:0] = ( 32'h00000001 << b_in[4:0] );
assign bitmanip_sb_1hot[31:0] = (32'h00000001 << b_in[4:0]);
assign bitmanip_sb_data[31:0] = ( {32{ap_bset}} & ( a_in[31:0] | bitmanip_sb_1hot[31:0]) ) |
( {32{ap_bclr}} & ( a_in[31:0] & ~bitmanip_sb_1hot[31:0]) ) |
@ -470,7 +487,7 @@ import el2_pkg::*;
assign sel_shift = ap.sll | ap.srl | ap.sra | ap_rol | ap_ror;
assign sel_adder = (ap.add | ap.sub | ap_zba) & ~ap.slt & ~ap_min & ~ap_max;
assign sel_pc = ap.jal | pp_in.pcall | pp_in.pja | pp_in.pret;
assign csr_write_data[31:0]= (ap.csr_imm) ? b_in[31:0] : a_in[31:0];
assign csr_write_data[31:0] = (ap.csr_imm) ? b_in[31:0] : a_in[31:0];
assign slt_one = ap.slt & lt;
@ -498,24 +515,18 @@ import el2_pkg::*;
// *** branch handling ***
assign any_jal = ap.jal |
pp_in.pcall |
pp_in.pja |
pp_in.pret;
assign any_jal = ap.jal | pp_in.pcall | pp_in.pja | pp_in.pret;
assign actual_taken = (ap.beq & eq) |
(ap.bne & ne) |
(ap.blt & lt) |
(ap.bge & ge) |
any_jal;
assign actual_taken = (ap.beq & eq) | (ap.bne & ne) | (ap.blt & lt) | (ap.bge & ge) | any_jal;
// for a conditional br pcout[] will be the opposite of the branch prediction
// for jal or pcall, it will be the link address pc+2 or pc+4
rvbradder ibradder (
.pc ( pc_in[31:1] ),
.offset ( brimm_in[12:1] ),
.dout ( pcout[31:1] ));
.pc (pc_in[31:1]),
.offset(brimm_in[12:1]),
.dout (pcout[31:1])
);
// pred_correct is for the npc logic
@ -527,12 +538,11 @@ import el2_pkg::*;
// for any_jal adder output is the flush path
assign flush_path_out[31:1]= (any_jal) ? aout[31:1] : pcout[31:1];
assign flush_path_out[31:1] = (any_jal) ? aout[31:1] : pcout[31:1];
// pcall and pret are included here
assign cond_mispredict = (ap.predict_t & ~actual_taken) |
(ap.predict_nt & actual_taken);
assign cond_mispredict = (ap.predict_t & ~actual_taken) | (ap.predict_nt & actual_taken);
// target mispredicts on ret's
@ -558,8 +568,8 @@ import el2_pkg::*;
// 10 1 11
// 11 1 11
assign newhist[1] = ( pp_in.hist[1] & pp_in.hist[0]) | (~pp_in.hist[0] & actual_taken);
assign newhist[0] = (~pp_in.hist[1] & ~actual_taken) | ( pp_in.hist[1] & actual_taken);
assign newhist[1] = (pp_in.hist[1] & pp_in.hist[0]) | (~pp_in.hist[0] & actual_taken);
assign newhist[0] = (~pp_in.hist[1] & ~actual_taken) | (pp_in.hist[1] & actual_taken);
always_comb begin
predict_p_out = pp_in;

756
Flow/design/exu/el2_exu_div_ctl.sv
View File

File diff suppressed because it is too large Load Diff

200
Flow/design/exu/el2_exu_mul_ctl.sv
View File

@ -15,11 +15,10 @@
module el2_exu_mul_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Top level clock
input logic rst_l, // Reset
input logic scan_mode, // Scan mode
@ -31,7 +30,7 @@ import el2_pkg::*;
output logic [31:0] result_x // Result
);
);
logic mul_x_enable;
@ -82,32 +81,25 @@ import el2_pkg::*;
logic ap_bfp;
if (pt.BITMANIP_ZBE == 1)
begin
if (pt.BITMANIP_ZBE == 1) begin
assign ap_bcompress = mul_p.bcompress;
assign ap_bdecompress = mul_p.bdecompress;
end
else
begin
end else begin
assign ap_bcompress = 1'b0;
assign ap_bdecompress = 1'b0;
end
if (pt.BITMANIP_ZBC == 1)
begin
if (pt.BITMANIP_ZBC == 1) begin
assign ap_clmul = mul_p.clmul;
assign ap_clmulh = mul_p.clmulh;
assign ap_clmulr = mul_p.clmulr;
end
else
begin
end else begin
assign ap_clmul = 1'b0;
assign ap_clmulh = 1'b0;
assign ap_clmulr = 1'b0;
end
if (pt.BITMANIP_ZBP == 1)
begin
if (pt.BITMANIP_ZBP == 1) begin
assign ap_grev = mul_p.grev;
assign ap_gorc = mul_p.gorc;
assign ap_shfl = mul_p.shfl;
@ -115,9 +107,7 @@ import el2_pkg::*;
assign ap_xperm_n = mul_p.xperm_n;
assign ap_xperm_b = mul_p.xperm_b;
assign ap_xperm_h = mul_p.xperm_h;
end
else
begin
end else begin
assign ap_grev = 1'b0;
assign ap_gorc = 1'b0;
assign ap_shfl = 1'b0;
@ -127,17 +117,14 @@ import el2_pkg::*;
assign ap_xperm_h = 1'b0;
end
if (pt.BITMANIP_ZBR == 1)
begin
if (pt.BITMANIP_ZBR == 1) begin
assign ap_crc32_b = mul_p.crc32_b;
assign ap_crc32_h = mul_p.crc32_h;
assign ap_crc32_w = mul_p.crc32_w;
assign ap_crc32c_b = mul_p.crc32c_b;
assign ap_crc32c_h = mul_p.crc32c_h;
assign ap_crc32c_w = mul_p.crc32c_w;
end
else
begin
end else begin
assign ap_crc32_b = 1'b0;
assign ap_crc32_h = 1'b0;
assign ap_crc32_w = 1'b0;
@ -146,12 +133,9 @@ import el2_pkg::*;
assign ap_crc32c_w = 1'b0;
end
if (pt.BITMANIP_ZBF == 1)
begin
if (pt.BITMANIP_ZBF == 1) begin
assign ap_bfp = mul_p.bfp;
end
else
begin
end else begin
assign ap_bfp = 1'b0;
end
@ -177,8 +161,20 @@ import el2_pkg::*;
logic signed [32:0] rs1_x;
logic signed [32:0] rs2_x;
rvdffe #(34) i_a_x_ff (.*, .clk(clk), .din({mul_p.low,rs1_ext_in[32:0]}), .dout({low_x,rs1_x[32:0]}), .en(mul_x_enable));
rvdffe #(33) i_b_x_ff (.*, .clk(clk), .din( rs2_ext_in[32:0] ), .dout( rs2_x[32:0] ), .en(mul_x_enable));
rvdffe #(34) i_a_x_ff (
.*,
.clk (clk),
.din ({mul_p.low, rs1_ext_in[32:0]}),
.dout({low_x, rs1_x[32:0]}),
.en (mul_x_enable)
);
rvdffe #(33) i_b_x_ff (
.*,
.clk (clk),
.din (rs2_ext_in[32:0]),
.dout(rs2_x[32:0]),
.en (mul_x_enable)
);
assign prod_x[65:0] = rs1_x * rs2_x;
@ -196,18 +192,15 @@ import el2_pkg::*;
integer bcompress_i, bcompress_j;
always_comb
begin
always_comb begin
bcompress_j = 0;
bcompress_test_bit_d = 1'b0;
bcompress_d[31:0] = 32'b0;
for (bcompress_i=0; bcompress_i<32; bcompress_i++)
begin
for (bcompress_i = 0; bcompress_i < 32; bcompress_i++) begin
bcompress_test_bit_d = rs2_in[bcompress_i];
if (bcompress_test_bit_d)
begin
if (bcompress_test_bit_d) begin
bcompress_d[bcompress_j] = rs1_in[bcompress_i];
bcompress_j = bcompress_j + 1;
end // IF bcompress_test_bit
@ -223,18 +216,15 @@ import el2_pkg::*;
integer bdecompress_i, bdecompress_j;
always_comb
begin
always_comb begin
bdecompress_j = 0;
bdecompress_test_bit_d = 1'b0;
bdecompress_d[31:0] = 32'b0;
for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
begin
for (bdecompress_i = 0; bdecompress_i < 32; bdecompress_i++) begin
bdecompress_test_bit_d = rs2_in[bdecompress_i];
if (bdecompress_test_bit_d)
begin
if (bdecompress_test_bit_d) begin
bdecompress_d[bdecompress_i] = rs1_in[bdecompress_j];
bdecompress_j = bdecompress_j + 1;
end // IF bdecompress_test_bit
@ -324,7 +314,7 @@ import el2_pkg::*;
assign grev8_d[31:0] = (rs2_in[3]) ? {grev4_d[23:16],grev4_d[31:24],grev4_d[07:00],grev4_d[15:08]} : grev4_d[31:0];
assign grev_d[31:0] = (rs2_in[4]) ? {grev8_d[15:00],grev8_d[31:16]} : grev8_d[31:0];
assign grev_d[31:0] = (rs2_in[4]) ? {grev8_d[15:00], grev8_d[31:16]} : grev8_d[31:0];
@ -368,7 +358,7 @@ import el2_pkg::*;
assign gorc8_d[31:0] = ( {32{rs2_in[3]}} & {gorc4_d[23:16],gorc4_d[31:24],gorc4_d[07:00],gorc4_d[15:08]} ) | gorc4_d[31:0];
assign gorc_d[31:0] = ( {32{rs2_in[4]}} & {gorc8_d[15:00],gorc8_d[31:16]} ) | gorc8_d[31:0];
assign gorc_d[31:0] = ({32{rs2_in[4]}} & {gorc8_d[15:00], gorc8_d[31:16]}) | gorc8_d[31:0];
@ -463,33 +453,33 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : XPERM * * * * * * * * * * * * * * * * *
//
// These instructions operate on nibbles/bytes/half-words/words.
// rs1 is a vector of data words and rs2 is a vector of indices into rs1.
// The result of the instruction is the vector rs2 with each element replaced by the corresponding data word from rs1,
// or zero then the index in rs2 is out of bounds.
//
// uint_xlen_t xperm(uint_xlen_t rs1, uint_xlen_t rs2, int sz_log2)
// {
// uint_xlen_t r = 0;
// uint_xlen_t sz = 1LL << sz_log2;
// uint_xlen_t mask = (1LL << sz) - 1;
// for (int i = 0; i < XLEN; i += sz)
// { uint_xlen_t pos = ((rs2 >> i) & mask) << sz_log2;
// if (pos < XLEN)
// r |= ((rs1 >> pos) & mask) << i;
// }
// return r;
// }
//
// uint_xlen_t xperm_n (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 2); }
// uint_xlen_t xperm_b (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 3); }
// uint_xlen_t xperm_h (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 4); }
// uint_xlen_t xperm_w (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 5); } Not part of RV32
//
// The xperm.[nbhw] instructions can be implemented with an XLEN/4-lane nibble-wide crossbarswitch.
//
// These instructions operate on nibbles/bytes/half-words/words.
// rs1 is a vector of data words and rs2 is a vector of indices into rs1.
// The result of the instruction is the vector rs2 with each element replaced by the corresponding data word from rs1,
// or zero then the index in rs2 is out of bounds.
//
// uint_xlen_t xperm(uint_xlen_t rs1, uint_xlen_t rs2, int sz_log2)
// {
// uint_xlen_t r = 0;
// uint_xlen_t sz = 1LL << sz_log2;
// uint_xlen_t mask = (1LL << sz) - 1;
// for (int i = 0; i < XLEN; i += sz)
// { uint_xlen_t pos = ((rs2 >> i) & mask) << sz_log2;
// if (pos < XLEN)
// r |= ((rs1 >> pos) & mask) << i;
// }
// return r;
// }
//
// uint_xlen_t xperm_n (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 2); }
// uint_xlen_t xperm_b (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 3); }
// uint_xlen_t xperm_h (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 4); }
// uint_xlen_t xperm_w (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 5); } Not part of RV32
//
// The xperm.[nbhw] instructions can be implemented with an XLEN/4-lane nibble-wide crossbarswitch.
// *** XPERM_B ***
// *** XPERM_B ***
// XLEN = 32
// SZ_LOG2 = 3
@ -524,13 +514,13 @@ import el2_pkg::*;
logic [31:0] xperm_h;
assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & ( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects
assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & ( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf );
assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & ( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf );
assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & ( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf );
assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & ( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf );
assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & ( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf );
assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & ( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf );
assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & ( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf );
assign xperm_n[07:04] = {4{~rs2_in[07]}} & ((rs1_in[31:0] >> {rs2_in[06:04], 2'b0}) & 4'hf);
assign xperm_n[11:08] = {4{~rs2_in[11]}} & ((rs1_in[31:0] >> {rs2_in[10:08], 2'b0}) & 4'hf);
assign xperm_n[15:12] = {4{~rs2_in[15]}} & ((rs1_in[31:0] >> {rs2_in[14:12], 2'b0}) & 4'hf);
assign xperm_n[19:16] = {4{~rs2_in[19]}} & ((rs1_in[31:0] >> {rs2_in[18:16], 2'b0}) & 4'hf);
assign xperm_n[23:20] = {4{~rs2_in[23]}} & ((rs1_in[31:0] >> {rs2_in[22:20], 2'b0}) & 4'hf);
assign xperm_n[27:24] = {4{~rs2_in[27]}} & ((rs1_in[31:0] >> {rs2_in[26:24], 2'b0}) & 4'hf);
assign xperm_n[31:28] = {4{~rs2_in[31]}} & ((rs1_in[31:0] >> {rs2_in[30:28], 2'b0}) & 4'hf);
assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & ( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects
assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & ( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff );
@ -584,34 +574,28 @@ import el2_pkg::*;
assign crc32c_poly_rev[31:0] = 32'h82F63B78; // bit reverse of 32'h1EDC6F41
always_comb
begin
always_comb begin
crc32_bd[31:0] = rs1_in[31:0];
for (crc32_bi=0; crc32_bi<8; crc32_bi++)
begin
for (crc32_bi = 0; crc32_bi < 8; crc32_bi++) begin
crc32_bd[31:0] = (crc32_bd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_bd[0]}});
end // FOR crc32_bi
end // ALWAYS_COMB
always_comb
begin
always_comb begin
crc32_hd[31:0] = rs1_in[31:0];
for (crc32_hi=0; crc32_hi<16; crc32_hi++)
begin
for (crc32_hi = 0; crc32_hi < 16; crc32_hi++) begin
crc32_hd[31:0] = (crc32_hd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_hd[0]}});
end // FOR crc32_hi
end // ALWAYS_COMB
always_comb
begin
always_comb begin
crc32_wd[31:0] = rs1_in[31:0];
for (crc32_wi=0; crc32_wi<32; crc32_wi++)
begin
for (crc32_wi = 0; crc32_wi < 32; crc32_wi++) begin
crc32_wd[31:0] = (crc32_wd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_wd[0]}});
end // FOR crc32_wi
end // ALWAYS_COMB
@ -619,34 +603,28 @@ import el2_pkg::*;
always_comb
begin
always_comb begin
crc32c_bd[31:0] = rs1_in[31:0];
for (crc32c_bi=0; crc32c_bi<8; crc32c_bi++)
begin
for (crc32c_bi = 0; crc32c_bi < 8; crc32c_bi++) begin
crc32c_bd[31:0] = (crc32c_bd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_bd[0]}});
end // FOR crc32c_bi
end // ALWAYS_COMB
always_comb
begin
always_comb begin
crc32c_hd[31:0] = rs1_in[31:0];
for (crc32c_hi=0; crc32c_hi<16; crc32c_hi++)
begin
for (crc32c_hi = 0; crc32c_hi < 16; crc32c_hi++) begin
crc32c_hd[31:0] = (crc32c_hd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_hd[0]}});
end // FOR crc32c_hi
end // ALWAYS_COMB
always_comb
begin
always_comb begin
crc32c_wd[31:0] = rs1_in[31:0];
for (crc32c_wi=0; crc32c_wi<32; crc32c_wi++)
begin
for (crc32c_wi = 0; crc32c_wi < 32; crc32c_wi++) begin
crc32c_wd[31:0] = (crc32c_wd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_wd[0]}});
end // FOR crc32c_wi
end // ALWAYS_COMB
@ -670,8 +648,8 @@ import el2_pkg::*;
// return (data & mask) | (rs1 & ~mask);
logic [4:0] bfp_len;
logic [4:0] bfp_off;
logic [ 4:0] bfp_len;
logic [ 4:0] bfp_off;
logic [31:0] bfp_len_mask_;
logic [31:0] bfp_off_mask_;
logic [15:0] bfp_preshift_data;
@ -686,9 +664,9 @@ import el2_pkg::*;
assign bfp_len_mask_[31:0] = 32'hffff_ffff << bfp_len[4:0];
assign bfp_off_mask_[31:0] = 32'hffff_ffff << bfp_off[4:0];
assign bfp_preshift_data[15:0]= rs2_in[15:0] & ~bfp_len_mask_[15:0];
assign bfp_preshift_data[15:0] = rs2_in[15:0] & ~bfp_len_mask_[15:0];
assign bfp_shift_data[31:0] = {16'b0,bfp_preshift_data[15:0]} << bfp_off[4:0];
assign bfp_shift_data[31:0] = {16'b0, bfp_preshift_data[15:0]} << bfp_off[4:0];
assign bfp_shift_mask[31:0] = (bfp_len_mask_[31:0] << bfp_off[4:0]) | ~bfp_off_mask_[31:0];
assign bfp_result_d[31:0] = bfp_shift_data[31:0] | (rs1_in[31:0] & bfp_shift_mask[31:0]);
@ -723,7 +701,13 @@ import el2_pkg::*;
rvdffe #(33) i_bitmanip_ff (.*, .clk(clk), .din({bitmanip_sel_d,bitmanip_d[31:0]}), .dout({bitmanip_sel_x,bitmanip_x[31:0]}), .en(bit_x_enable));
rvdffe #(33) i_bitmanip_ff (
.*,
.clk (clk),
.din ({bitmanip_sel_d, bitmanip_d[31:0]}),
.dout({bitmanip_sel_x, bitmanip_x[31:0]}),
.en (bit_x_enable)
);

217
Flow/design/ifu/el2_ifu.sv
View File

@ -20,11 +20,10 @@
//********************************************************************************
module el2_ifu
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
@ -33,12 +32,12 @@ import el2_pkg::*;
input logic dec_i0_decode_d, // Valid instruction at D and not blocked
input logic exu_flush_final, // flush, includes upper and lower
input logic dec_tlu_i0_commit_cmt , // committed i0
input logic dec_tlu_flush_err_wb , // flush due to parity error.
input logic dec_tlu_i0_commit_cmt, // committed i0
input logic dec_tlu_flush_err_wb, // flush due to parity error.
input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
input logic [31:1] exu_flush_path_final, // flush fetch address
input logic [31:0] dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
input logic [31:0] dec_tlu_mrac_ff, // Side_effect , cacheable for each region
input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches
@ -50,19 +49,19 @@ import el2_pkg::*;
// AXI Write Channels
output logic ifu_axi_awvalid,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
output logic [31:0] ifu_axi_awaddr,
output logic [3:0] ifu_axi_awregion,
output logic [7:0] ifu_axi_awlen,
output logic [2:0] ifu_axi_awsize,
output logic [1:0] ifu_axi_awburst,
output logic [ 31:0] ifu_axi_awaddr,
output logic [ 3:0] ifu_axi_awregion,
output logic [ 7:0] ifu_axi_awlen,
output logic [ 2:0] ifu_axi_awsize,
output logic [ 1:0] ifu_axi_awburst,
output logic ifu_axi_awlock,
output logic [3:0] ifu_axi_awcache,
output logic [2:0] ifu_axi_awprot,
output logic [3:0] ifu_axi_awqos,
output logic [ 3:0] ifu_axi_awcache,
output logic [ 2:0] ifu_axi_awprot,
output logic [ 3:0] ifu_axi_awqos,
output logic ifu_axi_wvalid,
output logic [63:0] ifu_axi_wdata,
output logic [7:0] ifu_axi_wstrb,
output logic [ 7:0] ifu_axi_wstrb,
output logic ifu_axi_wlast,
output logic ifu_axi_bready,
@ -71,44 +70,44 @@ import el2_pkg::*;
output logic ifu_axi_arvalid,
input logic ifu_axi_arready,
output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
output logic [31:0] ifu_axi_araddr,
output logic [3:0] ifu_axi_arregion,
output logic [7:0] ifu_axi_arlen,
output logic [2:0] ifu_axi_arsize,
output logic [1:0] ifu_axi_arburst,
output logic [ 31:0] ifu_axi_araddr,
output logic [ 3:0] ifu_axi_arregion,
output logic [ 7:0] ifu_axi_arlen,
output logic [ 2:0] ifu_axi_arsize,
output logic [ 1:0] ifu_axi_arburst,
output logic ifu_axi_arlock,
output logic [3:0] ifu_axi_arcache,
output logic [2:0] ifu_axi_arprot,
output logic [3:0] ifu_axi_arqos,
output logic [ 3:0] ifu_axi_arcache,
output logic [ 2:0] ifu_axi_arprot,
output logic [ 3:0] ifu_axi_arqos,
input logic ifu_axi_rvalid,
output logic ifu_axi_rready,
input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
input logic [63:0] ifu_axi_rdata,
input logic [1:0] ifu_axi_rresp,
input logic [ 63:0] ifu_axi_rdata,
input logic [ 1:0] ifu_axi_rresp,
input logic ifu_bus_clk_en,
input logic dma_iccm_req,
input logic [31:0] dma_mem_addr,
input logic [2:0] dma_mem_sz,
input logic [ 2:0] dma_mem_sz,
input logic dma_mem_write,
input logic [63:0] dma_mem_wdata,
input logic [2:0] dma_mem_tag, // DMA Buffer entry number
input logic [ 2:0] dma_mem_tag, // DMA Buffer entry number
input logic dma_iccm_stall_any,
output logic iccm_dma_ecc_error,
output logic iccm_dma_rvalid,
output logic [63:0] iccm_dma_rdata,
output logic [2:0] iccm_dma_rtag, // Tag of the DMA req
output logic [ 2:0] iccm_dma_rtag, // Tag of the DMA req
output logic iccm_ready,
output logic ifu_pmu_instr_aligned,
output logic ifu_pmu_fetch_stall,
output logic ifu_ic_error_start, // has all of the I$ ecc/parity for data/tag
// I$ & ITAG Ports
// I$ & ITAG Ports
output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.
output logic ic_rd_en, // Icache read enable.
@ -116,7 +115,7 @@ import el2_pkg::*;
output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
input logic [25:0] ictag_debug_rd_data, // Debug icache tag.
output logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ifu_ic_debug_rd_data,
@ -126,7 +125,7 @@ import el2_pkg::*;
output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
output logic ic_sel_premux_data, // Select the premux data.
output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
output logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
output logic ic_debug_rd_en, // Icache debug rd
output logic ic_debug_wr_en, // Icache debug wr
output logic ic_debug_tag_array, // Debug tag array
@ -143,15 +142,15 @@ import el2_pkg::*;
output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.
output logic iccm_wren, // ICCM write enable (through the DMA)
output logic iccm_rden, // ICCM read enable.
output logic [77:0] iccm_wr_data, // ICCM write data.
output logic [2:0] iccm_wr_size, // ICCM write location within DW.
output logic [ 77:0] iccm_wr_data, // ICCM write data.
output logic [ 2:0] iccm_wr_size, // ICCM write location within DW.
input logic [63:0] iccm_rd_data, // Data read from ICCM.
input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.
output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error.
// Perf counter sigs
// Perf counter sigs
output logic ifu_pmu_ic_miss, // ic miss
output logic ifu_pmu_ic_hit, // ic hit
output logic ifu_pmu_bus_error, // iside bus error
@ -166,8 +165,8 @@ import el2_pkg::*;
output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst
output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
output logic[31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
output logic[31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode
output logic [31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
output logic [31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode
output logic ifu_i0_pc4, // Instruction 0 is 4 byte. From Aligner to Decode
output logic ifu_miss_state_idle, // There is no outstanding miss. Cache miss state is idle.
@ -179,10 +178,10 @@ import el2_pkg::*;
output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
input el2_predict_pkt_t exu_mp_pkt, // mispredict packet
input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
input logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
input logic [ pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
@ -194,23 +193,23 @@ import el2_pkg::*;
output logic [15:0] ifu_i0_cinst,
/// Icache debug
input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt ,
/// Icache debug
input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt,
output logic ifu_ic_debug_rd_data_valid,
output logic iccm_buf_correct_ecc,
output logic iccm_correction_state,
input logic scan_mode
);
);
localparam TAGWIDTH = 2 ;
localparam IDWIDTH = 2 ;
localparam TAGWIDTH = 2;
localparam IDWIDTH = 2;
logic ifu_fb_consume1, ifu_fb_consume2;
logic [31:1] ifc_fetch_addr_f;
logic [31:1] ifc_fetch_addr_bf;
logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
logic [ 1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
logic [31:1] ifu_fetch_pc; // starting pc of fetch
logic iccm_rd_ecc_single_err, ic_error_start;
@ -238,26 +237,24 @@ import el2_pkg::*;
logic [1:0] ifu_bp_pc4_f; // pc4 indication; right justified
logic [1:0] ifu_bp_valid_f; // branch valid, right justified
logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
logic [1:0][$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
// fetch control
el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*
);
el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*);
// branch predictor
if (pt.BTB_ENABLE==1) begin : bpred
if (pt.BTB_ENABLE == 1) begin : bpred
el2_ifu_bp_ctl #(.pt(pt)) bp (.*);
end
else begin : bpred
end else begin : bpred
assign ifu_bp_hit_taken_f = '0;
// verif wires
logic btb_wr_en_way0, btb_wr_en_way1,dec_tlu_error_wb;
logic btb_wr_en_way0, btb_wr_en_way1, dec_tlu_error_wb;
logic [16+pt.BTB_BTAG_SIZE:0] btb_wr_data;
assign btb_wr_en_way0 = '0;
assign btb_wr_en_way1 = '0;
assign btb_wr_data = '0;
assign dec_tlu_error_wb ='0;
assign dec_tlu_error_wb = '0;
assign ifu_bp_inst_mask_f = 1'b1;
end
@ -284,14 +281,14 @@ import el2_pkg::*;
// aligner
el2_ifu_aln_ctl #(.pt(pt)) aln (
.*
);
el2_ifu_aln_ctl #(.pt(pt)) aln (.*);
// icache
el2_ifu_mem_ctl #(.pt(pt)) mem_ctl
(.*,
el2_ifu_mem_ctl #(
.pt(pt)
) mem_ctl (
.*,
.ic_data_f(ic_data_f[31:0])
);
@ -309,8 +306,8 @@ import el2_pkg::*;
logic exu_mp_call; // branch is a call inst
logic exu_mp_ret; // branch is a ret inst
logic exu_mp_ja; // branch is a jump always
logic [1:0] exu_mp_hist; // new history
logic [11:0] exu_mp_tgt; // target offset
logic [ 1:0] exu_mp_hist; // new history
logic [ 11:0] exu_mp_tgt; // target offset
logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict
@ -322,43 +319,105 @@ import el2_pkg::*;
assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always
assign exu_mp_way = exu_mp_pkt.way; // branch is a jump always
assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history
assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset
assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset
assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address
logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;
`define DEC top.rvtop.swerv.dec
`define EXU top.rvtop.swerv.exu
el2_btb_addr_hash f2hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
el2_btb_addr_hash f2hash (
.pc (ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
);
logic [31:0] mppc_ns, mppc;
logic exu_flush_final_d1;
assign mppc_ns[31:1] = `EXU.i0_flush_upper_x ? `EXU.exu_i0_pc_x : `EXU.dec_i0_pc_d;
assign mppc_ns[0] = 1'b0;
rvdff #(33) junk_ff (.*, .clk(active_clk), .din({mppc_ns[31:0], exu_flush_final}), .dout({mppc[31:0], exu_flush_final_d1}));
rvdff #(33) junk_ff (
.*,
.clk (active_clk),
.din ({mppc_ns[31:0], exu_flush_final}),
.dout({mppc[31:0], exu_flush_final_d1})
);
logic tmp_bnk;
assign tmp_bnk = bpred.bp.btb_sel_f[1];
always @(negedge clk) begin
if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
$display("BTB_CONFIG: %d",pt.BTB_SIZE);
`ifndef BP_NOGSHARE
$display("BHT_CONFIG: %d gshare: 1",pt.BHT_SIZE);
`else
$display("BHT_CONFIG: %d gshare: 0",pt.BHT_SIZE);
`endif
if (`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
$display("BTB_CONFIG: %d", pt.BTB_SIZE);
`ifndef BP_NOGSHARE
$display("BHT_CONFIG: %d gshare: 1", pt.BHT_SIZE);
`else
$display("BHT_CONFIG: %d gshare: 0", pt.BHT_SIZE);
`endif
$display("RS_CONFIG: %d", pt.RET_STACK_SIZE);
end
if(exu_flush_final_d1 & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
$display("%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO], 1'b0, exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_btag[pt.BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[pt.BHT_GHR_SIZE-1:0], exu_mp_valid, bpred.bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
$display(
"%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h",
`DEC.tlu.mcyclel[31:0] + 32'ha,
exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
1'b0,
exu_mp_call,
exu_mp_ret,
exu_mp_ataken,
exu_mp_hist[1:0],
exu_mp_valid,
exu_mp_btag[pt.BTB_BTAG_SIZE-1:0],
{
exu_flush_path_final[31:1], 1'b0
},
exu_mp_eghr[pt.BHT_GHR_SIZE-1:0],
exu_mp_valid,
bpred.bp.bht_wr_addr0,
mppc[31:0],
exu_mp_pkt.way
);
for(int i = 0; i < 8; i++) begin
if(ifu_bp_valid_f[i] & ifc_fetch_req_f)
$display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],bpred.bp.btb_sel_f[1], bpred.bp.btb_rd_call_f, bpred.bp.btb_rd_ret_f, ifu_bp_hist1_f[tmp_bnk], ifu_bp_hist0_f[tmp_bnk], bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f[31:1], 1'b0}, bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0], bpred.bp.bht_rd_addr_f, ifu_bp_way_f[tmp_bnk]);
for (int i = 0; i < 8; i++) begin
if (ifu_bp_valid_f[i] & ifc_fetch_req_f)
$display(
"%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h",
`DEC.tlu.mcyclel[31:0] + 32'ha,
btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
bpred.bp.btb_sel_f[1],
bpred.bp.btb_rd_call_f,
bpred.bp.btb_rd_ret_f,
ifu_bp_hist1_f[tmp_bnk],
ifu_bp_hist0_f[tmp_bnk],
bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0],
{
ifu_bp_btb_target_f[31:1], 1'b0
},
bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0],
bpred.bp.bht_rd_addr_f,
ifu_bp_way_f[tmp_bnk]
);
end
if(dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))
$display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],{dec_tlu_br0_r_pkt.middle}, dec_tlu_br0_r_pkt.hist, dec_tlu_br0_r_pkt.way);
if (dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))
$display(
"%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h",
`DEC.tlu.mcyclel[31:0] + 32'ha,
bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],
{
dec_tlu_br0_r_pkt.middle
},
dec_tlu_br0_r_pkt.hist,
dec_tlu_br0_r_pkt.way
);
if(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)
$display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],1'b0, dec_tlu_br0_r_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_r_pkt.way);
if (dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)
$display(
"%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h",
`DEC.tlu.mcyclel[31:0] + 32'ha,
exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
1'b0,
dec_tlu_br0_r_pkt.br_start_error,
{
exu_flush_path_final[31:1], 1'b0
},
dec_tlu_br0_r_pkt.way
);
end // always @ (negedge clk)
function [1:0] encode4_2;
input [3:0] in;

443
Flow/design/ifu/el2_ifu_aln_ctl.sv
View File

@ -19,11 +19,10 @@
// Function: Instruction aligner
//********************************************************************************
module el2_ifu_aln_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic scan_mode, // Flop scan mode control
input logic rst_l, // reset, active low
@ -43,7 +42,7 @@ import el2_pkg::*;
input logic [31:0] ifu_fetch_data_f, // fetch data in memory format - not right justified
input logic [1:0] ifu_fetch_val, // valids on a 2B boundary, right justified
input logic [ 1:0] ifu_fetch_val, // valids on a 2B boundary, right justified
input logic [31:1] ifu_fetch_pc, // starting pc of fetch
@ -65,7 +64,9 @@ import el2_pkg::*;
input logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch GHR
input logic [31:1] ifu_bp_btb_target_f, // predicted RET target
input logic [11:0] ifu_bp_poffset_f, // predicted target offset
input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)
input logic [1:0][$clog2(
pt.BTB_SIZE
)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)
input logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 1, right justified
input logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
@ -77,15 +78,15 @@ import el2_pkg::*;
output el2_br_pkt_t i0_brp, // Branch packet for I0.
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
output logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
output logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
output logic ifu_pmu_instr_aligned, // number of inst aligned this cycle
output logic [15:0] ifu_i0_cinst // 16b compress inst for i0
);
);
@ -108,54 +109,54 @@ import el2_pkg::*;
logic f2_valid, sf1_valid, sf0_valid;
logic [31:0] ifirst;
logic [1:0] alignval;
logic [ 1:0] alignval;
logic [31:1] firstpc, secondpc;
logic [11:0] f1poffset;
logic [11:0] f0poffset;
logic [ 11:0] f1poffset;
logic [ 11:0] f0poffset;
logic [pt.BHT_GHR_SIZE-1:0] f1fghr;
logic [pt.BHT_GHR_SIZE-1:0] f0fghr;
logic [1:0] f1hist1;
logic [1:0] f0hist1;
logic [1:0] f1hist0;
logic [1:0] f0hist0;
logic [ 1:0] f1hist1;
logic [ 1:0] f0hist1;
logic [ 1:0] f1hist0;
logic [ 1:0] f0hist0;
logic [1:0][$clog2(pt.BTB_SIZE)-1:0] f0index, f1index, alignindex;
logic [1:0] f1ictype;
logic [1:0] f0ictype;
logic [ 1:0] f1ictype;
logic [ 1:0] f0ictype;
logic [1:0] f1pc4;
logic [1:0] f0pc4;
logic [ 1:0] f1pc4;
logic [ 1:0] f0pc4;
logic [1:0] f1ret;
logic [1:0] f0ret;
logic [1:0] f1way;
logic [1:0] f0way;
logic [ 1:0] f1ret;
logic [ 1:0] f0ret;
logic [ 1:0] f1way;
logic [ 1:0] f0way;
logic [1:0] f1brend;
logic [1:0] f0brend;
logic [ 1:0] f1brend;
logic [ 1:0] f0brend;
logic [1:0] alignbrend;
logic [1:0] alignpc4;
logic [ 1:0] alignbrend;
logic [ 1:0] alignpc4;
logic [1:0] alignret;
logic [1:0] alignway;
logic [1:0] alignhist1;
logic [1:0] alignhist0;
logic [1:1] alignfromf1;
logic [ 1:0] alignret;
logic [ 1:0] alignway;
logic [ 1:0] alignhist1;
logic [ 1:0] alignhist0;
logic [ 1:1] alignfromf1;
logic i0_ends_f1;
logic i0_br_start_error;
logic [31:1] f1prett;
logic [31:1] f0prett;
logic [1:0] f1dbecc;
logic [1:0] f0dbecc;
logic [1:0] f1icaf;
logic [1:0] f0icaf;
logic [ 1:0] f1dbecc;
logic [ 1:0] f0dbecc;
logic [ 1:0] f1icaf;
logic [ 1:0] f0icaf;
logic [1:0] aligndbecc;
logic [1:0] alignicaf;
logic [ 1:0] aligndbecc;
logic [ 1:0] alignicaf;
logic i0_brp_pc4;
logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] firstpc_hash, secondpc_hash;
@ -165,7 +166,7 @@ import el2_pkg::*;
logic [1:0] wrptr, wrptr_in;
logic [1:0] rdptr, rdptr_in;
logic [2:0] qwen;
logic [31:0] q2,q1,q0;
logic [31:0] q2, q1, q0;
logic q2off_in, q2off;
logic q1off_in, q1off;
logic q0off_in, q0off;
@ -174,26 +175,26 @@ import el2_pkg::*;
logic [31:0] q0eff;
logic [31:0] q0final;
logic q0ptr;
logic [1:0] q0sel;
logic [ 1:0] q0sel;
logic [31:0] q1eff;
logic [15:0] q1final;
logic q1ptr;
logic [1:0] q1sel;
logic [ 1:0] q1sel;
logic [2:0] qren;
logic [ 2:0] qren;
logic consume_fb1, consume_fb0;
logic [1:0] icaf_eff;
localparam BRDATA_SIZE = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
localparam BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
localparam BRDATA_SIZE = pt.BTB_ENABLE ? 16 + ($clog2(pt.BTB_SIZE) * 2 * pt.BTB_FULLYA) : 4;
localparam BRDATA_WIDTH = pt.BTB_ENABLE ? 8 + ($clog2(pt.BTB_SIZE) * pt.BTB_FULLYA) : 2;
logic [BRDATA_SIZE-1:0] brdata_in, brdata2, brdata1, brdata0;
logic [BRDATA_SIZE-1:0] brdata1eff, brdata0eff;
logic [BRDATA_SIZE-1:0] brdata1final, brdata0final;
localparam MHI = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
localparam MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
localparam MHI = 1 + (pt.BTB_ENABLE * (43 + pt.BHT_GHR_SIZE));
localparam MSIZE = 2 + (pt.BTB_ENABLE * (43 + pt.BHT_GHR_SIZE));
logic [MHI:0] misc_data_in, misc2, misc1, misc0;
logic [MHI:0] misc1eff, misc0eff;
@ -204,57 +205,143 @@ import el2_pkg::*;
assign error_stall_in = (error_stall | ifu_async_error_start) & ~exu_flush_final;
rvdff #(.WIDTH(7)) bundle1ff (.*,
.clk(active_clk),
.din ({wrptr_in[1:0],rdptr_in[1:0],q2off_in,q1off_in,q0off_in}),
rvdff #(
.WIDTH(7)
) bundle1ff (
.*,
.clk (active_clk),
.din ({wrptr_in[1:0], rdptr_in[1:0], q2off_in, q1off_in, q0off_in}),
.dout({wrptr[1:0], rdptr[1:0], q2off, q1off, q0off})
);
rvdffie #(.WIDTH(7),.OVERRIDE(1)) bundle2ff (.*,
.din ({error_stall_in,f2val_in[1:0],f1val_in[1:0],f0val_in[1:0]}),
.dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0] })
rvdffie #(
.WIDTH(7),
.OVERRIDE(1)
) bundle2ff (
.*,
.din ({error_stall_in, f2val_in[1:0], f1val_in[1:0], f0val_in[1:0]}),
.dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0]})
);
if(pt.BTB_ENABLE==1) begin
rvdffe #(BRDATA_SIZE) brdata2ff (.*, .clk(clk), .en(qwen[2]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata2[BRDATA_SIZE-1:0]));
rvdffe #(BRDATA_SIZE) brdata1ff (.*, .clk(clk), .en(qwen[1]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata1[BRDATA_SIZE-1:0]));
rvdffe #(BRDATA_SIZE) brdata0ff (.*, .clk(clk), .en(qwen[0]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata0[BRDATA_SIZE-1:0]));
rvdffe #(MSIZE) misc2ff (.*, .clk(clk), .en(qwen[2]), .din(misc_data_in[MHI:0]), .dout(misc2[MHI:0]));
rvdffe #(MSIZE) misc1ff (.*, .clk(clk), .en(qwen[1]), .din(misc_data_in[MHI:0]), .dout(misc1[MHI:0]));
rvdffe #(MSIZE) misc0ff (.*, .clk(clk), .en(qwen[0]), .din(misc_data_in[MHI:0]), .dout(misc0[MHI:0]));
end
else begin
if (pt.BTB_ENABLE == 1) begin
rvdffe #(BRDATA_SIZE) brdata2ff (
.*,
.clk (clk),
.en (qwen[2]),
.din (brdata_in[BRDATA_SIZE-1:0]),
.dout(brdata2[BRDATA_SIZE-1:0])
);
rvdffe #(BRDATA_SIZE) brdata1ff (
.*,
.clk (clk),
.en (qwen[1]),
.din (brdata_in[BRDATA_SIZE-1:0]),
.dout(brdata1[BRDATA_SIZE-1:0])
);
rvdffe #(BRDATA_SIZE) brdata0ff (
.*,
.clk (clk),
.en (qwen[0]),
.din (brdata_in[BRDATA_SIZE-1:0]),
.dout(brdata0[BRDATA_SIZE-1:0])
);
rvdffe #(MSIZE) misc2ff (
.*,
.clk (clk),
.en (qwen[2]),
.din (misc_data_in[MHI:0]),
.dout(misc2[MHI:0])
);
rvdffe #(MSIZE) misc1ff (
.*,
.clk (clk),
.en (qwen[1]),
.din (misc_data_in[MHI:0]),
.dout(misc1[MHI:0])
);
rvdffe #(MSIZE) misc0ff (
.*,
.clk (clk),
.en (qwen[0]),
.din (misc_data_in[MHI:0]),
.dout(misc0[MHI:0])
);
end else begin
rvdffie #((MSIZE*3)+(BRDATA_SIZE*3)) miscff (.*,
.din({qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]},
rvdffie #((MSIZE * 3) + (BRDATA_SIZE * 3)) miscff (
.*,
.din({
qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]},
qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE-1:0]},
qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]}}),
.dout({misc2[MHI:0], brdata2[BRDATA_SIZE-1:0],
misc1[MHI:0], brdata1[BRDATA_SIZE-1:0],
misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]})
qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]}
}),
.dout({
misc2[MHI:0],
brdata2[BRDATA_SIZE-1:0],
misc1[MHI:0],
brdata1[BRDATA_SIZE-1:0],
misc0[MHI:0],
brdata0[BRDATA_SIZE-1:0]
})
);
end
end
logic [31:1] q2pc, q1pc, q0pc;
rvdffe #(31) q2pcff (.*, .clk(clk), .en(qwen[2]), .din(ifu_fetch_pc[31:1]), .dout(q2pc[31:1]));
rvdffe #(31) q1pcff (.*, .clk(clk), .en(qwen[1]), .din(ifu_fetch_pc[31:1]), .dout(q1pc[31:1]));
rvdffe #(31) q0pcff (.*, .clk(clk), .en(qwen[0]), .din(ifu_fetch_pc[31:1]), .dout(q0pc[31:1]));
rvdffe #(31) q2pcff (
.*,
.clk (clk),
.en (qwen[2]),
.din (ifu_fetch_pc[31:1]),
.dout(q2pc[31:1])
);
rvdffe #(31) q1pcff (
.*,
.clk (clk),
.en (qwen[1]),
.din (ifu_fetch_pc[31:1]),
.dout(q1pc[31:1])
);
rvdffe #(31) q0pcff (
.*,
.clk (clk),
.en (qwen[0]),
.din (ifu_fetch_pc[31:1]),
.dout(q0pc[31:1])
);
rvdffe #(32) q2ff (.*, .clk(clk), .en(qwen[2]), .din(ifu_fetch_data_f[31:0]), .dout(q2[31:0]));
rvdffe #(32) q1ff (.*, .clk(clk), .en(qwen[1]), .din(ifu_fetch_data_f[31:0]), .dout(q1[31:0]));
rvdffe #(32) q0ff (.*, .clk(clk), .en(qwen[0]), .din(ifu_fetch_data_f[31:0]), .dout(q0[31:0]));
rvdffe #(32) q2ff (
.*,
.clk (clk),
.en (qwen[2]),
.din (ifu_fetch_data_f[31:0]),
.dout(q2[31:0])
);
rvdffe #(32) q1ff (
.*,
.clk (clk),
.en (qwen[1]),
.din (ifu_fetch_data_f[31:0]),
.dout(q1[31:0])
);
rvdffe #(32) q0ff (
.*,
.clk (clk),
.en (qwen[0]),
.din (ifu_fetch_data_f[31:0]),
.dout(q0[31:0])
);
// new queue control logic
assign qren[2:0] = { rdptr[1:0] == 2'b10,
rdptr[1:0] == 2'b01,
rdptr[1:0] == 2'b00 };
assign qren[2:0] = {rdptr[1:0] == 2'b10, rdptr[1:0] == 2'b01, rdptr[1:0] == 2'b00};
assign qwen[2:0] = { (wrptr[1:0] == 2'b10) & ifvalid,
assign qwen[2:0] = {
(wrptr[1:0] == 2'b10) & ifvalid,
(wrptr[1:0] == 2'b01) & ifvalid,
(wrptr[1:0] == 2'b00) & ifvalid };
(wrptr[1:0] == 2'b00) & ifvalid
};
assign rdptr_in[1:0] = ({2{ qren[0] & ifu_fb_consume1 & ~exu_flush_final}} & 2'b01 ) |
@ -294,16 +381,16 @@ end
( (rdptr[1:0]==2'b01) & q2off ) |
( (rdptr[1:0]==2'b10) & q0off );
assign q0sel[1:0] = {q0ptr,~q0ptr};
assign q0sel[1:0] = {q0ptr, ~q0ptr};
assign q1sel[1:0] = {q1ptr,~q1ptr};
assign q1sel[1:0] = {q1ptr, ~q1ptr};
// end new queue control logic
// misc data that is associated with each fetch buffer
if(pt.BTB_ENABLE==1)
if (pt.BTB_ENABLE == 1)
assign misc_data_in[MHI:0] = {
ic_access_fault_type_f[1:0],
@ -311,17 +398,14 @@ end
ifu_bp_poffset_f[11:0],
ifu_bp_fghr_f[pt.BHT_GHR_SIZE-1:0]
};
else
assign misc_data_in[MHI:0] = {
ic_access_fault_type_f[1:0]
};
else assign misc_data_in[MHI:0] = {ic_access_fault_type_f[1:0]};
assign {misc1eff[MHI:0],misc0eff[MHI:0]} = (({MSIZE*2{qren[0]}} & {misc1[MHI:0],misc0[MHI:0]}) |
({MSIZE*2{qren[1]}} & {misc2[MHI:0],misc1[MHI:0]}) |
({MSIZE*2{qren[2]}} & {misc0[MHI:0],misc2[MHI:0]}));
if(pt.BTB_ENABLE==1) begin
if (pt.BTB_ENABLE == 1) begin
assign {
f1ictype[1:0],
f1prett[31:1],
@ -336,10 +420,26 @@ end
f0fghr[pt.BHT_GHR_SIZE-1:0]
} = misc0eff[MHI:0];
if(pt.BTB_FULLYA) begin
if (pt.BTB_FULLYA) begin
assign brdata_in[BRDATA_SIZE-1:0] = {
ifu_bp_fa_index_f[1], iccm_rd_ecc_double_err[1],ic_access_fault_f[1],ifu_bp_hist1_f[1],ifu_bp_hist0_f[1],ifu_bp_pc4_f[1],ifu_bp_way_f[1],ifu_bp_valid_f[1],ifu_bp_ret_f[1],
ifu_bp_fa_index_f[0], iccm_rd_ecc_double_err[0],ic_access_fault_f[0],ifu_bp_hist1_f[0],ifu_bp_hist0_f[0],ifu_bp_pc4_f[0],ifu_bp_way_f[0],ifu_bp_valid_f[0],ifu_bp_ret_f[0]
ifu_bp_fa_index_f[1],
iccm_rd_ecc_double_err[1],
ic_access_fault_f[1],
ifu_bp_hist1_f[1],
ifu_bp_hist0_f[1],
ifu_bp_pc4_f[1],
ifu_bp_way_f[1],
ifu_bp_valid_f[1],
ifu_bp_ret_f[1],
ifu_bp_fa_index_f[0],
iccm_rd_ecc_double_err[0],
ic_access_fault_f[0],
ifu_bp_hist1_f[0],
ifu_bp_hist0_f[0],
ifu_bp_pc4_f[0],
ifu_bp_way_f[0],
ifu_bp_valid_f[0],
ifu_bp_ret_f[0]
};
assign {f0index[1],f0dbecc[1],f0icaf[1],f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],
f0index[0],f0dbecc[0],f0icaf[0],f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]} = brdata0final[BRDATA_SIZE-1:0];
@ -347,11 +447,24 @@ end
assign {f1index[1],f1dbecc[1],f1icaf[1],f1hist1[1],f1hist0[1],f1pc4[1],f1way[1],f1brend[1],f1ret[1],
f1index[0],f1dbecc[0],f1icaf[0],f1hist1[0],f1hist0[0],f1pc4[0],f1way[0],f1brend[0],f1ret[0]} = brdata1final[BRDATA_SIZE-1:0];
end
else begin
end else begin
assign brdata_in[BRDATA_SIZE-1:0] = {
iccm_rd_ecc_double_err[1],ic_access_fault_f[1],ifu_bp_hist1_f[1],ifu_bp_hist0_f[1],ifu_bp_pc4_f[1],ifu_bp_way_f[1],ifu_bp_valid_f[1],ifu_bp_ret_f[1],
iccm_rd_ecc_double_err[0],ic_access_fault_f[0],ifu_bp_hist1_f[0],ifu_bp_hist0_f[0],ifu_bp_pc4_f[0],ifu_bp_way_f[0],ifu_bp_valid_f[0],ifu_bp_ret_f[0]
iccm_rd_ecc_double_err[1],
ic_access_fault_f[1],
ifu_bp_hist1_f[1],
ifu_bp_hist0_f[1],
ifu_bp_pc4_f[1],
ifu_bp_way_f[1],
ifu_bp_valid_f[1],
ifu_bp_ret_f[1],
iccm_rd_ecc_double_err[0],
ic_access_fault_f[0],
ifu_bp_hist1_f[0],
ifu_bp_hist0_f[0],
ifu_bp_pc4_f[0],
ifu_bp_way_f[0],
ifu_bp_valid_f[0],
ifu_bp_ret_f[0]
};
assign {f0dbecc[1],f0icaf[1],f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],
f0dbecc[0],f0icaf[0],f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]} = brdata0final[BRDATA_SIZE-1:0];
@ -376,23 +489,19 @@ end
end // if (pt.BTB_ENABLE==1)
else begin
assign {
f1ictype[1:0]
} = misc1eff[MHI:0];
assign {f1ictype[1:0]} = misc1eff[MHI:0];
assign {
f0ictype[1:0]
} = misc0eff[MHI:0];
assign {f0ictype[1:0]} = misc0eff[MHI:0];
assign brdata_in[BRDATA_SIZE-1:0] = {
iccm_rd_ecc_double_err[1],ic_access_fault_f[1],
iccm_rd_ecc_double_err[0],ic_access_fault_f[0]
iccm_rd_ecc_double_err[1],
ic_access_fault_f[1],
iccm_rd_ecc_double_err[0],
ic_access_fault_f[0]
};
assign {f0dbecc[1],f0icaf[1],
f0dbecc[0],f0icaf[0]} = brdata0final[BRDATA_SIZE-1:0];
assign {f0dbecc[1], f0icaf[1], f0dbecc[0], f0icaf[0]} = brdata0final[BRDATA_SIZE-1:0];
assign {f1dbecc[1],f1icaf[1],
f1dbecc[0],f1icaf[0]} = brdata1final[BRDATA_SIZE-1:0];
assign {f1dbecc[1], f1icaf[1], f1dbecc[0], f1icaf[0]} = brdata1final[BRDATA_SIZE-1:0];
assign {brdata1eff[BRDATA_SIZE-1:0],brdata0eff[BRDATA_SIZE-1:0]} = (({BRDATA_SIZE*2{qren[0]}} & {brdata1[BRDATA_SIZE-1:0],brdata0[BRDATA_SIZE-1:0]}) |
({BRDATA_SIZE*2{qren[1]}} & {brdata2[BRDATA_SIZE-1:0],brdata1[BRDATA_SIZE-1:0]}) |
@ -451,8 +560,7 @@ end
({2{~fetch_to_f2 & ~shift_f2_f1 & ~shift_f2_f0 & ~exu_flush_final}} & f2val[1:0] );
assign sf1val[1:0] = ({2{ f1_shift_2B}} & {1'b0,f1val[1]}) |
({2{~f1_shift_2B}} & f1val[1:0] );
assign sf1val[1:0] = ({2{f1_shift_2B}} & {1'b0, f1val[1]}) | ({2{~f1_shift_2B}} & f1val[1:0]);
assign f1val_in[1:0] = ({2{ fetch_to_f1 & ~exu_flush_final}} & ifu_fetch_val[1:0]) |
({2{ shift_f2_f1 & ~exu_flush_final}} & f2val[1:0] ) |
@ -475,8 +583,7 @@ end
assign q0final[31:0] = ({32{q0sel[0]}} & { q0eff[31:0]}) |
({32{q0sel[1]}} & {16'b0,q0eff[31:16]});
assign q1final[15:0] = ({16{q1sel[0]}} & q1eff[15:0] ) |
({16{q1sel[1]}} & q1eff[31:16]);
assign q1final[15:0] = ({16{q1sel[0]}} & q1eff[15:0]) | ({16{q1sel[1]}} & q1eff[31:16]);
logic [31:1] q0pceff, q0pcfinal;
logic [31:1] q1pceff;
@ -491,8 +598,7 @@ end
assign aligndata[31:0] = ({32{ f0val[1] }} & {q0final[31:0]}) |
({32{~f0val[1] & f0val[0]}} & {q1final[15:0],q0final[15:0]});
assign alignval[1:0] = ({ 2{ f0val[1] }} & {2'b11}) |
({ 2{~f0val[1] & f0val[0]}} & {f1val[0],1'b1});
assign alignval[1:0] = ({2{f0val[1]}} & {2'b11}) | ({2{~f0val[1] & f0val[0]}} & {f1val[0], 1'b1});
assign alignicaf[1:0] = ({ 2{ f0val[1] }} & f0icaf[1:0] ) |
({ 2{~f0val[1] & f0val[0]}} & {f1icaf[0],f0icaf[0]});
@ -500,7 +606,7 @@ end
assign aligndbecc[1:0] = ({ 2{ f0val[1] }} & f0dbecc[1:0] ) |
({ 2{~f0val[1] & f0val[0]}} & {f1dbecc[0],f0dbecc[0]});
if (pt.BTB_ENABLE==1) begin
if (pt.BTB_ENABLE == 1) begin
// for branch prediction
@ -510,7 +616,7 @@ end
assign alignpc4[1:0] = ({ 2{ f0val[1] }} & f0pc4[1:0] ) |
({ 2{~f0val[1] & f0val[0]}} & {f1pc4[0],f0pc4[0]});
if(pt.BTB_FULLYA) begin
if (pt.BTB_FULLYA) begin
assign alignindex[0] = f0index[0];
assign alignindex[1] = f0val[1] ? f0index[1] : f1index[0];
end
@ -527,9 +633,9 @@ end
assign alignhist0[1:0] = ({ 2{ f0val[1] }} & f0hist0[1:0] ) |
({ 2{~f0val[1] & f0val[0]}} & {f1hist0[0],f0hist0[0]});
assign secondpc[31:1] = ({31{ f0val[1] }} & (q0pceff[31:1] + 31'd1)) |
assign secondpc[31:1] = ({31{f0val[1]}} & (q0pceff[31:1] + 31'd1)) |
// you need the base pc for 2nd one only (4B max, 2B for the 1st and 2B for the 2nd)
({31{~f0val[1] & f0val[0]}} & q1pceff[31:1] );
({31{~f0val[1] & f0val[0]}} & q1pceff[31:1]);
assign firstpc[31:1] = q0pcfinal[31:1];
@ -549,12 +655,10 @@ end
assign first4B = (aligndata[1:0] == 2'b11);
assign first2B = ~first4B;
assign ifu_i0_valid = (first4B & alignval[1]) |
(first2B & alignval[0]);
assign ifu_i0_valid = (first4B & alignval[1]) | (first2B & alignval[0]);
// inst access fault on any byte of inst results in access fault for the inst
assign ifu_i0_icaf = (first4B & (|alignicaf[1:0])) |
(first2B & alignicaf[0] );
assign ifu_i0_icaf = (first4B & (|alignicaf[1:0])) | (first2B & alignicaf[0]);
assign ifu_i0_icaf_type[1:0] = (first4B & ~f0val[1] & f0val[0] & ~alignicaf[0] & ~aligndbecc[0]) ? f1ictype[1:0] : f0ictype[1:0];
@ -563,8 +667,7 @@ end
assign ifu_i0_icaf_second = first4B & ~icaf_eff[0] & icaf_eff[1];
assign ifu_i0_dbecc = (first4B & (|aligndbecc[1:0])) |
(first2B & aligndbecc[0] );
assign ifu_i0_dbecc = (first4B & (|aligndbecc[1:0])) | (first2B & aligndbecc[0]);
assign ifirst[31:0] = aligndata[31:0];
@ -573,31 +676,53 @@ end
assign ifu_i0_instr[31:0] = ({32{first4B & alignval[1]}} & ifirst[31:0]) |
({32{first2B & alignval[0]}} & uncompress0[31:0]);
if(pt.BTB_ENABLE==1) begin
if (pt.BTB_ENABLE == 1) begin
// if you detect br does not start on instruction boundary
el2_btb_addr_hash #(.pt(pt)) firsthash (.pc(firstpc [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(firstpc_hash [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
el2_btb_addr_hash #(.pt(pt)) secondhash(.pc(secondpc[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(secondpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
el2_btb_addr_hash #(
.pt(pt)
) firsthash (
.pc (firstpc[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(firstpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
);
el2_btb_addr_hash #(
.pt(pt)
) secondhash (
.pc (secondpc[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(secondpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
);
if(pt.BTB_FULLYA) begin
if (pt.BTB_FULLYA) begin
assign firstbrtag_hash = firstpc;
assign secondbrtag_hash = secondpc;
end
else begin
if(pt.BTB_BTAG_FOLD) begin : btbfold
el2_btb_tag_hash_fold #(.pt(pt)) first_brhash (.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(firstbrtag_hash [pt.BTB_BTAG_SIZE-1:0]));
el2_btb_tag_hash_fold #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0]));
end
else begin
el2_btb_tag_hash #(.pt(pt)) first_brhash (.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(firstbrtag_hash [pt.BTB_BTAG_SIZE-1:0]));
el2_btb_tag_hash #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0]));
end else begin
if (pt.BTB_BTAG_FOLD) begin : btbfold
el2_btb_tag_hash_fold #(
.pt(pt)
) first_brhash (
.pc (firstpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(firstbrtag_hash[pt.BTB_BTAG_SIZE-1:0])
);
el2_btb_tag_hash_fold #(
.pt(pt)
) second_brhash (
.pc (secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0])
);
end else begin
el2_btb_tag_hash #(
.pt(pt)
) first_brhash (
.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(firstbrtag_hash[pt.BTB_BTAG_SIZE-1:0])
);
el2_btb_tag_hash #(
.pt(pt)
) second_brhash (
.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0])
);
end
end // else: !if(pt.BTB_FULLYA)
@ -611,23 +736,17 @@ if(pt.BTB_ENABLE==1) begin
i0_br_start_error = (first4B & alignval[1] & alignbrend[0]);
i0_brp.valid = (first2B & alignbrend[0]) |
(first4B & alignbrend[1]) |
i0_br_start_error;
i0_brp.valid = (first2B & alignbrend[0]) | (first4B & alignbrend[1]) | i0_br_start_error;
i0_brp_pc4 = (first2B & alignpc4[0]) |
(first4B & alignpc4[1]);
i0_brp_pc4 = (first2B & alignpc4[0]) | (first4B & alignpc4[1]);
i0_brp.ret = (first2B & alignret[0]) |
(first4B & alignret[1]);
i0_brp.ret = (first2B & alignret[0]) | (first4B & alignret[1]);
i0_brp.way = (first2B | alignbrend[0]) ? alignway[0] : alignway[1];
i0_brp.hist[1] = (first2B & alignhist1[0]) |
(first4B & alignhist1[1]);
i0_brp.hist[1] = (first2B & alignhist1[0]) | (first4B & alignhist1[1]);
i0_brp.hist[0] = (first2B & alignhist0[0]) |
(first4B & alignhist0[1]);
i0_brp.hist[0] = (first2B & alignhist0[0]) | (first4B & alignhist0[1]);
i0_ends_f1 = first4B & alignfromf1[1];
@ -642,10 +761,9 @@ if(pt.BTB_ENABLE==1) begin
i0_brp.br_error = (i0_brp.valid & i0_brp_pc4 & first2B) |
(i0_brp.valid & ~i0_brp_pc4 & first4B);
if(pt.BTB_FULLYA)
if (pt.BTB_FULLYA)
ifu_i0_fa_index = (first2B | alignbrend[0]) ? alignindex[0] : alignindex[1];
else
ifu_i0_fa_index = '0;
else ifu_i0_fa_index = '0;
end
@ -658,18 +776,20 @@ if(pt.BTB_ENABLE==1) begin
assign ifu_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0] = (first2B | alignbrend[0]) ? firstbrtag_hash[pt.BTB_BTAG_SIZE-1:0] :
secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0];
end
else begin
end else begin
assign i0_brp = '0;
assign ifu_i0_bp_index = '0;
assign ifu_i0_bp_fghr = '0;
assign ifu_i0_bp_btag = '0;
end // else: !if(pt.BTB_ENABLE==1)
end // else: !if(pt.BTB_ENABLE==1)
// decompress
// quiet inputs for 4B inst
el2_ifu_compress_ctl compress0 (.din((first2B) ? aligndata[15:0] : '0), .dout(uncompress0[31:0]));
el2_ifu_compress_ctl compress0 (
.din ((first2B) ? aligndata[15:0] : '0),
.dout(uncompress0[31:0])
);
@ -685,8 +805,7 @@ end // else: !if(pt.BTB_ENABLE==1)
assign shift_4B = i0_shift & first4B;
// exact equations for the queue logic
assign f0_shift_2B = (shift_2B & f0val[0] ) |
(shift_4B & f0val[0] & ~f0val[1]);
assign f0_shift_2B = (shift_2B & f0val[0]) | (shift_4B & f0val[0] & ~f0val[1]);
// f0 valid states

500
Flow/design/ifu/el2_ifu_bp_ctl.sv
View File

@ -25,11 +25,10 @@
//********************************************************************************
module el2_ifu_bp_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk,
input logic rst_l,
@ -43,7 +42,9 @@ import el2_pkg::*;
input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
input logic [$clog2(
pt.BTB_SIZE
)-1:0] dec_fa_error_index, // Fully associative btb error index
input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches
@ -52,10 +53,10 @@ import el2_pkg::*;
input el2_predict_pkt_t exu_mp_pkt, // mispredict packet
input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
input logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
input logic [ pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
input logic exu_flush_final, // all flushes
@ -73,32 +74,34 @@ import el2_pkg::*;
output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
output logic [11:0] ifu_bp_poffset_f, // predicted target
output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)
output logic [1:0][$clog2(
pt.BTB_SIZE
)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)
input logic scan_mode
);
);
localparam BTB_DWIDTH = pt.BTB_TOFFSET_SIZE+pt.BTB_BTAG_SIZE+5;
localparam BTB_DWIDTH_TOP = int'(pt.BTB_TOFFSET_SIZE)+int'(pt.BTB_BTAG_SIZE)+4;
localparam BTB_FA_INDEX = $clog2(pt.BTB_SIZE)-1;
localparam BTB_DWIDTH = pt.BTB_TOFFSET_SIZE + pt.BTB_BTAG_SIZE + 5;
localparam BTB_DWIDTH_TOP = int'(pt.BTB_TOFFSET_SIZE) + int'(pt.BTB_BTAG_SIZE) + 4;
localparam BTB_FA_INDEX = $clog2(pt.BTB_SIZE) - 1;
localparam FA_CMP_LOWER = $clog2(pt.ICACHE_LN_SZ);
localparam FA_TAG_END_UPPER= 5+int'(pt.BTB_TOFFSET_SIZE)+int'(FA_CMP_LOWER)-1; // must cast to int or vcs build fails
localparam FA_TAG_START_LOWER = 3+int'(pt.BTB_TOFFSET_SIZE)+int'(FA_CMP_LOWER);
localparam FA_TAG_END_LOWER = 5+int'(pt.BTB_TOFFSET_SIZE);
localparam FA_TAG_START_LOWER = 3 + int'(pt.BTB_TOFFSET_SIZE) + int'(FA_CMP_LOWER);
localparam FA_TAG_END_LOWER = 5 + int'(pt.BTB_TOFFSET_SIZE);
localparam TAG_START=BTB_DWIDTH-1;
localparam PC4=4;
localparam BOFF=3;
localparam CALL=2;
localparam RET=1;
localparam BV=0;
localparam TAG_START = BTB_DWIDTH - 1;
localparam PC4 = 4;
localparam BOFF = 3;
localparam CALL = 2;
localparam RET = 1;
localparam BV = 0;
localparam LRU_SIZE=pt.BTB_ARRAY_DEPTH;
localparam NUM_BHT_LOOP = (pt.BHT_ARRAY_DEPTH > 16 ) ? 16 : pt.BHT_ARRAY_DEPTH;
localparam LRU_SIZE = pt.BTB_ARRAY_DEPTH;
localparam NUM_BHT_LOOP = (pt.BHT_ARRAY_DEPTH > 16) ? 16 : pt.BHT_ARRAY_DEPTH;
localparam NUM_BHT_LOOP_INNER_HI = (pt.BHT_ARRAY_DEPTH > 16 ) ?pt.BHT_ADDR_LO+3 : pt.BHT_ADDR_HI;
localparam NUM_BHT_LOOP_OUTER_LO = (pt.BHT_ARRAY_DEPTH > 16 ) ?pt.BHT_ADDR_LO+4 : pt.BHT_ADDR_LO;
localparam BHT_NO_ADDR_MATCH = ( pt.BHT_ARRAY_DEPTH <= 16 );
localparam BHT_NO_ADDR_MATCH = (pt.BHT_ARRAY_DEPTH <= 16);
logic exu_mp_valid_write;
@ -124,9 +127,9 @@ import el2_pkg::*;
logic [pt.RET_STACK_SIZE-1:0] rsenable;
logic [11:0] btb_rd_tgt_f;
logic [ 11:0] btb_rd_tgt_f;
logic btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
logic [1:1] bp_total_branch_offset_f;
logic [ 1:1] bp_total_branch_offset_f;
logic [31:1] bp_btb_target_adder_f;
logic [31:1] bp_rs_call_target_f;
@ -139,14 +142,25 @@ import el2_pkg::*;
logic dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_error_addr_wb;
logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
logic
branch_error_collision_f,
fetch_mp_collision_f,
branch_error_collision_p1_f,
fetch_mp_collision_p1_f;
logic branch_error_bank_conflict_f;
logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
logic [1:0] num_valids;
logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
mp_wrindex_dec, mp_wrlru_b0;
logic [LRU_SIZE-1:0]
btb_lru_b0_f,
btb_lru_b0_hold,
btb_lru_b0_ns,
fetch_wrindex_dec,
fetch_wrindex_p1_dec,
fetch_wrlru_b0,
fetch_wrlru_p1_b0,
mp_wrindex_dec,
mp_wrlru_b0;
logic btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
logic tag_match_way0_f, tag_match_way1_f;
logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
@ -154,15 +168,15 @@ import el2_pkg::*;
logic leak_one_f, leak_one_f_d1;
logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_out ;
logic [ LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_out;
logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_out ;
logic [ LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_out;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f;
logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f;
logic [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
@ -175,7 +189,12 @@ import el2_pkg::*;
logic branch_error_bank_conflict_p1_f;
logic tag_match_way0_p1_f, tag_match_way1_p1_f;
logic [1:0] btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
logic [1:0]
btb_vlru_rd_f,
fetch_start_f,
tag_match_vway1_expanded_f,
tag_match_way0_expanded_p1_f,
tag_match_way1_expanded_p1_f;
logic [31:2] fetch_addr_p1_f;
@ -200,7 +219,7 @@ import el2_pkg::*;
assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always
assign exu_mp_way = exu_mp_pkt.way; // repl way
assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history
assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset
assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset
assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address
assign exu_mp_ataken = exu_mp_pkt.ataken;
@ -222,11 +241,21 @@ import el2_pkg::*;
// ----------------------------------------------------------------------
// hash the incoming fetch PC, first guess at hashing algorithm
el2_btb_addr_hash #(.pt(pt)) f1hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
el2_btb_addr_hash #(
.pt(pt)
) f1hash (
.pc (ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
);
assign fetch_addr_p1_f[31:2] = ifc_fetch_addr_f[31:2] + 30'b1;
el2_btb_addr_hash #(.pt(pt)) f1hash_p1(.pc(fetch_addr_p1_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
el2_btb_addr_hash #(
.pt(pt)
) f1hash_p1 (
.pc (fetch_addr_p1_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
.hash(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
);
assign btb_sel_f[1] = ~bht_dir_f[0];
assign btb_sel_f[0] = bht_dir_f[0];
@ -244,9 +273,9 @@ import el2_pkg::*;
// set on leak one, hold until next flush without leak one
assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
logic exu_flush_final_d1;
logic exu_flush_final_d1;
if(!pt.BTB_FULLYA) begin
if (!pt.BTB_FULLYA) begin
assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
exu_mp_valid & ifc_fetch_req_f &
(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
@ -271,17 +300,25 @@ logic exu_flush_final_d1;
// Both ways could hit, use the offset bit to reorder
assign tag_match_way0_expanded_f[1:0] = {tag_match_way0_f & (btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4]),
tag_match_way0_f & ~(btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4])};
assign tag_match_way0_expanded_f[1:0] = {
tag_match_way0_f & (btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4]),
tag_match_way0_f & ~(btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4])
};
assign tag_match_way1_expanded_f[1:0] = {tag_match_way1_f & (btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4]),
tag_match_way1_f & ~(btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4])};
assign tag_match_way1_expanded_f[1:0] = {
tag_match_way1_f & (btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4]),
tag_match_way1_f & ~(btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4])
};
assign tag_match_way0_expanded_p1_f[1:0] = {tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4]),
tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4])};
assign tag_match_way0_expanded_p1_f[1:0] = {
tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4]),
tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4])
};
assign tag_match_way1_expanded_p1_f[1:0] = {tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4]),
tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4])};
assign tag_match_way1_expanded_p1_f[1:0] = {
tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4]),
tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4])
};
assign wayhit_f[1:0] = tag_match_way0_expanded_f[1:0] | tag_match_way1_expanded_f[1:0];
assign wayhit_p1_f[1:0] = tag_match_way0_expanded_p1_f[1:0] | tag_match_way1_expanded_p1_f[1:0];
@ -351,16 +388,19 @@ logic exu_flush_final_d1;
({2{fetch_start_f[1]}} & {tag_match_way1_expanded_p1_f[0], tag_match_way1_expanded_f[1]}) );
rvdffe #(LRU_SIZE) btb_lru_ff (.*, .en(ifc_fetch_req_f | exu_mp_valid),
.din(btb_lru_b0_ns[(LRU_SIZE)-1:0]),
.dout(btb_lru_b0_f[(LRU_SIZE)-1:0]));
rvdffe #(LRU_SIZE) btb_lru_ff (
.*,
.en (ifc_fetch_req_f | exu_mp_valid),
.din (btb_lru_b0_ns[(LRU_SIZE)-1:0]),
.dout(btb_lru_b0_f[(LRU_SIZE)-1:0])
);
end // if (!pt.BTB_FULLYA)
// Detect end of cache line and mask as needed
logic eoc_near;
logic eoc_mask;
assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
assign eoc_mask = ~eoc_near | (|(~ifc_fetch_addr_f[2:1]));
@ -387,8 +427,10 @@ logic exu_flush_final_d1;
// Don't put calls/rets/ja in the predictor, force the bht taken instead
assign bht_force_taken_f[1:0] = {(btb_vbank1_rd_data_f[CALL] | btb_vbank1_rd_data_f[RET]),
(btb_vbank0_rd_data_f[CALL] | btb_vbank0_rd_data_f[RET])};
assign bht_force_taken_f[1:0] = {
(btb_vbank1_rd_data_f[CALL] | btb_vbank1_rd_data_f[RET]),
(btb_vbank0_rd_data_f[CALL] | btb_vbank0_rd_data_f[RET])
};
// taken and valid, otherwise, branch errors must clear the bht
@ -401,8 +443,10 @@ logic exu_flush_final_d1;
({2{fetch_start_f[1]}} & bht_bank0_rd_data_p1_f[1:0]) );
assign bht_dir_f[1:0] = {(bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]) & bht_valid_f[1],
(bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]) & bht_valid_f[0]};
assign bht_dir_f[1:0] = {
(bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]) & bht_valid_f[1],
(bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]) & bht_valid_f[0]
};
assign ifu_bp_inst_mask_f = (ifu_bp_hit_taken_f & btb_sel_f[1]) | ~ifu_bp_hit_taken_f;
@ -427,15 +471,17 @@ logic exu_flush_final_d1;
assign hist1_raw[1:0] = bht_force_taken_f[1:0] | {bht_vbank1_rd_data_f[1],
bht_vbank0_rd_data_f[1]};
assign hist0_raw[1:0] = {bht_vbank1_rd_data_f[0],
bht_vbank0_rd_data_f[0]};
assign hist0_raw[1:0] = {bht_vbank1_rd_data_f[0], bht_vbank0_rd_data_f[0]};
assign pc4_raw[1:0] = {vwayhit_f[1] & btb_vbank1_rd_data_f[PC4],
vwayhit_f[0] & btb_vbank0_rd_data_f[PC4]};
assign pc4_raw[1:0] = {
vwayhit_f[1] & btb_vbank1_rd_data_f[PC4], vwayhit_f[0] & btb_vbank0_rd_data_f[PC4]
};
assign pret_raw[1:0] = {vwayhit_f[1] & ~btb_vbank1_rd_data_f[CALL] & btb_vbank1_rd_data_f[RET],
vwayhit_f[0] & ~btb_vbank0_rd_data_f[CALL] & btb_vbank0_rd_data_f[RET]};
assign pret_raw[1:0] = {
vwayhit_f[1] & ~btb_vbank1_rd_data_f[CALL] & btb_vbank1_rd_data_f[RET],
vwayhit_f[0] & ~btb_vbank0_rd_data_f[CALL] & btb_vbank0_rd_data_f[RET]
};
// GHR
@ -455,7 +501,7 @@ logic exu_flush_final_d1;
assign merged_ghr[pt.BHT_GHR_SIZE-1:0] = (
({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h2}} & {fghr[pt.BHT_GHR_SIZE-3:0], 1'b0, final_h}) | // 0H
({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]})); // PP
logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
@ -464,9 +510,14 @@ logic exu_flush_final_d1;
({pt.BHT_GHR_SIZE{~exu_flush_final_d1 & ifc_fetch_req_f & ic_hit_f & ~leak_one_f_d1}} & merged_ghr[pt.BHT_GHR_SIZE-1:0]) |
({pt.BHT_GHR_SIZE{~exu_flush_final_d1 & ~(ifc_fetch_req_f & ic_hit_f & ~leak_one_f_d1)}} & fghr[pt.BHT_GHR_SIZE-1:0]));
rvdffie #(.WIDTH(pt.BHT_GHR_SIZE+3),.OVERRIDE(1)) fetchghr (.*,
rvdffie #(
.WIDTH(pt.BHT_GHR_SIZE + 3),
.OVERRIDE(1)
) fetchghr (
.*,
.din ({exu_flush_final, exu_mp_way, leak_one_f, fghr_ns[pt.BHT_GHR_SIZE-1:0]}),
.dout({exu_flush_final_d1, exu_mp_way_f, leak_one_f_d1, fghr[pt.BHT_GHR_SIZE-1:0]}));
.dout({exu_flush_final_d1, exu_mp_way_f, leak_one_f_d1, fghr[pt.BHT_GHR_SIZE-1:0]})
);
assign ifu_bp_fghr_f[pt.BHT_GHR_SIZE-1:0] = fghr[pt.BHT_GHR_SIZE-1:0];
@ -483,27 +534,25 @@ logic exu_flush_final_d1;
// compute target
// Form the fetch group offset based on the btb hit location and the location of the branch within the 4 byte chunk
// .i 5
// .o 3
// .ilb bht_dir_f[1] bht_dir_f[0] fetch_start_f[1] fetch_start_f[0] btb_rd_pc4_f
// .ob bloc_f[1] bloc_f[0] use_fa_plus
// .type fr
//
//
// ## rotdir[1:0] fs pc4 off fapl
// -1 01 - 01 0
// 10 01 - 10 0
//
// -1 10 - 10 0
// 10 10 0 01 1
// 10 10 1 01 0
logic [1:0] bloc_f;
logic use_fa_plus;
assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
& fetch_start_f[0]);
assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
& ~fetch_start_f[0]);
assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
// .i 5
// .o 3
// .ilb bht_dir_f[1] bht_dir_f[0] fetch_start_f[1] fetch_start_f[0] btb_rd_pc4_f
// .ob bloc_f[1] bloc_f[0] use_fa_plus
// .type fr
//
//
// ## rotdir[1:0] fs pc4 off fapl
// -1 01 - 01 0
// 10 01 - 10 0
//
// -1 10 - 10 0
// 10 10 0 01 1
// 10 10 1 01 0
logic [1:0] bloc_f;
logic use_fa_plus;
assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0] & fetch_start_f[0]);
assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0] & ~fetch_start_f[0]);
assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
@ -513,7 +562,15 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
assign bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f;
logic [31:2] adder_pc_in_f, ifc_fetch_adder_prior;
rvdfflie #(.WIDTH(30), .LEFT(19)) faddrf_ff (.*, .en(ifc_fetch_req_f & ~ifu_bp_hit_taken_f & ic_hit_f), .din(ifc_fetch_addr_f[31:2]), .dout(ifc_fetch_adder_prior[31:2]));
rvdfflie #(
.WIDTH(30),
.LEFT (19)
) faddrf_ff (
.*,
.en (ifc_fetch_req_f & ~ifu_bp_hit_taken_f & ic_hit_f),
.din (ifc_fetch_addr_f[31:2]),
.dout(ifc_fetch_adder_prior[31:2])
);
assign ifu_bp_poffset_f[11:0] = btb_rd_tgt_f[11:0];
@ -522,7 +579,8 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
({30{ btb_fg_crossing_f}} & ifc_fetch_adder_prior[31:2]) |
({30{~btb_fg_crossing_f & ~use_fa_plus}} & ifc_fetch_addr_f[31:2]));
rvbradder predtgt_addr (.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
rvbradder predtgt_addr (
.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
.offset(btb_rd_tgt_f[11:0]),
.dout(bp_btb_target_adder_f[31:1])
);
@ -535,7 +593,8 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
// Return Stack
// ----------------------------------------------------------------------
rvbradder rs_addr (.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
rvbradder rs_addr (
.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
.offset({11'b0, ~btb_rd_pc4_f}),
.dout(bp_rs_call_target_f[31:1])
);
@ -552,19 +611,23 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
assign rsenable[0] = ~rs_hold;
for (i=0; i<pt.RET_STACK_SIZE; i++) begin : retstack
for (i = 0; i < pt.RET_STACK_SIZE; i++) begin : retstack
// for the last entry in the stack, we don't have a pop position
if(i==pt.RET_STACK_SIZE-1) begin
if (i == pt.RET_STACK_SIZE - 1) begin
assign rets_in[i][31:0] = rets_out[i-1][31:0];
assign rsenable[i] = rs_push;
end
else if(i>0) begin
end else if (i > 0) begin
assign rets_in[i][31:0] = ( ({32{rs_push}} & rets_out[i-1][31:0]) |
({32{rs_pop}} & rets_out[i+1][31:0]) );
assign rsenable[i] = rs_push | rs_pop;
end
rvdffe #(32) rets_ff (.*, .en(rsenable[i]), .din(rets_in[i][31:0]), .dout(rets_out[i][31:0]));
rvdffe #(32) rets_ff (
.*,
.en (rsenable[i]),
.din (rets_in[i][31:0]),
.dout(rets_out[i][31:0])
);
end : retstack
@ -583,19 +646,38 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
assign btb_wr_tag[pt.BTB_BTAG_SIZE-1:0] = exu_mp_btag[pt.BTB_BTAG_SIZE-1:0];
if(!pt.BTB_FULLYA) begin
if (!pt.BTB_FULLYA) begin
if(pt.BTB_BTAG_FOLD) begin : btbfold
el2_btb_tag_hash_fold #(.pt(pt)) rdtagf (.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
el2_btb_tag_hash_fold #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({fetch_addr_p1_f[ pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
end
else begin
el2_btb_tag_hash #(.pt(pt)) rdtagf(.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
el2_btb_tag_hash #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({fetch_addr_p1_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
if (pt.BTB_BTAG_FOLD) begin : btbfold
el2_btb_tag_hash_fold #(
.pt(pt)
) rdtagf (
.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]})
);
el2_btb_tag_hash_fold #(
.pt(pt)
) rdtagp1f (
.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({fetch_addr_p1_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]})
);
end else begin
el2_btb_tag_hash #(
.pt(pt)
) rdtagf (
.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({
ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]
})
);
el2_btb_tag_hash #(
.pt(pt)
) rdtagp1f (
.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({
fetch_addr_p1_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]
})
);
end
assign btb_wr_en_way0 = ( ({{~exu_mp_way & exu_mp_valid_write & ~dec_tlu_error_wb}}) |
@ -611,8 +693,15 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
end // if (!pt.BTB_FULLYA)
assign btb_wr_data[BTB_DWIDTH-1:0] = {btb_wr_tag[pt.BTB_BTAG_SIZE-1:0], exu_mp_tgt[pt.BTB_TOFFSET_SIZE-1:0], exu_mp_pc4, exu_mp_boffset,
exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
assign btb_wr_data[BTB_DWIDTH-1:0] = {
btb_wr_tag[pt.BTB_BTAG_SIZE-1:0],
exu_mp_tgt[pt.BTB_TOFFSET_SIZE-1:0],
exu_mp_pc4,
exu_mp_boffset,
exu_mp_call | exu_mp_ja,
exu_mp_ret | exu_mp_ja,
btb_valid
};
assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
logic [1:0] bht_wr_data0, bht_wr_data2;
@ -620,7 +709,7 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
assign bht_wr_en2[1:0] = {2{dec_tlu_br0_v_wb}} & {dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb} ;
assign bht_wr_en2[1:0] = {2{dec_tlu_br0_v_wb}} & {dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb};
// Experiments show this is the best priority scheme for same bank/index writes at the same time.
assign bht_wr_data0[1:0] = exu_mp_hist[1:0]; // lowest priority
@ -628,13 +717,39 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]
bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
el2_btb_ghr_hash #(.pt(pt)) mpghrhs (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
el2_btb_ghr_hash #(.pt(pt)) fghrhs_p1 (.hashin(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]
mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
el2_btb_ghr_hash #(
.pt(pt)
) mpghrhs (
.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]),
.ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]),
.hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO])
);
el2_btb_ghr_hash #(
.pt(pt)
) br0ghrhs (
.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]),
.ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]),
.hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO])
);
el2_btb_ghr_hash #(
.pt(pt)
) fghrhs (
.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]),
.ghr(fghr[pt.BHT_GHR_SIZE-1:0]),
.hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO])
);
el2_btb_ghr_hash #(
.pt(pt)
) fghrhs_p1 (
.hashin(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]),
.ghr(fghr[pt.BHT_GHR_SIZE-1:0]),
.hash(bht_rd_addr_hashed_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO])
);
assign bht_wr_addr0[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];
assign bht_wr_addr2[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];
@ -648,31 +763,35 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
// BTB
// Entry -> tag[pt.BTB_BTAG_SIZE-1:0], toffset[11:0], pc4, boffset, call, ret, valid
if(!pt.BTB_FULLYA) begin
if (!pt.BTB_FULLYA) begin
for (j=0 ; j<LRU_SIZE ; j++) begin : BTB_FLOPS
for (j = 0; j < LRU_SIZE; j++) begin : BTB_FLOPS
// Way 0
rvdffe #(17+pt.BTB_BTAG_SIZE) btb_bank0_way0 (.*,
.en(((btb_wr_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == j) & btb_wr_en_way0)),
rvdffe #(17 + pt.BTB_BTAG_SIZE) btb_bank0_way0 (
.*,
.en (((btb_wr_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == j) & btb_wr_en_way0)),
.din (btb_wr_data[BTB_DWIDTH-1:0]),
.dout (btb_bank0_rd_data_way0_out[j]));
.dout(btb_bank0_rd_data_way0_out[j])
);
// Way 1
rvdffe #(17+pt.BTB_BTAG_SIZE) btb_bank0_way1 (.*,
.en(((btb_wr_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == j) & btb_wr_en_way1)),
rvdffe #(17 + pt.BTB_BTAG_SIZE) btb_bank0_way1 (
.*,
.en (((btb_wr_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == j) & btb_wr_en_way1)),
.din (btb_wr_data[BTB_DWIDTH-1:0]),
.dout (btb_bank0_rd_data_way1_out[j]));
.dout(btb_bank0_rd_data_way1_out[j])
);
end
always_comb begin : BTB_rd_mux
btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] = '0 ;
btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] = '0 ;
btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] = '0 ;
btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] = '0;
btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] = '0;
btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] = '0;
btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0;
for (int j=0; j< LRU_SIZE; j++) begin
for (int j = 0; j < LRU_SIZE; j++) begin
if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] = btb_bank0_rd_data_way0_out[j];
@ -680,7 +799,7 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
end
end
for (int j=0; j< LRU_SIZE; j++) begin
for (int j = 0; j < LRU_SIZE; j++) begin
if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] = btb_bank0_rd_data_way0_out[j];
@ -689,20 +808,20 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
end
end
end
end // if (!pt.BTB_FULLYA)
end // if (!pt.BTB_FULLYA)
if(pt.BTB_FULLYA) begin : fa
if (pt.BTB_FULLYA) begin : fa
logic found1, hit0, hit1;
logic btb_used_reset, write_used;
logic [$clog2(pt.BTB_SIZE)-1:0] btb_fa_wr_addr0, hit0_index, hit1_index;
logic [pt.BTB_SIZE-1:0] btb_tag_hit, btb_offset_0, btb_offset_1, btb_used_ns, btb_used,
wr0_en, btb_upper_hit;
logic [pt.BTB_SIZE-1:0]
btb_tag_hit, btb_offset_0, btb_offset_1, btb_used_ns, btb_used, wr0_en, btb_upper_hit;
logic [pt.BTB_SIZE-1:0][BTB_DWIDTH-1:0] btbdata;
// Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
@ -721,10 +840,10 @@ end // if (!pt.BTB_FULLYA)
always_comb begin
btb_vbank0_rd_data_f = '0;
btb_vbank1_rd_data_f = '0;
// btb_tag_hit = '0;
// btb_upper_hit = '0;
// btb_offset_0 = '0;
// btb_offset_1 = '0;
// btb_tag_hit = '0;
// btb_upper_hit = '0;
// btb_offset_0 = '0;
// btb_offset_1 = '0;
found1 = 1'b0;
hit0 = 1'b0;
@ -733,44 +852,44 @@ end // if (!pt.BTB_FULLYA)
hit1_index = '0;
btb_fa_wr_addr0 = '0;
for(int i=0; i<pt.BTB_SIZE; i++) begin
for (int i = 0; i < pt.BTB_SIZE; i++) begin
logic upper_hit, offset_0, offset_1;
// Break the cmp into chunks for lower area.
// Chunk1: FA 31:6 or 31:5 depending on icache line size
// Chunk2: FA 5:1 or 4:1 depending on icache line size
// btb_upper_hit[i] = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i];
// btb_offset_0[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
// btb_offset_1[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
// btb_upper_hit[i] = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i];
// btb_offset_0[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
// btb_offset_1[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
upper_hit = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i];
offset_0 = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & upper_hit;
offset_1 = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & upper_hit;
if(~hit0) begin
if(offset_0) begin
hit0_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i);
if (~hit0) begin
if (offset_0) begin
hit0_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX + 1)'(i);
// hit unless we are also writing this entry at the same time
hit0 = 1'b1;
end
end
if(~hit1) begin
if(offset_1) begin
hit1_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i);
if (~hit1) begin
if (offset_1) begin
hit1_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX + 1)'(i);
hit1 = 1'b1;
end
end
// Mux out the 2 potential branches
if(offset_0)
if (offset_0)
btb_vbank0_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_f ? btb_wr_data : btbdata[i];
if(offset_1)
if (offset_1)
btb_vbank1_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_p1_f ? btb_wr_data : btbdata[i];
// find the first zero from bit zero in the used vector, this is the write address
if(~found1 & ((exu_mp_valid_write & ~exu_mp_pkt.way) | dec_tlu_error_wb)) begin
if(~btb_used[i]) begin
if (~found1 & ((exu_mp_valid_write & ~exu_mp_pkt.way) | dec_tlu_error_wb)) begin
if (~btb_used[i]) begin
btb_fa_wr_addr0[BTB_FA_INDEX:0] = i[BTB_FA_INDEX:0];
found1 = 1'b1;
end
@ -783,15 +902,18 @@ end // if (!pt.BTB_FULLYA)
// way bit is reused as the predicted bit
assign way_raw[1:0] = vwayhit_f[1:0] | {fetch_mp_collision_p1_f, fetch_mp_collision_f};
for (j=0 ; j<pt.BTB_SIZE ; j++) begin : BTB_FAFLOPS
for (j = 0; j < pt.BTB_SIZE; j++) begin : BTB_FAFLOPS
assign wr0_en[j] = ((btb_fa_wr_addr0[BTB_FA_INDEX:0] == j) & (exu_mp_valid_write & ~exu_mp_pkt.way)) |
((dec_fa_error_index == j) & dec_tlu_error_wb);
rvdffe #(BTB_DWIDTH) btb_fa (.*, .clk(clk),
rvdffe #(BTB_DWIDTH) btb_fa (
.*,
.clk (clk),
.en (wr0_en[j]),
.din (btb_wr_data[BTB_DWIDTH-1:0]),
.dout(btbdata[j]));
.dout(btbdata[j])
);
end // block: BTB_FAFLOPS
assign ifu_bp_fa_index_f[1] = hit1 ? hit1_index : '0;
@ -808,12 +930,15 @@ end // if (!pt.BTB_FULLYA)
assign write_used = btb_used_reset | ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb;
rvdffe #(pt.BTB_SIZE) btb_usedf (.*, .clk(clk),
rvdffe #(pt.BTB_SIZE) btb_usedf (
.*,
.clk (clk),
.en (write_used),
.din (btb_used_ns[pt.BTB_SIZE-1:0]),
.dout(btb_used[pt.BTB_SIZE-1:0]));
.dout(btb_used[pt.BTB_SIZE-1:0])
);
end // block: fa
end // block: fa
//-----------------------------------------------------------------------------
@ -822,52 +947,58 @@ end // block: fa
//
//-----------------------------------------------------------------------------
// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0] bht_bank_wr_data ;
logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0] bht_bank_rd_data_out ;
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clken ;
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clk ;
// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0] bht_bank_sel ;
// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0] bht_bank_wr_data ;
logic [1:0][ pt.BHT_ARRAY_DEPTH-1:0][1:0] bht_bank_rd_data_out;
logic [1:0][(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clken;
logic [1:0][(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clk;
// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0] bht_bank_sel ;
for ( i=0; i<2; i++) begin : BANKS
wire[pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1;
for (i = 0; i < 2; i++) begin : BANKS
wire [pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1;
assign wr0 = bht_wr_en0[i] << bht_wr_addr0;
assign wr1 = bht_wr_en2[i] << bht_wr_addr2;
for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP
for (genvar k = 0; k < (pt.BHT_ARRAY_DEPTH) / NUM_BHT_LOOP; k++) begin : BHT_CLK_GROUP
assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
(bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH));
rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* );
rvclkhdr bht_bank_grp_cgc (
.en(bht_bank_clken[i][k]),
.l1clk(bht_bank_clk[i][k]),
.*
);
for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS
wire[1:0] wdata;
for (j = 0; j < NUM_BHT_LOOP; j++) begin : BHT_FLOPS
wire [1:0] wdata;
wire bank_sel = wr1[NUM_BHT_LOOP*k+j] | wr0[NUM_BHT_LOOP*k+j];
// assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
// (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ;
// assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
// (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ;
// assign bht_bank_wr_data[i][k][j] = (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data2[1:0] :
// bht_wr_data0[1:0] ;
assign wdata = wr1[NUM_BHT_LOOP*k+j] ? bht_wr_data2[1:0] :bht_wr_data0;
// assign bht_bank_wr_data[i][k][j] = (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data2[1:0] :
// bht_wr_data0[1:0] ;
assign wdata = wr1[NUM_BHT_LOOP*k+j] ? bht_wr_data2[1:0] : bht_wr_data0;
rvdffs_fpga #(2) bht_bank (.*,
rvdffs_fpga #(2) bht_bank (
.*,
.clk (bht_bank_clk[i][k]),
.en (bank_sel),
.rawclk (clk),
.rawclk(clk),
.clken (bank_sel),
.din (wdata),
.dout (bht_bank_rd_data_out[i][(16*k)+j]));
.dout (bht_bank_rd_data_out[i][(16*k)+j])
);
end // block: BHT_FLOPS
end // block: BHT_CLK_GROUP
end // block: BANKS
always_comb begin : BHT_rd_mux
bht_bank0_rd_data_f[1:0] = '0 ;
bht_bank1_rd_data_f[1:0] = '0 ;
bht_bank0_rd_data_p1_f[1:0] = '0 ;
for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
bht_bank0_rd_data_f[1:0] = '0;
bht_bank1_rd_data_f[1:0] = '0;
bht_bank0_rd_data_p1_f[1:0] = '0;
for (int j = 0; j < pt.BHT_ARRAY_DEPTH; j++) begin
if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
@ -879,13 +1010,12 @@ end // block: fa
end // block: BHT_rd_mux
function [1:0] countones;
function [1:0] countones;
input [1:0] valid;
begin
countones[1:0] = {2'b0, valid[1]} +
{2'b0, valid[0]};
countones[1:0] = {2'b0, valid[1]} + {2'b0, valid[0]};
end
endfunction
endmodule // el2_ifu_bp_ctl

181
Flow/design/ifu/el2_ifu_compress_ctl.sv
View File

@ -18,27 +18,26 @@
// purpose of this file is to convert 16b RISCV compressed instruction into 32b equivalent
module el2_ifu_compress_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic [15:0] din, // 16-bit compressed instruction
output logic [31:0] dout // 32-bit uncompressed instruction
);
);
logic legal;
logic [15:0] i;
logic [31:0] o,l1,l2,l3;
logic [31:0] o, l1, l2, l3;
assign i[15:0] = din[15:0];
logic [4:0] rs2d,rdd,rdpd,rs2pd;
logic [4:0] rs2d, rdd, rdpd, rs2pd;
logic rdrd;
logic rdrs1;
@ -106,44 +105,42 @@ import el2_pkg::*;
// rs2
assign l1[24:20] = o[24:20] |
({5{rs2rs2}} & rs2d[4:0]) |
({5{rs2prs2}} & rs2pd[4:0]);
assign l1[24:20] = o[24:20] | ({5{rs2rs2}} & rs2d[4:0]) | ({5{rs2prs2}} & rs2pd[4:0]);
assign l1[31:25] = o[31:25];
logic [5:0] simm5d;
logic [9:2] uimm9d;
logic [ 5:0] simm5d;
logic [ 9:2] uimm9d;
logic [9:4] simm9d;
logic [6:2] ulwimm6d;
logic [7:2] ulwspimm7d;
logic [5:0] uimm5d;
logic [20:1] sjald;
logic [ 9:4] simm9d;
logic [ 6:2] ulwimm6d;
logic [ 7:2] ulwspimm7d;
logic [ 5:0] uimm5d;
logic [ 20:1] sjald;
logic [31:12] sluimmd;
// merge in immediates + jal offset
assign simm5d[5:0] = { i[12], i[6:2] };
assign simm5d[5:0] = {i[12], i[6:2]};
assign uimm9d[9:2] = { i[10:7], i[12:11], i[5], i[6] };
assign uimm9d[9:2] = {i[10:7], i[12:11], i[5], i[6]};
assign simm9d[9:4] = { i[12], i[4:3], i[5], i[2], i[6] };
assign simm9d[9:4] = {i[12], i[4:3], i[5], i[2], i[6]};
assign ulwimm6d[6:2] = { i[5], i[12:10], i[6] };
assign ulwimm6d[6:2] = {i[5], i[12:10], i[6]};
assign ulwspimm7d[7:2] = { i[3:2], i[12], i[6:4] };
assign ulwspimm7d[7:2] = {i[3:2], i[12], i[6:4]};
assign uimm5d[5:0] = { i[12], i[6:2] };
assign uimm5d[5:0] = {i[12], i[6:2]};
assign sjald[11:1] = { i[12], i[8], i[10:9], i[6], i[7], i[2], i[11], i[5:4], i[3] };
assign sjald[11:1] = {i[12], i[8], i[10:9], i[6], i[7], i[2], i[11], i[5:4], i[3]};
assign sjald[20:12] = {9{i[12]}};
assign sluimmd[31:12] = { {15{i[12]}}, i[6:2] };
assign sluimmd[31:12] = {{15{i[12]}}, i[6:2]};
assign l2[31:20] = ( l1[31:20] ) |
@ -173,11 +170,11 @@ import el2_pkg::*;
logic [7:2] uswspimm7d;
assign sbr8d[8:1] = { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
assign sbr8d[8:1] = {i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3]};
assign uswimm6d[6:2] = { i[5], i[12:10], i[6] };
assign uswimm6d[6:2] = {i[5], i[12:10], i[6]};
assign uswspimm7d[7:2] = { i[8:7], i[12:9] };
assign uswspimm7d[7:2] = {i[8:7], i[12:9]};
assign l3[31:25] = ( l2[31:25] ) |
( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) |
@ -198,157 +195,157 @@ import el2_pkg::*;
assign dout[31:0] = l3[31:0] & {32{legal}};
// file "cdecode" is human readable file that has all of the compressed instruction decodes defined and is part of git repo
// modify this file as needed
// file "cdecode" is human readable file that has all of the compressed instruction decodes defined and is part of git repo
// modify this file as needed
// to generate all the equations below from "cdecode" except legal equation:
// to generate all the equations below from "cdecode" except legal equation:
// 1) coredecode -in cdecode > cdecode.e
// 1) coredecode -in cdecode > cdecode.e
// 2) espresso -Dso -oeqntott cdecode.e | addassign > compress_equations
// 2) espresso -Dso -oeqntott cdecode.e | addassign > compress_equations
// to generate the legal (16b compressed instruction is legal) equation below:
// to generate the legal (16b compressed instruction is legal) equation below:
// 1) coredecode -in cdecode -legal > clegal.e
// 1) coredecode -in cdecode -legal > clegal.e
// 2) espresso -Dso -oeqntott clegal.e | addassign > clegal_equation
// 2) espresso -Dso -oeqntott clegal.e | addassign > clegal_equation
// espresso decodes
assign rdrd = (!i[14]&i[6]&i[1]) | (!i[15]&i[14]&i[11]&i[0]) | (!i[14]&i[5]&i[1]) | (
// espresso decodes
assign rdrd = (!i[14]&i[6]&i[1]) | (!i[15]&i[14]&i[11]&i[0]) | (!i[14]&i[5]&i[1]) | (
!i[15]&i[14]&i[10]&i[0]) | (!i[14]&i[4]&i[1]) | (!i[15]&i[14]&i[9]
&i[0]) | (!i[14]&i[3]&i[1]) | (!i[15]&i[14]&!i[8]&i[0]) | (!i[14]
&i[2]&i[1]) | (!i[15]&i[14]&i[7]&i[0]) | (!i[15]&i[1]) | (!i[15]
&!i[13]&i[0]);
assign rdrs1 = (!i[14]&i[12]&i[11]&i[1]) | (!i[14]&i[12]&i[10]&i[1]) | (!i[14]
assign rdrs1 = (!i[14]&i[12]&i[11]&i[1]) | (!i[14]&i[12]&i[10]&i[1]) | (!i[14]
&i[12]&i[9]&i[1]) | (!i[14]&i[12]&i[8]&i[1]) | (!i[14]&i[12]&i[7]
&i[1]) | (!i[14]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
&i[12]&i[6]&i[1]) | (!i[14]&i[12]&i[5]&i[1]) | (!i[14]&i[12]&i[4]
&i[1]) | (!i[14]&i[12]&i[3]&i[1]) | (!i[14]&i[12]&i[2]&i[1]) | (
!i[15]&!i[14]&!i[13]&i[0]) | (!i[15]&!i[14]&i[1]);
assign rs2rs2 = (i[15]&i[6]&i[1]) | (i[15]&i[5]&i[1]) | (i[15]&i[4]&i[1]) | (
assign rs2rs2 = (i[15]&i[6]&i[1]) | (i[15]&i[5]&i[1]) | (i[15]&i[4]&i[1]) | (
i[15]&i[3]&i[1]) | (i[15]&i[2]&i[1]) | (i[15]&i[14]&i[1]);
assign rdprd = (i[15]&!i[14]&!i[13]&i[0]);
assign rdprd = (i[15] & !i[14] & !i[13] & i[0]);
assign rdprs1 = (i[15]&!i[13]&i[0]) | (i[15]&i[14]&i[0]) | (i[14]&!i[1]&!i[0]);
assign rdprs1 = (i[15] & !i[13] & i[0]) | (i[15] & i[14] & i[0]) | (i[14] & !i[1] & !i[0]);
assign rs2prs2 = (i[15]&!i[14]&!i[13]&i[11]&i[10]&i[0]) | (i[15]&!i[1]&!i[0]);
assign rs2prs2 = (i[15] & !i[14] & !i[13] & i[11] & i[10] & i[0]) | (i[15] & !i[1] & !i[0]);
assign rs2prd = (!i[15]&!i[1]&!i[0]);
assign rs2prd = (!i[15] & !i[1] & !i[0]);
assign uimm9_2 = (!i[14]&!i[1]&!i[0]);
assign uimm9_2 = (!i[14] & !i[1] & !i[0]);
assign ulwimm6_2 = (!i[15]&i[14]&!i[1]&!i[0]);
assign ulwimm6_2 = (!i[15] & i[14] & !i[1] & !i[0]);
assign ulwspimm7_2 = (!i[15]&i[14]&i[1]);
assign ulwspimm7_2 = (!i[15] & i[14] & i[1]);
assign rdeq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);
assign rdeq2 = (!i[15] & i[14] & i[13] & !i[11] & !i[10] & !i[9] & i[8] & !i[7]);
assign rdeq1 = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
assign rdeq1 = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
&i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]
&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]
&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]
&!i[2]&i[1]) | (!i[15]&!i[14]&i[13]);
assign rs1eq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]) | (i[14]
assign rs1eq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]) | (i[14]
&i[1]) | (!i[14]&!i[1]&!i[0]);
assign sbroffset8_1 = (i[15]&i[14]&i[0]);
assign sbroffset8_1 = (i[15] & i[14] & i[0]);
assign simm9_4 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);
assign simm9_4 = (!i[15] & i[14] & i[13] & !i[11] & !i[10] & !i[9] & i[8] & !i[7]);
assign simm5_0 = (!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (!i[15]&!i[13]&i[0]);
assign simm5_0 = (!i[14] & !i[13] & i[11] & !i[10] & i[0]) | (!i[15] & !i[13] & i[0]);
assign sjaloffset11_1 = (!i[14]&i[13]);
assign sjaloffset11_1 = (!i[14] & i[13]);
assign sluimm17_12 = (!i[15]&i[14]&i[13]&i[7]) | (!i[15]&i[14]&i[13]&!i[8]) | (
assign sluimm17_12 = (!i[15]&i[14]&i[13]&i[7]) | (!i[15]&i[14]&i[13]&!i[8]) | (
!i[15]&i[14]&i[13]&i[9]) | (!i[15]&i[14]&i[13]&i[10]) | (!i[15]&i[14]
&i[13]&i[11]);
assign uimm5_0 = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (!i[15]&!i[14]&i[1]);
assign uimm5_0 = (i[15] & !i[14] & !i[13] & !i[11] & i[0]) | (!i[15] & !i[14] & i[1]);
assign uswimm6_2 = (i[15]&!i[1]&!i[0]);
assign uswimm6_2 = (i[15] & !i[1] & !i[0]);
assign uswspimm7_2 = (i[15]&i[14]&i[1]);
assign uswspimm7_2 = (i[15] & i[14] & i[1]);
assign o[31] = 1'b0;
assign o[31] = 1'b0;
assign o[30] = (i[15]&!i[14]&!i[13]&i[10]&!i[6]&!i[5]&i[0]) | (i[15]&!i[14]
assign o[30] = (i[15]&!i[14]&!i[13]&i[10]&!i[6]&!i[5]&i[0]) | (i[15]&!i[14]
&!i[13]&!i[11]&i[10]&i[0]);
assign o[29] = 1'b0;
assign o[29] = 1'b0;
assign o[28] = 1'b0;
assign o[28] = 1'b0;
assign o[27] = 1'b0;
assign o[27] = 1'b0;
assign o[26] = 1'b0;
assign o[26] = 1'b0;
assign o[25] = 1'b0;
assign o[25] = 1'b0;
assign o[24] = 1'b0;
assign o[24] = 1'b0;
assign o[23] = 1'b0;
assign o[23] = 1'b0;
assign o[22] = 1'b0;
assign o[22] = 1'b0;
assign o[21] = 1'b0;
assign o[21] = 1'b0;
assign o[20] = (!i[14]&i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]
assign o[20] = (!i[14]&i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]
&!i[3]&!i[2]&i[1]);
assign o[19] = 1'b0;
assign o[19] = 1'b0;
assign o[18] = 1'b0;
assign o[18] = 1'b0;
assign o[17] = 1'b0;
assign o[17] = 1'b0;
assign o[16] = 1'b0;
assign o[16] = 1'b0;
assign o[15] = 1'b0;
assign o[15] = 1'b0;
assign o[14] = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (i[15]&!i[14]&!i[13]&!i[10]
assign o[14] = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (i[15]&!i[14]&!i[13]&!i[10]
&i[0]) | (i[15]&!i[14]&!i[13]&i[6]&i[0]) | (i[15]&!i[14]&!i[13]&i[5]
&i[0]);
assign o[13] = (i[15]&!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (i[15]&!i[14]&!i[13]
assign o[13] = (i[15]&!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (i[15]&!i[14]&!i[13]
&i[11]&i[6]&i[0]) | (i[14]&!i[0]);
assign o[12] = (i[15]&!i[14]&!i[13]&i[6]&i[5]&i[0]) | (i[15]&!i[14]&!i[13]&!i[11]
assign o[12] = (i[15]&!i[14]&!i[13]&i[6]&i[5]&i[0]) | (i[15]&!i[14]&!i[13]&!i[11]
&i[0]) | (i[15]&!i[14]&!i[13]&!i[10]&i[0]) | (!i[15]&!i[14]&i[1]) | (
i[15]&i[14]&i[13]);
assign o[11] = 1'b0;
assign o[11] = 1'b0;
assign o[10] = 1'b0;
assign o[10] = 1'b0;
assign o[9] = 1'b0;
assign o[9] = 1'b0;
assign o[8] = 1'b0;
assign o[8] = 1'b0;
assign o[7] = 1'b0;
assign o[7] = 1'b0;
assign o[6] = (i[15]&!i[14]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[0]) | (!i[14]&i[13]) | (
assign o[6] = (i[15]&!i[14]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[0]) | (!i[14]&i[13]) | (
i[15]&i[14]&i[0]);
assign o[5] = (i[15]&!i[0]) | (i[15]&i[11]&i[10]) | (i[13]&!i[8]) | (i[13]&i[7]) | (
assign o[5] = (i[15]&!i[0]) | (i[15]&i[11]&i[10]) | (i[13]&!i[8]) | (i[13]&i[7]) | (
i[13]&i[9]) | (i[13]&i[10]) | (i[13]&i[11]) | (!i[14]&i[13]) | (
i[15]&i[14]);
assign o[4] = (!i[14]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[0]) | (!i[15]&!i[14]
assign o[4] = (!i[14]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[0]) | (!i[15]&!i[14]
&!i[0]) | (!i[14]&i[6]&!i[0]) | (!i[15]&i[14]&i[0]) | (!i[14]&i[5]
&!i[0]) | (!i[14]&i[4]&!i[0]) | (!i[14]&!i[13]&i[0]) | (!i[14]&i[3]
&!i[0]) | (!i[14]&i[2]&!i[0]);
assign o[3] = (!i[14]&i[13]);
assign o[3] = (!i[14] & i[13]);
assign o[2] = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
assign o[2] = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
&i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]
&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]
&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]
@ -356,13 +353,13 @@ assign o[2] = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
&!i[0]) | (!i[15]&i[13]&!i[8]) | (!i[15]&i[13]&i[7]) | (!i[15]&i[13]
&i[9]) | (!i[15]&i[13]&i[10]) | (!i[15]&i[13]&i[11]) | (!i[14]&i[13]);
// 32b instruction has lower two bits 2'b11
// 32b instruction has lower two bits 2'b11
assign o[1] = 1'b1;
assign o[1] = 1'b1;
assign o[0] = 1'b1;
assign o[0] = 1'b1;
assign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[6]&i[1]&!i[0]) | (
assign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[6]&i[1]&!i[0]) | (
!i[15]&!i[13]&i[11]&!i[1]) | (!i[13]&!i[12]&i[5]&i[1]&!i[0]) | (
!i[13]&!i[12]&i[10]&i[1]&!i[0]) | (!i[15]&!i[13]&i[6]&!i[1]) | (
i[15]&!i[12]&!i[1]&i[0]) | (!i[13]&!i[12]&i[9]&i[1]&!i[0]) | (!i[12]

624
Flow/design/ifu/el2_ifu_ic_mem.sv
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File diff suppressed because it is too large Load Diff

231
Flow/design/ifu/el2_ifu_iccm_mem.sv
View File

@ -20,10 +20,10 @@
//********************************************************************************
module el2_ifu_iccm_mem
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
@ -49,22 +49,22 @@ import el2_pkg::*;
logic [pt.ICCM_NUM_BANKS-1:0] wren_bank;
logic [pt.ICCM_NUM_BANKS-1:0] rden_bank;
logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;
logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
logic [pt.ICCM_BITS-1:1] addr_bank_inc;
logic [pt.ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
logic [pt.ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
logic [63:0] iccm_rd_data_pre;
logic [63:0] iccm_data;
logic [1:0] addr_incr;
logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
logic [pt.ICCM_NUM_BANKS-1:0][38:0] iccm_bank_dout, iccm_bank_dout_fn;
logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_wr_data;
logic [ pt.ICCM_BITS-1:1] addr_bank_inc;
logic [ pt.ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
logic [ pt.ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
logic [ 63:0] iccm_rd_data_pre;
logic [ 63:0] iccm_data;
logic [ 1:0] addr_incr;
logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_wr_data_vec;
// logic to handle hard persisten faults
logic [1:0] [pt.ICCM_BITS-1:2] redundant_address;
logic [1:0] [38:0] redundant_data;
logic [1:0] redundant_valid;
logic [ 1:0][pt.ICCM_BITS-1:2] redundant_address;
logic [ 1:0][ 38:0] redundant_data;
logic [ 1:0] redundant_valid;
logic [pt.ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
@ -91,15 +91,15 @@ import el2_pkg::*;
// end of testing flip
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10 : 2'b01;
assign addr_bank_inc[pt.ICCM_BITS-1 : 1] = iccm_rw_addr[pt.ICCM_BITS-1 : 1] + addr_incr[1:0];
for (genvar i=0; i<pt.ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
for (genvar i = 0; i < pt.ICCM_NUM_BANKS / 2; i++) begin : mem_bank_data
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
end
for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: mem_bank
for (genvar i = 0; i < pt.ICCM_NUM_BANKS; i++) begin : mem_bank
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[pt.ICCM_BANK_HI:2] == i) | (addr_bank_inc[pt.ICCM_BANK_HI:2] == i));
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[pt.ICCM_BANK_HI:2] == i) | (addr_bank_inc[pt.ICCM_BANK_HI:2] == i));
@ -108,9 +108,12 @@ import el2_pkg::*;
((addr_bank_inc[pt.ICCM_BANK_HI:2] == i) ?
addr_bank_inc[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO] :
iccm_rw_addr[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO]);
`ifdef VERILATOR
`ifdef VERILATOR
el2_ram #(.depth(1<<pt.ICCM_INDEX_BITS), .width(39)) iccm_bank (
el2_ram #(
.depth(1 << pt.ICCM_INDEX_BITS),
.width(39)
) iccm_bank (
// Primary ports
.ME(iccm_clken[i]),
.CLK(clk),
@ -118,22 +121,22 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
`else
`else
if (pt.ICCM_INDEX_BITS == 6 ) begin : iccm
if (pt.ICCM_INDEX_BITS == 6) begin : iccm
ram_64x39 iccm_bank (
// Primary ports
.CLK(clk),
@ -142,14 +145,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -166,14 +169,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -190,14 +193,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -213,14 +216,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -236,14 +239,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -259,14 +262,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -282,14 +285,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -305,14 +308,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -328,14 +331,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -351,14 +354,14 @@ import el2_pkg::*;
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
.ROP(),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.SD(iccm_ext_in_pkt[i].SD),
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
@ -374,15 +377,19 @@ import el2_pkg::*;
assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[0][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
((addr_bank_inc[pt.ICCM_BITS-1:2]== redundant_address[0][pt.ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
rvdff #(1) selred0 (.*,
.clk(active_clk),
.din(sel_red0[i]),
.dout(sel_red0_q[i]));
rvdff #(1) selred0 (
.*,
.clk (active_clk),
.din (sel_red0[i]),
.dout(sel_red0_q[i])
);
rvdff #(1) selred1 (.*,
.clk(active_clk),
.din(sel_red1[i]),
.dout(sel_red1_q[i]));
rvdff #(1) selred1 (
.*,
.clk (active_clk),
.din (sel_red1[i]),
.dout(sel_red1_q[i])
);
// muxing out the memory data with the redundant data if the address matches
@ -391,43 +398,53 @@ import el2_pkg::*;
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
end : mem_bank
// This section does the redundancy for tolerating single bit errors
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
// Also a LRU flop is kept to decide which of the redundant element to replace.
// This section does the redundancy for tolerating single bit errors
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
// Also a LRU flop is kept to decide which of the redundant element to replace.
assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[pt.ICCM_NUM_BANKS-1:0]) | (|sel_red1[pt.ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[pt.ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
.clk(active_clk),
.en(redundant_lru_en),
.din(redundant_lru_in),
.dout(redundant_lru));
rvdffs #() red_lru (
.*, // LRU flop for the redundant replacements
.clk (active_clk),
.en (redundant_lru_en),
.din (redundant_lru_in),
.dout(redundant_lru)
);
rvdffs #(pt.ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r0_addr_en),
.din(iccm_rw_addr[pt.ICCM_BITS-1:2]),
.dout(redundant_address[0][pt.ICCM_BITS-1:2]));
rvdffs #(pt.ICCM_BITS - 2) r0_address (
.*, // Redundant Row 0 address
.clk (active_clk),
.en (r0_addr_en),
.din (iccm_rw_addr[pt.ICCM_BITS-1:2]),
.dout(redundant_address[0][pt.ICCM_BITS-1:2])
);
rvdffs #(pt.ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r1_addr_en),
.din(iccm_rw_addr[pt.ICCM_BITS-1:2]),
.dout(redundant_address[1][pt.ICCM_BITS-1:2]));
rvdffs #(pt.ICCM_BITS - 2) r1_address (
.*, // Redundant Row 0 address
.clk (active_clk),
.en (r1_addr_en),
.din (iccm_rw_addr[pt.ICCM_BITS-1:2]),
.dout(redundant_address[1][pt.ICCM_BITS-1:2])
);
rvdffs #(1) r0_valid (.*,
.clk(active_clk), // Redundant Row 0 Valid
.en(r0_addr_en),
.din(1'b1),
.dout(redundant_valid[0]));
rvdffs #(1) r0_valid (
.*,
.clk (active_clk), // Redundant Row 0 Valid
.en (r0_addr_en),
.din (1'b1),
.dout(redundant_valid[0])
);
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
.clk(active_clk),
.en(r1_addr_en),
.din(1'b1),
.dout(redundant_valid[1]));
rvdffs #(1) r1_valid (
.*, // Redundant Row 1 Valid
.clk (active_clk),
.en (r1_addr_en),
.din (1'b1),
.dout(redundant_valid[1])
);
@ -440,30 +457,52 @@ import el2_pkg::*;
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data0_en),
.din(redundant_data0_in[38:0]),
.dout(redundant_data[0][38:0]));
rvdffs #(39) r0_data (
.*, // Redundant Row 1 data
.clk (active_clk),
.en (redundant_data0_en),
.din (redundant_data0_in[38:0]),
.dout(redundant_data[0][38:0])
);
assign redundant_data1_en = ((iccm_rw_addr[pt.ICCM_BITS-1:3] == redundant_address[1][pt.ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
(redundant_lru & iccm_buf_correct_ecc);
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data1_en),
.din(redundant_data1_in[38:0]),
.dout(redundant_data[1][38:0]));
rvdffs #(39) r1_data (
.*, // Redundant Row 1 data
.clk (active_clk),
.en (redundant_data1_en),
.din (redundant_data1_in[38:0]),
.dout(redundant_data[1][38:0])
);
rvdffs #(pt.ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [pt.ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
rvdffs #(pt.ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[pt.ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[pt.ICCM_BANK_HI:2]), .en(1'b1));
rvdffs #(pt.ICCM_BANK_HI) rd_addr_lo_ff (
.*,
.clk (active_clk),
.din (iccm_rw_addr[pt.ICCM_BANK_HI:1]),
.dout(iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:1]),
.en (1'b1)
); // bit 0 of address is always 0
rvdffs #(pt.ICCM_BANK_BITS) rd_addr_hi_ff (
.*,
.clk (active_clk),
.din (addr_bank_inc[pt.ICCM_BANK_HI:2]),
.dout(iccm_rd_addr_hi_q[pt.ICCM_BANK_HI:2]),
.en (1'b1)
);
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][31:0]};
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
assign iccm_rd_data_pre[63:0] = {
iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0],
iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][31:0]
};
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16 * iccm_rd_addr_lo_q[1]))});
assign iccm_rd_data[63:0] = {iccm_data[63:0]};
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][38:0]};
assign iccm_rd_data_ecc[77:0] = {
iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0],
iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][38:0]
};
endmodule // el2_ifu_iccm_mem

125
Flow/design/ifu/el2_ifu_ifc_ctl.sv
View File

@ -21,11 +21,10 @@
//********************************************************************************
module el2_ifu_ifc_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
@ -49,7 +48,7 @@ import el2_pkg::*;
input logic ic_write_stall, // IC is writing, stop fetching
input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
input logic [31:0] dec_tlu_mrac_ff , // side_effect and cacheable for each region
input logic [31:0] dec_tlu_mrac_ff, // side_effect and cacheable for each region
output logic [31:1] ifc_fetch_addr_f, // fetch addr F
output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
@ -67,7 +66,7 @@ import el2_pkg::*;
output logic ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
);
);
logic [31:1] fetch_addr_bf;
logic [31:1] fetch_addr_next;
@ -84,12 +83,14 @@ import el2_pkg::*;
logic fetch_addr_next_1;
// FSM assignment
typedef enum logic [1:0] { IDLE = 2'b00 ,
FETCH = 2'b01 ,
STALL = 2'b10 ,
WFM = 2'b11 } state_t ;
state_t state ;
state_t next_state ;
typedef enum logic [1:0] {
IDLE = 2'b00,
FETCH = 2'b01,
STALL = 2'b10,
WFM = 2'b11
} state_t;
state_t state;
state_t next_state;
logic dma_stall;
assign dma_stall = ic_dma_active | dma_iccm_stall_any_f;
@ -101,7 +102,7 @@ import el2_pkg::*;
// - Miss *or* flush during WFM (icache miss buffer is blocking)
// - Sequential
if(pt.BTB_ENABLE==1) begin
if (pt.BTB_ENABLE == 1) begin
logic sel_btb_addr_bf;
assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
@ -111,11 +112,11 @@ if(pt.BTB_ENABLE==1) begin
assign fetch_addr_bf[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) | // FLUSH path
({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path
({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]})| // BTB target
({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]}) | // BTB target
({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
end // if (pt.BTB_ENABLE=1)
end // if (pt.BTB_ENABLE=1)
else begin
assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
assign sel_next_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ic_hit_f;
@ -125,8 +126,8 @@ end // if (pt.BTB_ENABLE=1)
({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path
({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
end
assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 31'b1), fetch_addr_next_1 };
end
assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 31'b1), fetch_addr_next_1};
assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);
assign fetch_addr_next_1 = line_wrap ? 1'b0 : ifc_fetch_addr_f[1];
@ -151,23 +152,23 @@ end
// If we're in IDLE, and we get a flush, goto FETCH
assign leave_idle = exu_flush_final & ~dec_tlu_flush_noredir_wb & idle;
//.i 7
//.o 2
//.ilb state[1] state[0] reset_delayed miss_f mb_empty_mod goto_idle leave_idle
//.ob next_state[1] next_state[0]
//.type fr
//
//# fetch 01, stall 10, wfm 11, idle 00
//-- 1---- 01
//-- 0--1- 00
//00 0--00 00
//00 0--01 01
//
//01 01-0- 11
//01 00-0- 01
//
//11 0-10- 01
//11 0-00- 11
//.i 7
//.o 2
//.ilb state[1] state[0] reset_delayed miss_f mb_empty_mod goto_idle leave_idle
//.ob next_state[1] next_state[0]
//.type fr
//
//# fetch 01, stall 10, wfm 11, idle 00
//-- 1---- 01
//-- 0--1- 00
//00 0--00 00
//00 0--01 01
//
//01 01-0- 11
//01 00-0- 01
//
//11 0-10- 01
//11 0-00- 11
assign next_state[1] = (~state[1] & state[0] & miss_f & ~goto_idle) |
(state[1] & ~mb_empty_mod & ~goto_idle);
@ -185,7 +186,7 @@ end
assign fb_left = ifc_fetch_req_f & ~(ifu_fb_consume1 | ifu_fb_consume2) & ~miss_f;
// CBH
// CBH
assign fb_write_ns[3:0] = ( ({4{(flush_fb)}} & 4'b0001) |
({4{~flush_fb & fb_right }} & {1'b0, fb_write_f[3:1]}) |
({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f[3:2]}) |
@ -195,12 +196,22 @@ end
assign fb_full_f_ns = fb_write_ns[3];
assign idle = state == IDLE ;
assign wfm = state == WFM ;
assign idle = state == IDLE;
assign wfm = state == WFM;
rvdffie #(10) fbwrite_ff (.*, .clk(free_l2clk),
.din( {dma_iccm_stall_any, miss_f, ifc_fetch_req_bf, next_state[1:0], fb_full_f_ns, fb_write_ns[3:0]}),
.dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]}));
rvdffie #(10) fbwrite_ff (
.*,
.clk(free_l2clk),
.din({
dma_iccm_stall_any,
miss_f,
ifc_fetch_req_bf,
next_state[1:0],
fb_full_f_ns,
fb_write_ns[3:0]
}),
.dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]})
);
assign ifu_pmu_fetch_stall = wfm |
(ifc_fetch_req_bf_raw &
@ -211,20 +222,27 @@ end
assign ifc_fetch_addr_bf[31:1] = fetch_addr_bf[31:1];
rvdffpcie #(31) faddrf1_ff (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f[31:1]));
rvdffpcie #(31) faddrf1_ff (
.*,
.en (fetch_bf_en),
.din (fetch_addr_bf[31:1]),
.dout(ifc_fetch_addr_f[31:1])
);
if (pt.ICCM_ENABLE) begin
logic iccm_acc_in_region_bf;
logic iccm_acc_in_range_bf;
rvrangecheck #( .CCM_SADR (pt.ICCM_SADR),
.CCM_SIZE (pt.ICCM_SIZE) ) iccm_rangecheck (
.addr ({ifc_fetch_addr_bf[31:1],1'b0}) ,
.in_range (iccm_acc_in_range_bf) ,
rvrangecheck #(
.CCM_SADR(pt.ICCM_SADR),
.CCM_SIZE(pt.ICCM_SIZE)
) iccm_rangecheck (
.addr ({ifc_fetch_addr_bf[31:1], 1'b0}),
.in_range (iccm_acc_in_range_bf),
.in_region(iccm_acc_in_region_bf)
);
assign ifc_iccm_access_bf = iccm_acc_in_range_bf ;
assign ifc_iccm_access_bf = iccm_acc_in_range_bf;
assign ifc_dma_access_ok = ( (~ifc_iccm_access_bf |
(fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1)) |
@ -232,15 +250,16 @@ end
idle ) & ~exu_flush_final) |
dma_iccm_stall_any_f;
assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf ;
end
else begin
assign ifc_iccm_access_bf = 1'b0 ;
assign ifc_dma_access_ok = 1'b0 ;
assign ifc_region_acc_fault_bf = 1'b0 ;
assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf;
end else begin
assign ifc_iccm_access_bf = 1'b0;
assign ifc_dma_access_ok = 1'b0;
assign ifc_region_acc_fault_bf = 1'b0;
end
assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{ifc_fetch_addr_bf[31:28] , 1'b0 }] ; // bit 0 of each region description is the cacheable bit
assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{
ifc_fetch_addr_bf[31:28], 1'b0
}]; // bit 0 of each region description is the cacheable bit
endmodule // el2_ifu_ifc_ctl

1308
Flow/design/ifu/el2_ifu_mem_ctl.sv
View File

File diff suppressed because it is too large Load Diff

25
Flow/design/ifu/el2_ifu_tb_memread.sv
View File

@ -38,24 +38,24 @@ module el2_ifu_tb_memread;
integer i;
initial begin
clk=0;
rst_l=0;
clk = 0;
rst_l = 0;
// initialize the reads and populate the instruction arrays
$readmemh ("left64k", compressed );
$readmemh ("right64k", expected );
$readmemh("left64k", compressed);
$readmemh("right64k", expected);
$dumpfile ("top.vcd");
$dumpfile("top.vcd");
$dumpvars;
$dumpon;
end
always #50 clk =~clk;
always #50 clk = ~clk;
always @(posedge clk) begin
clk_count = clk_count +1;
if (clk_count>=1 & clk_count<=3) rst_l <= 1'b0;
clk_count = clk_count + 1;
if (clk_count >= 1 & clk_count <= 3) rst_l <= 1'b0;
else rst_l <= 1'b1;
if (clk_count > 3) begin
@ -73,12 +73,17 @@ module el2_ifu_tb_memread;
always @(negedge clk) begin
if (clk_count > 3 & error) begin
$display("clock: %d compressed %h error actual %h expected %h",clk_count,compressed_din,actual,expected_val);
$display("clock: %d compressed %h error actual %h expected %h", clk_count, compressed_din,
actual, expected_val);
end
end
el2_ifu_compress_ctl align (.*,.din(compressed_din[15:0]),.dout(actual[31:0]));
el2_ifu_compress_ctl align (
.*,
.din (compressed_din[15:0]),
.dout(actual[31:0])
);
assign error = actual[31:0] != expected_val[31:0];

52
Flow/design/include/el2_def.sv
View File

@ -3,7 +3,7 @@
//`define EL2_DEF_SV
package el2_pkg;
typedef struct packed {
typedef struct packed {
logic trace_rv_i_valid_ip;
logic [31:0] trace_rv_i_insn_ip;
logic [31:0] trace_rv_i_address_ip;
@ -14,7 +14,7 @@ typedef struct packed {
} el2_trace_pkt_t;
typedef enum logic [3:0] {
typedef enum logic [3:0] {
NULL = 4'b0000,
MUL = 4'b0001,
LOAD = 4'b0010,
@ -33,19 +33,19 @@ typedef enum logic [3:0] {
BITMANIPU = 4'b1111
} el2_inst_pkt_t;
typedef struct packed {
typedef struct packed {
logic valid;
logic wb;
logic [2:0] tag;
logic [4:0] rd;
} el2_load_cam_pkt_t;
typedef struct packed {
typedef struct packed {
logic pc0_call;
logic pc0_ret;
logic pc0_pc4;
} el2_rets_pkt_t;
typedef struct packed {
typedef struct packed {
logic valid;
logic [11:0] toffset;
logic [1:0] hist;
@ -57,7 +57,7 @@ typedef struct packed {
logic ret;
} el2_br_pkt_t;
typedef struct packed {
typedef struct packed {
logic valid;
logic [1:0] hist;
logic br_error;
@ -66,7 +66,7 @@ typedef struct packed {
logic middle;
} el2_br_tlu_pkt_t;
typedef struct packed {
typedef struct packed {
logic misp;
logic ataken;
logic boffset;
@ -84,7 +84,7 @@ typedef struct packed {
logic [31:1] prett;
} el2_predict_pkt_t;
typedef struct packed {
typedef struct packed {
// unlikely to change
logic icaf;
logic icaf_second;
@ -99,7 +99,7 @@ typedef struct packed {
el2_inst_pkt_t pmu_i0_itype; // pmu - instruction type
} el2_trap_pkt_t;
typedef struct packed {
typedef struct packed {
// unlikely to change
logic i0div;
logic csrwen;
@ -113,20 +113,20 @@ typedef struct packed {
logic i0valid;
} el2_dest_pkt_t;
typedef struct packed {
typedef struct packed {
logic mul;
logic load;
logic alu;
} el2_class_pkt_t;
typedef struct packed {
typedef struct packed {
logic [4:0] rs1;
logic [4:0] rs2;
logic [4:0] rd;
} el2_reg_pkt_t;
typedef struct packed {
typedef struct packed {
logic clz;
logic ctz;
logic cpop;
@ -171,11 +171,11 @@ typedef struct packed {
logic csr_imm;
} el2_alu_pkt_t;
typedef struct packed {
typedef struct packed {
logic fast_int;
/* verilator lint_off SYMRSVDWORD */
/* verilator lint_off SYMRSVDWORD */
logic stack;
/* verilator lint_on SYMRSVDWORD */
/* verilator lint_on SYMRSVDWORD */
logic by;
logic half;
logic word;
@ -190,7 +190,7 @@ typedef struct packed {
logic valid;
} el2_lsu_pkt_t;
typedef struct packed {
typedef struct packed {
logic inst_type; //0: Load, 1: Store
//logic dma_valid;
logic exc_type; //0: MisAligned, 1: Access Fault
@ -200,7 +200,7 @@ typedef struct packed {
logic exc_valid;
} el2_lsu_error_pkt_t;
typedef struct packed {
typedef struct packed {
logic clz;
logic ctz;
logic cpop;
@ -300,7 +300,7 @@ typedef struct packed {
} el2_dec_pkt_t;
typedef struct packed {
typedef struct packed {
logic valid;
logic rs1_sign;
logic rs2_sign;
@ -326,13 +326,13 @@ typedef struct packed {
logic xperm_h;
} el2_mul_pkt_t;
typedef struct packed {
typedef struct packed {
logic valid;
logic unsign;
logic rem;
} el2_div_pkt_t;
typedef struct packed {
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
@ -345,7 +345,7 @@ typedef struct packed {
logic BC2;
} el2_ccm_ext_in_pkt_t;
typedef struct packed {
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
@ -358,7 +358,7 @@ typedef struct packed {
} el2_dccm_ext_in_pkt_t;
typedef struct packed {
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
@ -371,7 +371,7 @@ typedef struct packed {
} el2_ic_data_ext_in_pkt_t;
typedef struct packed {
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
@ -385,7 +385,7 @@ typedef struct packed {
typedef struct packed {
typedef struct packed {
logic select;
logic match;
logic store;
@ -396,12 +396,12 @@ typedef struct packed {
} el2_trigger_pkt_t;
typedef struct packed {
typedef struct packed {
logic [70:0] icache_wrdata; // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
logic [16:0] icache_dicawics; // Arraysel:24, Waysel:21:20, Index:16:3
logic icache_rd_valid;
logic icache_wr_valid;
} el2_cache_debug_pkt_t;
//`endif
//`endif
endpackage // el2_pkg

262
Flow/design/lib/ahb_to_axi4.sv
View File

@ -21,7 +21,7 @@
//
//********************************************************************************
module ahb_to_axi4
import el2_pkg::*;
import el2_pkg::*;
#(
TAG = 1,
`include "el2_param.vh"
@ -39,46 +39,46 @@ import el2_pkg::*;
output logic axi_awvalid,
input logic axi_awready,
output logic [TAG-1:0] axi_awid,
output logic [31:0] axi_awaddr,
output logic [2:0] axi_awsize,
output logic [2:0] axi_awprot,
output logic [7:0] axi_awlen,
output logic [1:0] axi_awburst,
output logic [ 31:0] axi_awaddr,
output logic [ 2:0] axi_awsize,
output logic [ 2:0] axi_awprot,
output logic [ 7:0] axi_awlen,
output logic [ 1:0] axi_awburst,
output logic axi_wvalid,
input logic axi_wready,
output logic [63:0] axi_wdata,
output logic [7:0] axi_wstrb,
output logic [ 7:0] axi_wstrb,
output logic axi_wlast,
input logic axi_bvalid,
output logic axi_bready,
input logic [1:0] axi_bresp,
input logic [ 1:0] axi_bresp,
input logic [TAG-1:0] axi_bid,
// AXI Read Channels
output logic axi_arvalid,
input logic axi_arready,
output logic [TAG-1:0] axi_arid,
output logic [31:0] axi_araddr,
output logic [2:0] axi_arsize,
output logic [2:0] axi_arprot,
output logic [7:0] axi_arlen,
output logic [1:0] axi_arburst,
output logic [ 31:0] axi_araddr,
output logic [ 2:0] axi_arsize,
output logic [ 2:0] axi_arprot,
output logic [ 7:0] axi_arlen,
output logic [ 1:0] axi_arburst,
input logic axi_rvalid,
output logic axi_rready,
input logic [TAG-1:0] axi_rid,
input logic [63:0] axi_rdata,
input logic [1:0] axi_rresp,
input logic [ 63:0] axi_rdata,
input logic [ 1:0] axi_rresp,
// AHB-Lite signals
input logic [31:0] ahb_haddr, // ahb bus address
input logic [2:0] ahb_hburst, // tied to 0
input logic [ 2:0] ahb_hburst, // tied to 0
input logic ahb_hmastlock, // tied to 0
input logic [3:0] ahb_hprot, // tied to 4'b0011
input logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
input logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
input logic [ 3:0] ahb_hprot, // tied to 4'b0011
input logic [ 2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
input logic [ 1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
input logic ahb_hwrite, // ahb bus write
input logic [63:0] ahb_hwdata, // ahb bus write data
input logic ahb_hsel, // this slave was selected
@ -92,7 +92,8 @@ import el2_pkg::*;
logic [7:0] master_wstrb;
typedef enum logic [1:0] { IDLE = 2'b00, // Nothing in the buffer. No commands yet recieved
typedef enum logic [1:0] {
IDLE = 2'b00, // Nothing in the buffer. No commands yet recieved
WR = 2'b01, // Write Command recieved
RD = 2'b10, // Read Command recieved
PEND = 2'b11 // Waiting on Read Data from core
@ -107,7 +108,7 @@ import el2_pkg::*;
logic ahb_hready;
logic ahb_hready_q;
logic [1:0] ahb_htrans_in, ahb_htrans_q;
logic [2:0] ahb_hsize_q;
logic [ 2:0] ahb_hsize_q;
logic ahb_hwrite_q;
logic [31:0] ahb_haddr_q;
logic [63:0] ahb_hwdata_q;
@ -125,12 +126,12 @@ import el2_pkg::*;
logic cmdbuf_wr_en, cmdbuf_rst;
logic cmdbuf_full;
logic cmdbuf_vld, cmdbuf_write;
logic [1:0] cmdbuf_size;
logic [7:0] cmdbuf_wstrb;
logic [ 1:0] cmdbuf_size;
logic [ 7:0] cmdbuf_wstrb;
logic [31:0] cmdbuf_addr;
logic [63:0] cmdbuf_wdata;
// FSM to control the bus states and when to block the hready and load the command buffer
// FSM to control the bus states and when to block the hready and load the command buffer
always_comb begin
buf_nxtstate = IDLE;
buf_state_en = 1'b0;
@ -144,11 +145,11 @@ import el2_pkg::*;
end
WR: begin // Write command recieved last cycle
buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite ? WR : RD;
buf_state_en = (~cmdbuf_full | ahb_hresp) ;
buf_state_en = (~cmdbuf_full | ahb_hresp);
cmdbuf_wr_en = ~cmdbuf_full & ~(ahb_hresp | ((ahb_htrans[1:0] == 2'b01) & ahb_hsel)); // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
end
RD: begin // Read command recieved last cycle.
buf_nxtstate = ahb_hresp ? IDLE :PEND; // If error go to idle, else wait for read data
buf_nxtstate = ahb_hresp ? IDLE : PEND; // If error go to idle, else wait for read data
buf_state_en = (~cmdbuf_full | ahb_hresp); // only when command can go, or if its an error
cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full; // send command only when no error
end
@ -161,7 +162,17 @@ import el2_pkg::*;
endcase
end // always_comb begin
rvdffs_fpga #($bits(state_t)) state_reg (.*, .din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk));
rvdffs_fpga #($bits(
state_t
)) state_reg (
.*,
.din(buf_nxtstate),
.dout({buf_state}),
.en(buf_state_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk)
);
assign master_wstrb[7:0] = ({8{ahb_hsize_q[2:0] == 3'b0}} & (8'b1 << ahb_haddr_q[2:0])) |
({8{ahb_hsize_q[2:0] == 3'b1}} & (8'b11 << ahb_haddr_q[2:0])) |
@ -186,41 +197,119 @@ import el2_pkg::*;
(ahb_hresp_q & ~ahb_hready_q);
// Buffer signals - needed for the read data and ECC error response
rvdff_fpga #(.WIDTH(64)) buf_rdata_ff (.din(axi_rdata[63:0]), .dout(buf_rdata[63:0]), .clk(buf_rdata_clk), .clken(buf_rdata_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) buf_read_error_ff(.din(buf_read_error_in), .dout(buf_read_error), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*); // buf_read_error will be high only one cycle
rvdff_fpga #(
.WIDTH(64)
) buf_rdata_ff (
.din(axi_rdata[63:0]),
.dout(buf_rdata[63:0]),
.clk(buf_rdata_clk),
.clken(buf_rdata_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(1)
) buf_read_error_ff (
.din(buf_read_error_in),
.dout(buf_read_error),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
); // buf_read_error will be high only one cycle
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans_in[1:0]), .dout(ahb_htrans_q[1:0]), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(3)) hsize_ff (.din(ahb_hsize[2:0]), .dout(ahb_hsize_q[2:0]), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(32)) haddr_ff (.din(ahb_haddr[31:0]), .dout(ahb_haddr_q[31:0]), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);
rvdff_fpga #(
.WIDTH(1)
) hresp_ff (
.din(ahb_hresp),
.dout(ahb_hresp_q),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(1)
) hready_ff (
.din(ahb_hready),
.dout(ahb_hready_q),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(2)
) htrans_ff (
.din(ahb_htrans_in[1:0]),
.dout(ahb_htrans_q[1:0]),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(3)
) hsize_ff (
.din(ahb_hsize[2:0]),
.dout(ahb_hsize_q[2:0]),
.clk(ahb_addr_clk),
.clken(ahb_addr_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(1)
) hwrite_ff (
.din(ahb_hwrite),
.dout(ahb_hwrite_q),
.clk(ahb_addr_clk),
.clken(ahb_addr_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(32)
) haddr_ff (
.din(ahb_haddr[31:0]),
.dout(ahb_haddr_q[31:0]),
.clk(ahb_addr_clk),
.clken(ahb_addr_clk_en),
.rawclk(clk),
.*
);
// Address check dccm
rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)) addr_dccm_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)
) addr_dccm_rangecheck (
.addr(ahb_haddr_q[31:0]),
.in_range(ahb_addr_in_dccm),
.in_region(ahb_addr_in_dccm_region_nc)
);
// Address check iccm
if (pt.ICCM_ENABLE == 1) begin: GenICCM
rvrangecheck #(.CCM_SADR(pt.ICCM_SADR),
.CCM_SIZE(pt.ICCM_SIZE)) addr_iccm_rangecheck (
if (pt.ICCM_ENABLE == 1) begin : GenICCM
rvrangecheck #(
.CCM_SADR(pt.ICCM_SADR),
.CCM_SIZE(pt.ICCM_SIZE)
) addr_iccm_rangecheck (
.addr(ahb_haddr_q[31:0]),
.in_range(ahb_addr_in_iccm),
.in_region(ahb_addr_in_iccm_region_nc)
);
end else begin: GenNoICCM
end else begin : GenNoICCM
assign ahb_addr_in_iccm = '0;
assign ahb_addr_in_iccm_region_nc = '0;
end
// PIC memory address check
rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)) addr_pic_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)
) addr_pic_rangecheck (
.addr(ahb_haddr_q[31:0]),
.in_range(ahb_addr_in_pic),
.in_region(ahb_addr_in_pic_region_nc)
@ -230,12 +319,69 @@ import el2_pkg::*;
assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write);
assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)));
rvdffsc_fpga #(.WIDTH(1)) cmdbuf_vldff (.din(1'b1), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clear(cmdbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(1)) cmdbuf_writeff (.din(ahb_hwrite_q), .dout(cmdbuf_write), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(2)) cmdbuf_sizeff (.din(ahb_hsize_q[1:0]), .dout(cmdbuf_size[1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(8)) cmdbuf_wstrbff (.din(master_wstrb[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .clk(clk), .*);
rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en & bus_clk_en), .clk(clk), .*);
rvdffsc_fpga #(
.WIDTH(1)
) cmdbuf_vldff (
.din(1'b1),
.dout(cmdbuf_vld),
.en(cmdbuf_wr_en),
.clear(cmdbuf_rst),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(1)
) cmdbuf_writeff (
.din(ahb_hwrite_q),
.dout(cmdbuf_write),
.en(cmdbuf_wr_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(2)
) cmdbuf_sizeff (
.din(ahb_hsize_q[1:0]),
.dout(cmdbuf_size[1:0]),
.en(cmdbuf_wr_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(8)
) cmdbuf_wstrbff (
.din(master_wstrb[7:0]),
.dout(cmdbuf_wstrb[7:0]),
.en(cmdbuf_wr_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(32)
) cmdbuf_addrff (
.din (ahb_haddr_q[31:0]),
.dout(cmdbuf_addr[31:0]),
.en (cmdbuf_wr_en & bus_clk_en),
.clk (clk),
.*
);
rvdffe #(
.WIDTH(64)
) cmdbuf_wdataff (
.din (ahb_hwdata[63:0]),
.dout(cmdbuf_wdata[63:0]),
.en (cmdbuf_wr_en & bus_clk_en),
.clk (clk),
.*
);
// AXI Write Command Channel
assign axi_awvalid = cmdbuf_vld & cmdbuf_write;
@ -267,8 +413,20 @@ import el2_pkg::*;
assign ahb_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);
assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
rvclkhdr ahb_addr_cgc (.en(ahb_addr_clk_en), .l1clk(ahb_addr_clk), .*);
rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*);
rvclkhdr bus_cgc (
.en(bus_clk_en),
.l1clk(bus_clk),
.*
);
rvclkhdr ahb_addr_cgc (
.en(ahb_addr_clk_en),
.l1clk(ahb_addr_clk),
.*
);
rvclkhdr buf_rdata_cgc (
.en(buf_rdata_clk_en),
.l1clk(buf_rdata_clk),
.*
);
endmodule // ahb_to_axi4

463
Flow/design/lib/axi4_to_ahb.sv
View File

@ -22,10 +22,11 @@
//
//********************************************************************************
module axi4_to_ahb
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
,parameter TAG = 1) (
`include "el2_param.vh",
parameter TAG = 1
) (
input clk,
input free_clk,
@ -40,43 +41,43 @@ import el2_pkg::*;
input logic axi_awvalid,
output logic axi_awready,
input logic [TAG-1:0] axi_awid,
input logic [31:0] axi_awaddr,
input logic [2:0] axi_awsize,
input logic [2:0] axi_awprot,
input logic [ 31:0] axi_awaddr,
input logic [ 2:0] axi_awsize,
input logic [ 2:0] axi_awprot,
input logic axi_wvalid,
output logic axi_wready,
input logic [63:0] axi_wdata,
input logic [7:0] axi_wstrb,
input logic [ 7:0] axi_wstrb,
input logic axi_wlast,
output logic axi_bvalid,
input logic axi_bready,
output logic [1:0] axi_bresp,
output logic [ 1:0] axi_bresp,
output logic [TAG-1:0] axi_bid,
// AXI Read Channels
input logic axi_arvalid,
output logic axi_arready,
input logic [TAG-1:0] axi_arid,
input logic [31:0] axi_araddr,
input logic [2:0] axi_arsize,
input logic [2:0] axi_arprot,
input logic [ 31:0] axi_araddr,
input logic [ 2:0] axi_arsize,
input logic [ 2:0] axi_arprot,
output logic axi_rvalid,
input logic axi_rready,
output logic [TAG-1:0] axi_rid,
output logic [63:0] axi_rdata,
output logic [1:0] axi_rresp,
output logic [ 63:0] axi_rdata,
output logic [ 1:0] axi_rresp,
output logic axi_rlast,
// AHB-Lite signals
output logic [31:0] ahb_haddr, // ahb bus address
output logic [2:0] ahb_hburst, // tied to 0
output logic [ 2:0] ahb_hburst, // tied to 0
output logic ahb_hmastlock, // tied to 0
output logic [3:0] ahb_hprot, // tied to 4'b0011
output logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
output logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
output logic [ 3:0] ahb_hprot, // tied to 4'b0011
output logic [ 2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
output logic [ 1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
output logic ahb_hwrite, // ahb bus write
output logic [63:0] ahb_hwdata, // ahb bus write data
@ -88,52 +89,61 @@ import el2_pkg::*;
localparam ID = 1;
localparam PRTY = 1;
typedef enum logic [2:0] {IDLE=3'b000, CMD_RD=3'b001, CMD_WR=3'b010, DATA_RD=3'b011, DATA_WR=3'b100, DONE=3'b101, STREAM_RD=3'b110, STREAM_ERR_RD=3'b111} state_t;
typedef enum logic [2:0] {
IDLE = 3'b000,
CMD_RD = 3'b001,
CMD_WR = 3'b010,
DATA_RD = 3'b011,
DATA_WR = 3'b100,
DONE = 3'b101,
STREAM_RD = 3'b110,
STREAM_ERR_RD = 3'b111
} state_t;
state_t buf_state, buf_nxtstate;
logic slave_valid;
logic slave_ready;
logic [TAG-1:0] slave_tag;
logic [63:0] slave_rdata;
logic [3:0] slave_opc;
logic [ 63:0] slave_rdata;
logic [ 3:0] slave_opc;
logic wrbuf_en, wrbuf_data_en;
logic wrbuf_cmd_sent, wrbuf_rst;
logic wrbuf_vld;
logic wrbuf_data_vld;
logic [TAG-1:0] wrbuf_tag;
logic [2:0] wrbuf_size;
logic [31:0] wrbuf_addr;
logic [63:0] wrbuf_data;
logic [7:0] wrbuf_byteen;
logic [ 2:0] wrbuf_size;
logic [ 31:0] wrbuf_addr;
logic [ 63:0] wrbuf_data;
logic [ 7:0] wrbuf_byteen;
logic master_valid;
logic master_ready;
logic [TAG-1:0] master_tag;
logic [31:0] master_addr;
logic [63:0] master_wdata;
logic [2:0] master_size;
logic [2:0] master_opc;
logic [7:0] master_byteen;
logic [ 31:0] master_addr;
logic [ 63:0] master_wdata;
logic [ 2:0] master_size;
logic [ 2:0] master_opc;
logic [ 7:0] master_byteen;
// Buffer signals (one entry buffer)
logic [31:0] buf_addr;
logic [1:0] buf_size;
logic [ 31:0] buf_addr;
logic [ 1:0] buf_size;
logic buf_write;
logic [7:0] buf_byteen;
logic [ 7:0] buf_byteen;
logic buf_aligned;
logic [63:0] buf_data;
logic [ 63:0] buf_data;
logic [TAG-1:0] buf_tag;
//Miscellaneous signals
logic buf_rst;
logic [TAG-1:0] buf_tag_in;
logic [31:0] buf_addr_in;
logic [7:0] buf_byteen_in;
logic [63:0] buf_data_in;
logic [ 31:0] buf_addr_in;
logic [ 7:0] buf_byteen_in;
logic [ 63:0] buf_data_in;
logic buf_write_in;
logic buf_aligned_in;
logic [2:0] buf_size_in;
logic [ 2:0] buf_size_in;
logic buf_state_en;
logic buf_wr_en;
@ -150,9 +160,9 @@ import el2_pkg::*;
logic slave_valid_pre;
logic ahb_hready_q;
logic ahb_hresp_q;
logic [1:0] ahb_htrans_q;
logic [ 1:0] ahb_htrans_q;
logic ahb_hwrite_q;
logic [63:0] ahb_hrdata_q;
logic [ 63:0] ahb_hrdata_q;
logic slvbuf_write;
@ -165,7 +175,7 @@ import el2_pkg::*;
logic rd_bypass_idle;
logic last_addr_en;
logic [31:0] last_bus_addr;
logic [ 31:0] last_bus_addr;
// Clocks
logic buf_clken;
@ -205,16 +215,17 @@ import el2_pkg::*;
endfunction // get_write_addr
// Function to get the next byte pointer
function automatic logic [2:0] get_nxtbyte_ptr (logic [2:0] current_byte_ptr, logic [7:0] byteen, logic get_next);
function automatic logic [2:0] get_nxtbyte_ptr(logic [2:0] current_byte_ptr, logic [7:0] byteen,
logic get_next);
logic [2:0] start_ptr;
logic found;
found = '0;
//get_nxtbyte_ptr[2:0] = current_byte_ptr[2:0];
start_ptr[2:0] = get_next ? (current_byte_ptr[2:0] + 3'b1) : current_byte_ptr[2:0];
for (int j=0; j<8; j++) begin
for (int j = 0; j < 8; j++) begin
if (~found) begin
get_nxtbyte_ptr[2:0] = 3'(j);
found |= (byteen[j] & (3'(j) >= start_ptr[2:0])) ;
found |= (byteen[j] & (3'(j) >= start_ptr[2:0]));
end
end
endfunction // get_nextbyte_ptr
@ -222,7 +233,14 @@ import el2_pkg::*;
// Create bus synchronized version of force halt
assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;
assign dec_tlu_force_halt_bus_ns = ~bus_clk_en & dec_tlu_force_halt_bus;
rvdff #(.WIDTH(1)) force_halt_busff(.din(dec_tlu_force_halt_bus_ns), .dout(dec_tlu_force_halt_bus_q), .clk(free_clk), .*);
rvdff #(
.WIDTH(1)
) force_halt_busff (
.din (dec_tlu_force_halt_bus_ns),
.dout(dec_tlu_force_halt_bus_q),
.clk (free_clk),
.*
);
// Write buffer
assign wrbuf_en = axi_awvalid & axi_awready & master_ready;
@ -284,13 +302,14 @@ import el2_pkg::*;
buf_wr_en = buf_state_en;
buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
buf_cmd_byte_ptr_en = buf_state_en;
buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0, buf_byteen_in[7:0], 1'b0) :
master_addr[2:0];
bypass_en = buf_state_en;
rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD);
ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
end
CMD_RD: begin
buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000)) ? STREAM_RD : DATA_RD;
buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;
cmd_done = buf_state_en & ~master_valid;
slvbuf_wr_en = buf_state_en;
@ -327,8 +346,8 @@ import el2_pkg::*;
buf_nxtstate = DONE;
buf_state_en = (ahb_hready_q | ahb_hresp_q);
buf_data_wr_en = buf_state_en;
slvbuf_error_in= ahb_hresp_q;
slvbuf_error_en= buf_state_en;
slvbuf_error_in = ahb_hresp_q;
slvbuf_error_en = buf_state_en;
slvbuf_wr_en = buf_state_en;
end
@ -338,9 +357,11 @@ import el2_pkg::*;
buf_state_en = trxn_done;
buf_cmd_byte_ptr_en = buf_state_en;
slvbuf_wr_en = buf_state_en;
buf_cmd_byte_ptr = trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
buf_cmd_byte_ptr = trxn_done ?
get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1) : buf_cmd_byte_ptrQ;
cmd_done = trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ == 3'b111) |
(buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0));
(buf_byteen[get_nxtbyte_ptr(
buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1)] == 1'b0));
ahb_htrans[1:0] = {2{~(cmd_done | cmd_doneQ)}} & 2'b10;
end
DATA_WR: begin
@ -356,15 +377,16 @@ import el2_pkg::*;
buf_data_wr_en = buf_wr_en;
cmd_done = (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) &
((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0))));
((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(
buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1)] == 1'b0))));
bypass_en = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR); // Only bypass for writes for the time being
ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10;
slave_valid_pre = buf_state_en & (buf_nxtstate != DONE);
trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
buf_cmd_byte_ptr_en = trxn_done | bypass_en;
buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :
trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0, buf_byteen_in[7:0], 1'b0) : trxn_done ?
get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1) : buf_cmd_byte_ptrQ;
end
DONE: begin
buf_nxtstate = IDLE;
@ -378,11 +400,15 @@ import el2_pkg::*;
assign buf_rst = dec_tlu_force_halt_bus;
assign cmd_done_rst = slave_valid_pre;
assign buf_addr_in[31:3] = master_addr[31:3];
assign buf_addr_in[2:0] = (buf_aligned_in & (master_opc[2:1] == 2'b01)) ? get_write_addr(master_byteen[7:0]) : master_addr[2:0];
assign buf_addr_in[2:0] = (buf_aligned_in & (master_opc[2:1] == 2'b01)) ? get_write_addr(
master_byteen[7:0]
) : master_addr[2:0];
assign buf_tag_in[TAG-1:0] = master_tag[TAG-1:0];
assign buf_byteen_in[7:0] = wrbuf_byteen[7:0];
assign buf_data_in[63:0] = (buf_state == DATA_RD) ? ahb_hrdata_q[63:0] : master_wdata[63:0];
assign buf_size_in[1:0] = (buf_aligned_in & (master_size[1:0] == 2'b11) & (master_opc[2:1] == 2'b01)) ? get_write_size(master_byteen[7:0]) : master_size[1:0];
assign buf_size_in[1:0] = (buf_aligned_in & (master_size[1:0] == 2'b11) & (master_opc[2:1] == 2'b01)) ? get_write_size(
master_byteen[7:0]
) : master_size[1:0];
assign buf_aligned_in = (master_opc[2:0] == 3'b0) | // reads are always aligned since they are either DW or sideeffects
(master_size[1:0] == 2'b0) | (master_size[1:0] == 2'b01) | (master_size[1:0] == 2'b10) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
((master_size[1:0] == 2'b11) &
@ -396,59 +422,322 @@ import el2_pkg::*;
{1'b0, ({2{buf_aligned}} & buf_size[1:0])}; // Send the full size for aligned trxn
assign ahb_hburst[2:0] = 3'b0;
assign ahb_hmastlock = 1'b0;
assign ahb_hprot[3:0] = {3'b001,~axi_arprot[2]};
assign ahb_hprot[3:0] = {3'b001, ~axi_arprot[2]};
assign ahb_hwrite = bypass_en ? (master_opc[2:1] == 2'b01) : buf_write;
assign ahb_hwdata[63:0] = buf_data[63:0];
assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error);
assign slave_valid = slave_valid_pre; // & (~slvbuf_posted_write | slvbuf_error);
assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00;
assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10;
assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE) ? buf_data[63:0] : ahb_hrdata_q[63:0]);
assign slave_tag[TAG-1:0] = slvbuf_tag[TAG-1:0];
assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;
assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite;
rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff(.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(3)) wrbuf_sizeff (.din(axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & bus_clk_en), .clk(clk), .*);
rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & bus_clk_en), .clk(clk), .*);
rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff (.din(axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(
.WIDTH(1)
) wrbuf_vldff (
.din(1'b1),
.dout(wrbuf_vld),
.en(wrbuf_en),
.clear(wrbuf_rst),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffsc_fpga #(
.WIDTH(1)
) wrbuf_data_vldff (
.din(1'b1),
.dout(wrbuf_data_vld),
.en(wrbuf_data_en),
.clear(wrbuf_rst),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(TAG)
) wrbuf_tagff (
.din(axi_awid[TAG-1:0]),
.dout(wrbuf_tag[TAG-1:0]),
.en(wrbuf_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(3)
) wrbuf_sizeff (
.din(axi_awsize[2:0]),
.dout(wrbuf_size[2:0]),
.en(wrbuf_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(32)
) wrbuf_addrff (
.din (axi_awaddr[31:0]),
.dout(wrbuf_addr[31:0]),
.en (wrbuf_en & bus_clk_en),
.clk (clk),
.*
);
rvdffe #(
.WIDTH(64)
) wrbuf_dataff (
.din (axi_wdata[63:0]),
.dout(wrbuf_data[63:0]),
.en (wrbuf_data_en & bus_clk_en),
.clk (clk),
.*
);
rvdffs_fpga #(
.WIDTH(8)
) wrbuf_byteenff (
.din(axi_wstrb[7:0]),
.dout(wrbuf_byteen[7:0]),
.en(wrbuf_data_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(.WIDTH(32)) last_bus_addrff (.din(ahb_haddr[31:0]), .dout(last_bus_addr[31:0]), .en(last_addr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(
.WIDTH(32)
) last_bus_addrff (
.din(ahb_haddr[31:0]),
.dout(last_bus_addr[31:0]),
.en(last_addr_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffsc_fpga #(.WIDTH($bits(state_t))) buf_state_ff (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clear(buf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(1)) buf_writeff (.din(buf_write_in), .dout(buf_write), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(TAG)) buf_tagff (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[31:0]), .dout(buf_addr[31:0]), .en(buf_wr_en & bus_clk_en), .clk(clk), .*);
rvdffs_fpga #(.WIDTH(2)) buf_sizeff (.din(buf_size_in[1:0]), .dout(buf_size[1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(1)) buf_alignedff (.din(buf_aligned_in), .dout(buf_aligned), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(8)) buf_byteenff (.din(buf_byteen_in[7:0]), .dout(buf_byteen[7:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffe #(.WIDTH(64)) buf_dataff (.din(buf_data_in[63:0]), .dout(buf_data[63:0]), .en(buf_data_wr_en & bus_clk_en), .clk(clk), .*);
rvdffsc_fpga #(
.WIDTH($bits(state_t))
) buf_state_ff (
.din(buf_nxtstate),
.dout({buf_state}),
.en(buf_state_en),
.clear(buf_rst),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(1)
) buf_writeff (
.din(buf_write_in),
.dout(buf_write),
.en(buf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(TAG)
) buf_tagff (
.din(buf_tag_in[TAG-1:0]),
.dout(buf_tag[TAG-1:0]),
.en(buf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(32)
) buf_addrff (
.din (buf_addr_in[31:0]),
.dout(buf_addr[31:0]),
.en (buf_wr_en & bus_clk_en),
.clk (clk),
.*
);
rvdffs_fpga #(
.WIDTH(2)
) buf_sizeff (
.din(buf_size_in[1:0]),
.dout(buf_size[1:0]),
.en(buf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(1)
) buf_alignedff (
.din(buf_aligned_in),
.dout(buf_aligned),
.en(buf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(8)
) buf_byteenff (
.din(buf_byteen_in[7:0]),
.dout(buf_byteen[7:0]),
.en(buf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffe #(
.WIDTH(64)
) buf_dataff (
.din (buf_data_in[63:0]),
.dout(buf_data[63:0]),
.en (buf_data_wr_en & bus_clk_en),
.clk (clk),
.*
);
rvdffs_fpga #(.WIDTH(1)) slvbuf_writeff (.din(buf_write), .dout(slvbuf_write), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(TAG)) slvbuf_tagff (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(1)) slvbuf_errorff (.din(slvbuf_error_in), .dout(slvbuf_error), .en(slvbuf_error_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(
.WIDTH(1)
) slvbuf_writeff (
.din(buf_write),
.dout(slvbuf_write),
.en(slvbuf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(TAG)
) slvbuf_tagff (
.din(buf_tag[TAG-1:0]),
.dout(slvbuf_tag[TAG-1:0]),
.en(slvbuf_wr_en),
.clk(buf_clk),
.clken(buf_clken),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(1)
) slvbuf_errorff (
.din(slvbuf_error_in),
.dout(slvbuf_error),
.en(slvbuf_error_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff (.din(1'b1), .dout(cmd_doneQ), .en(cmd_done), .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(.WIDTH(3)) buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(
.WIDTH(1)
) buf_cmd_doneff (
.din(1'b1),
.dout(cmd_doneQ),
.en(cmd_done),
.clear(cmd_done_rst),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdffs_fpga #(
.WIDTH(3)
) buf_cmd_byte_ptrff (
.din(buf_cmd_byte_ptr[2:0]),
.dout(buf_cmd_byte_ptrQ[2:0]),
.en(buf_cmd_byte_ptr_en),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans[1:0]), .dout(ahb_htrans_q[1:0]), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .clken(ahbm_data_clken), .rawclk(clk), .*);
rvdff_fpga #(
.WIDTH(1)
) hready_ff (
.din(ahb_hready),
.dout(ahb_hready_q),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(2)
) htrans_ff (
.din(ahb_htrans[1:0]),
.dout(ahb_htrans_q[1:0]),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(1)
) hwrite_ff (
.din(ahb_hwrite),
.dout(ahb_hwrite_q),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(1)
) hresp_ff (
.din(ahb_hresp),
.dout(ahb_hresp_q),
.clk(bus_clk),
.clken(bus_clk_en),
.rawclk(clk),
.*
);
rvdff_fpga #(
.WIDTH(64)
) hrdata_ff (
.din(ahb_hrdata[63:0]),
.dout(ahb_hrdata_q[63:0]),
.clk(ahbm_data_clk),
.clken(ahbm_data_clken),
.rawclk(clk),
.*
);
// Clock headers
// clock enables for ahbm addr/data
assign buf_clken = bus_clk_en & (buf_wr_en | slvbuf_wr_en | clk_override);
assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*);
rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*);
rvclkhdr bus_cgc (
.en(bus_clk_en),
.l1clk(bus_clk),
.*
);
rvclkhdr buf_cgc (
.en(buf_clken),
.l1clk(buf_clk),
.*
);
rvclkhdr ahbm_data_cgc (
.en(ahbm_data_clken),
.l1clk(ahbm_data_clk),
.*
);
endmodule // axi4_to_ahb

462
Flow/design/lib/beh_lib.sv
View File

@ -16,78 +16,87 @@
// all flops call the rvdff flop
module rvdff #( parameter WIDTH=1, SHORT=0 )
(
module rvdff #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
if (SHORT == 1) begin
if (SHORT == 1) begin
assign dout = din;
end
else begin
end else begin
`ifdef RV_CLOCKGATE
always @(posedge tb_top.clk) begin
#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d", $time, din, dout, clk, WIDTH);
end
`endif
always_ff @(posedge clk or negedge rst_l) begin
if (rst_l == 0)
dout[WIDTH-1:0] <= 0;
else
dout[WIDTH-1:0] <= din[WIDTH-1:0];
if (rst_l == 0) dout[WIDTH-1:0] <= 0;
else dout[WIDTH-1:0] <= din[WIDTH-1:0];
end
end
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs #( parameter WIDTH=1, SHORT=0 )
(
module rvdffs #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
if (SHORT == 1) begin : genblock
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);
end
end else begin : genblock
rvdff #(WIDTH) dffs (
.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]),
.*
);
end
endmodule
// rvdff with en and clear
module rvdffsc #( parameter WIDTH=1, SHORT=0 )
(
module rvdffsc #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
if (SHORT == 1) begin
assign dout = din;
end
else begin
end else begin
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
end
rvdff #(WIDTH) dffsc (
.din(din_new[WIDTH-1:0]),
.*
);
end
endmodule
// _fpga versions
module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
(
module rvdff_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic clken,
@ -95,19 +104,20 @@ module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
if (SHORT == 1) begin
if (SHORT == 1) begin
assign dout = din;
end
else begin
end else begin
rvdff #(WIDTH) dff (.*);
end
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )
(
module rvdffs_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
@ -116,20 +126,21 @@ module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
if (SHORT == 1) begin : genblock
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
end else begin : genblock
rvdffs #(WIDTH) dffs (.*);
end
end
endmodule
// rvdff with en and clear
module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
(
module rvdffsc_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
@ -139,79 +150,99 @@ module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
input logic rst_l,
output logic [WIDTH-1:0] dout
);
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
if (SHORT == 1) begin
assign dout = din;
end
else begin
end else begin
rvdffsc #(WIDTH) dffsc (.*);
end
end
endmodule
module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
(
module rvdffe #(
parameter WIDTH = 1,
SHORT = 0,
OVERRIDE = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
);
logic l1clk;
if (SHORT == 1) begin : genblock
if (SHORT == 1) begin : genblock
if (1) begin : genblock
assign dout = din;
end
end
else begin : genblock
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
end // else: !if(SHORT == 1)
end else begin : genblock
rvclkhdr clkhdr (.*);
rvdff #(WIDTH) dff (
.*,
.clk(l1clk)
);
end // else: !if(SHORT == 1)
endmodule // rvdffe
module rvdffpcie #( parameter WIDTH=31 )
(
module rvdffpcie #(
parameter WIDTH = 31
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
);
rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
rvdfflie #(
.WIDTH(WIDTH),
.LEFT (19)
) dff (
.*
);
endmodule
// format: { LEFT, EXTRA }
// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe
module rvdfflie #( parameter WIDTH=16, LEFT=8 )
(
module rvdfflie #(
parameter WIDTH = 16,
LEFT = 8
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
localparam EXTRA = WIDTH - LEFT;
localparam LMSB = WIDTH - 1;
localparam LLSB = LMSB - LEFT + 1;
localparam XMSB = LLSB - 1;
localparam XLSB = LLSB - EXTRA;
rvdffiee #(LEFT) dff_left (
.*,
.din (din[LMSB:LLSB]),
.dout(dout[LMSB:LLSB])
);
rvdffe #(EXTRA) dff_extra (
.*,
.din (din[XMSB:XLSB]),
.dout(dout[XMSB:XLSB])
);
localparam EXTRA = WIDTH-LEFT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam XMSB = LLSB-1;
localparam XLSB = LLSB-EXTRA;
rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
endmodule
@ -221,55 +252,72 @@ endmodule
// special power flop for predict packet
// format: { LEFT, RIGHT==31 }
// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
module rvdffppe #( parameter WIDTH=32 )
(
module rvdffppe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
);
localparam RIGHT = 31;
localparam LEFT = WIDTH - RIGHT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam RMSB = LLSB-1;
localparam RLSB = LLSB-RIGHT;
localparam LMSB = WIDTH - 1;
localparam LLSB = LMSB - LEFT + 1;
localparam RMSB = LLSB - 1;
localparam RLSB = LLSB - RIGHT;
rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
rvdffe #(LEFT) dff_left (
.*,
.din (din[LMSB:LLSB]),
.dout(dout[LMSB:LLSB])
);
rvdffe #(RIGHT) dff_right (
.*,
.din (din[RMSB:RLSB]),
.dout(dout[RMSB:RLSB]),
.en (en & din[LLSB])
); // qualify with pret
endmodule
module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
(
module rvdffie #(
parameter WIDTH = 1,
OVERRIDE = 0
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
);
logic l1clk;
logic en;
assign en = |(din ^ dout);
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
rvclkhdr clkhdr (.*);
rvdff #(WIDTH) dff (
.*,
.clk(l1clk)
);
endmodule
// ie flop but it has an .en input
module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
(
module rvdffiee #(
parameter WIDTH = 1,
OVERRIDE = 0
) (
input logic [WIDTH-1:0] din,
input logic clk,
@ -277,7 +325,7 @@ module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
input logic scan_mode,
input logic en,
output logic [WIDTH-1:0] dout
);
);
logic l1clk;
logic final_en;
@ -285,51 +333,77 @@ module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
assign final_en = (|(din ^ dout)) & en;
rvdffe #(WIDTH) dff (.*, .en(final_en));
rvdffe #(WIDTH) dff (
.*,
.en(final_en)
);
endmodule
module rvsyncss #(parameter WIDTH = 251)
(
module rvsyncss #(
parameter WIDTH = 251
) (
input logic clk,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
);
logic [WIDTH-1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
rvdff #(WIDTH) sync_ff1 (
.*,
.din (din[WIDTH-1:0]),
.dout(din_ff1[WIDTH-1:0])
);
rvdff #(WIDTH) sync_ff2 (
.*,
.din (din_ff1[WIDTH-1:0]),
.dout(dout[WIDTH-1:0])
);
endmodule // rvsyncss
module rvsyncss_fpga #(parameter WIDTH = 251)
(
module rvsyncss_fpga #(
parameter WIDTH = 251
) (
input logic gw_clk,
input logic rawclk,
input logic clken,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
);
logic [WIDTH-1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
rvdff_fpga #(WIDTH) sync_ff1 (
.*,
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din[WIDTH-1:0]),
.dout(din_ff1[WIDTH-1:0])
);
rvdff_fpga #(WIDTH) sync_ff2 (
.*,
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din_ff1[WIDTH-1:0]),
.dout(dout[WIDTH-1:0])
);
endmodule // rvsyncss
module rvlsadder
(
module rvlsadder (
input logic [31:0] rs1,
input logic [11:0] offset,
output logic [31:0] dout
);
);
logic cout;
logic sign;
@ -337,7 +411,7 @@ module rvlsadder
logic [31:12] rs1_inc;
logic [31:12] rs1_dec;
assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
assign {cout, dout[11:0]} = {1'b0, rs1[11:0]} + {1'b0, offset[11:0]};
assign rs1_inc[31:12] = rs1[31:12] + 1;
@ -353,13 +427,12 @@ endmodule // rvlsadder
// assume we only maintain pc[31:1] in the pipe
module rvbradder
(
module rvbradder (
input [31:1] pc,
input [12:1] offset,
output [31:1] dout
);
);
logic cout;
logic sign;
@ -367,7 +440,7 @@ module rvbradder
logic [31:13] pc_inc;
logic [31:13] pc_dec;
assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};
assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]};
assign pc_inc[31:13] = pc[31:13] + 1;
@ -385,57 +458,61 @@ endmodule // rvbradder
// 2s complement circuit
module rvtwoscomp #( parameter WIDTH=32 )
(
module rvtwoscomp #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
);
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
for (i = 1; i < WIDTH; i++) begin : flip_after_first_one
assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
end : flip_after_first_one
assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };
assign dout[WIDTH-1:0] = {dout_temp[WIDTH-1:1], din[0]};
endmodule // 2'scomp
// find first
module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
(
module rvfindfirst1 #(
parameter WIDTH = 32,
SHIFT = $clog2(WIDTH)
) (
input logic [WIDTH-1:0] din,
output logic [SHIFT-1:0] dout
);
);
logic done;
always_comb begin
dout[SHIFT-1:0] = {SHIFT{1'b0}};
done = 1'b0;
for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
for (int i = WIDTH - 1; i > 0; i--) begin : find_first_one
done |= din[i];
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
end : find_first_one
end
endmodule // rvfindfirst1
module rvfindfirst1hot #( parameter WIDTH=32 )
(
module rvfindfirst1hot #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
);
logic done;
always_comb begin
dout[WIDTH-1:0] = {WIDTH{1'b0}};
done = 1'b0;
for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
for (int i = 0; i < WIDTH; i++) begin : find_first_one
dout[i] = ~done & din[i];
done |= din[i];
end : find_first_one
@ -444,13 +521,14 @@ endmodule // rvfindfirst1hot
// mask and match function matches bits after finding the first 0 position
// find first starting from LSB. Skip that location and match the rest of the bits
module rvmaskandmatch #( parameter WIDTH=32 )
(
module rvmaskandmatch #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions
input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits
input logic masken, // when 1 : do mask. 0 : full match
output logic match
);
);
logic [WIDTH-1:0] matchvec;
logic masken_or_fullmask;
@ -460,7 +538,7 @@ module rvmaskandmatch #( parameter WIDTH=32 )
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
for (i = 1; i < WIDTH; i++) begin : match_after_first_zero
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
end : match_after_first_zero
@ -472,8 +550,10 @@ endmodule // rvmaskandmatch
// Check if the S_ADDR <= addr < E_ADDR
module rvrangecheck #(CCM_SADR = 32'h0,
CCM_SIZE = 128) (
module rvrangecheck #(
CCM_SADR = 32'h0,
CCM_SIZE = 128
) (
input logic [31:0] addr, // Address to be checked for range
output logic in_range, // S_ADDR <= start_addr < E_ADDR
output logic in_region
@ -483,7 +563,7 @@ module rvrangecheck #(CCM_SADR = 32'h0,
localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
logic [31:0] start_addr;
logic [3:0] region;
logic [ 3:0] region;
assign start_addr[31:0] = CCM_SADR;
assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];
@ -491,61 +571,64 @@ module rvrangecheck #(CCM_SADR = 32'h0,
assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);
if (CCM_SIZE == 48)
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);
else
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
else assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
endmodule // rvrangechecker
// 16 bit even parity generator
module rveven_paritygen #(WIDTH = 16) (
module rveven_paritygen #(
WIDTH = 16
) (
input logic [WIDTH-1:0] data_in, // Data
output logic parity_out // generated even parity
);
);
assign parity_out = ^(data_in[WIDTH-1:0]) ;
assign parity_out = ^(data_in[WIDTH-1:0]);
endmodule // rveven_paritygen
module rveven_paritycheck #(WIDTH = 16) (
module rveven_paritycheck #(
WIDTH = 16
) (
input logic [WIDTH-1:0] data_in, // Data
input logic parity_in,
output logic parity_err // Parity error
);
);
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in;
endmodule // rveven_paritycheck
module rvecc_encode (
input [31:0] din,
output [6:0] ecc_out
);
logic [5:0] ecc_out_temp;
output [ 6:0] ecc_out
);
logic [5:0] ecc_out_temp;
assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
assign ecc_out_temp[5] = din[26] ^ din[27] ^ din[28] ^ din[29] ^ din[30] ^ din[31];
assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};
assign ecc_out[6:0] = {(^din[31:0]) ^ (^ecc_out_temp[5:0]), ecc_out_temp[5:0]};
endmodule // rvecc_encode
module rvecc_decode (
input en,
input [31:0] din,
input [6:0] ecc_in,
input [ 6:0] ecc_in,
input sed_ded, // only do detection and no correction. Used for the I$
output [31:0] dout,
output [6:0] ecc_out,
output [ 6:0] ecc_out,
output single_ecc_error,
output double_ecc_error
);
);
logic [6:0] ecc_check;
logic [ 6:0] ecc_check;
logic [38:0] error_mask;
logic [38:0] din_plus_parity, dout_plus_parity;
@ -555,32 +638,57 @@ module rvecc_decode (
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
assign ecc_check[5] = ecc_in[5] ^ din[26] ^ din[27] ^ din[28] ^ din[29] ^ din[30] ^ din[31];
// This is the parity bit
assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;
assign ecc_check[6] = ((^din[31:0]) ^ (^ecc_in[6:0])) & ~sed_ded;
assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded
assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE
// Generate the mask for error correctiong
for (genvar i=1; i<40; i++) begin
for (genvar i = 1; i < 40; i++) begin
assign error_mask[i-1] = (ecc_check[5:0] == i);
end
// Generate the corrected data
assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
assign din_plus_parity[38:0] = {
ecc_in[6],
din[31:26],
ecc_in[5],
din[25:11],
ecc_in[4],
din[10:4],
ecc_in[3],
din[3:1],
ecc_in[2],
din[0],
ecc_in[1:0]
};
assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];
assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
assign dout[31:0] = {
dout_plus_parity[37:32],
dout_plus_parity[30:16],
dout_plus_parity[14:8],
dout_plus_parity[6:4],
dout_plus_parity[2]
};
assign ecc_out[6:0] = {
(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)),
dout_plus_parity[31],
dout_plus_parity[15],
dout_plus_parity[7],
dout_plus_parity[3],
dout_plus_parity[1:0]
};
endmodule // rvecc_decode
module rvecc_encode_64 (
input [63:0] din,
output [6:0] ecc_out
);
output [ 6:0] ecc_out
);
assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
@ -593,7 +701,7 @@ module rvecc_encode_64 (
assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
assign ecc_out[6] = din[57] ^ din[58] ^ din[59] ^ din[60] ^ din[61] ^ din[62] ^ din[63];
endmodule // rvecc_encode_64
@ -601,9 +709,9 @@ endmodule // rvecc_encode_64
module rvecc_decode_64 (
input en,
input [63:0] din,
input [6:0] ecc_in,
input [ 6:0] ecc_in,
output ecc_error
);
);
logic [6:0] ecc_check;
@ -624,14 +732,15 @@ module rvecc_decode_64 (
assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE
endmodule // rvecc_decode_64
endmodule // rvecc_decode_64
module clockhdr
(
input logic SE, EN, CK,
module clockhdr (
input logic SE,
EN,
CK,
output Q
);
);
logic en_ff;
logic enable;
@ -644,41 +753,48 @@ module clockhdr
end
`else
always @(CK, enable) begin
if(!CK)
en_ff = enable;
if (!CK) en_ff = enable;
end
`endif
assign Q = CK & en_ff;
endmodule
module rvclkhdr
(
module rvclkhdr (
input logic en,
input logic clk,
input logic scan_mode,
output logic l1clk
);
);
logic SE;
assign SE = 0;
clockhdr clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
clockhdr clkhdr (
.*,
.EN(en),
.CK(clk),
.Q (l1clk)
);
endmodule // rvclkhdr
module rvoclkhdr
(
module rvoclkhdr (
input logic en,
input logic clk,
input logic scan_mode,
output logic l1clk
);
);
logic SE;
assign SE = 0;
clockhdr clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
clockhdr clkhdr (
.*,
.EN(en),
.CK(clk),
.Q (l1clk)
);
endmodule

57
Flow/design/lib/el2_lib.sv
View File

@ -1,63 +1,70 @@
module el2_btb_tag_hash #(
`include "el2_param.vh"
) (
`include "el2_param.vh"
) (
input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
output logic [pt.BTB_BTAG_SIZE-1:0] hash
);
);
assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^
assign hash = {
(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])};
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])
};
endmodule
module el2_btb_tag_hash_fold #(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
output logic [pt.BTB_BTAG_SIZE-1:0] hash
);
);
assign hash = {(
assign hash = {
(
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])};
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])
};
endmodule
module el2_btb_addr_hash #(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
);
);
if(pt.BTB_FOLD2_INDEX_HASH) begin : fold2
if (pt.BTB_FOLD2_INDEX_HASH) begin : fold2
assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^
pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO];
end
else begin
end else begin
assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^
pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^
pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO];
end
end
endmodule
module el2_btb_ghr_hash #(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
input logic [pt.BHT_GHR_SIZE-1:0] ghr,
output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
);
);
// The hash function is too complex to write in verilog for all cases.
// The config script generates the logic string based on the bp config.
if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1
assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]};
end
else begin : ghrhash_cfg2
assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]};
if (pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1
assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = {
ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1],
hashin[pt.BTB_INDEX1_HI:2] ^ ghr[pt.BTB_INDEX1_HI-2:0]
};
end else begin : ghrhash_cfg2
assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = {
hashin[pt.BHT_GHR_SIZE+1:2] ^ ghr[pt.BHT_GHR_SIZE-1:0]
};
end

22
Flow/design/lib/mem_lib.sv
View File

@ -83,22 +83,28 @@ assign ROP = ME; \
endmodule
// parameterizable RAM for verilator sims
module el2_ram #(depth=4096, width=39) (
input logic [$clog2(depth)-1:0] ADR,
input logic [(width-1):0] D,
output logic [(width-1):0] Q,
module el2_ram #(
depth = 4096,
width = 39
) (
input logic [$clog2(depth)-1:0] ADR,
input logic [(width-1):0] D,
output logic [(width-1):0] Q,
`EL2_LOCAL_RAM_TEST_IO
);
reg [(width-1):0] ram_core [(depth-1):0];
reg [(width-1):0] ram_core[(depth-1):0];
always @(posedge CLK) begin
always @(posedge CLK) begin
`ifdef GTLSIM
if (ME && WE) ram_core[ADR] <= D;
`else
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
if (ME && WE) begin
ram_core[ADR] <= D;
Q <= 'x;
end
`endif
if (ME && ~WE) Q <= ram_core[ADR];
end
end
endmodule
//=========================================================================================================================

97
Flow/design/lsu/el2_lsu.sv
View File

@ -26,11 +26,10 @@
//********************************************************************************
module el2_lsu
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk_override, // Override non-functional clock gating
input logic dec_tlu_flush_lower_r, // I0/I1 writeback flush. This is used to flush the old packets only
@ -60,7 +59,7 @@ import el2_pkg::*;
output logic lsu_active, // Used to turn off top level clk
output logic [31:1] lsu_fir_addr, // fast interrupt address
output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup
output logic [ 1:0] lsu_fir_error, // Error during fast interrupt lookup
output logic lsu_single_ecc_error_incr, // Increment the ecc counter
output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet
@ -116,61 +115,61 @@ import el2_pkg::*;
output logic lsu_axi_awvalid,
input logic lsu_axi_awready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
output logic [31:0] lsu_axi_awaddr,
output logic [3:0] lsu_axi_awregion,
output logic [7:0] lsu_axi_awlen,
output logic [2:0] lsu_axi_awsize,
output logic [1:0] lsu_axi_awburst,
output logic [ 31:0] lsu_axi_awaddr,
output logic [ 3:0] lsu_axi_awregion,
output logic [ 7:0] lsu_axi_awlen,
output logic [ 2:0] lsu_axi_awsize,
output logic [ 1:0] lsu_axi_awburst,
output logic lsu_axi_awlock,
output logic [3:0] lsu_axi_awcache,
output logic [2:0] lsu_axi_awprot,
output logic [3:0] lsu_axi_awqos,
output logic [ 3:0] lsu_axi_awcache,
output logic [ 2:0] lsu_axi_awprot,
output logic [ 3:0] lsu_axi_awqos,
output logic lsu_axi_wvalid,
input logic lsu_axi_wready,
output logic [63:0] lsu_axi_wdata,
output logic [7:0] lsu_axi_wstrb,
output logic [ 7:0] lsu_axi_wstrb,
output logic lsu_axi_wlast,
input logic lsu_axi_bvalid,
output logic lsu_axi_bready,
input logic [1:0] lsu_axi_bresp,
input logic [ 1:0] lsu_axi_bresp,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
// AXI Read Channels
output logic lsu_axi_arvalid,
input logic lsu_axi_arready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
output logic [31:0] lsu_axi_araddr,
output logic [3:0] lsu_axi_arregion,
output logic [7:0] lsu_axi_arlen,
output logic [2:0] lsu_axi_arsize,
output logic [1:0] lsu_axi_arburst,
output logic [ 31:0] lsu_axi_araddr,
output logic [ 3:0] lsu_axi_arregion,
output logic [ 7:0] lsu_axi_arlen,
output logic [ 2:0] lsu_axi_arsize,
output logic [ 1:0] lsu_axi_arburst,
output logic lsu_axi_arlock,
output logic [3:0] lsu_axi_arcache,
output logic [2:0] lsu_axi_arprot,
output logic [3:0] lsu_axi_arqos,
output logic [ 3:0] lsu_axi_arcache,
output logic [ 2:0] lsu_axi_arprot,
output logic [ 3:0] lsu_axi_arqos,
input logic lsu_axi_rvalid,
output logic lsu_axi_rready,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
input logic [63:0] lsu_axi_rdata,
input logic [1:0] lsu_axi_rresp,
input logic [ 63:0] lsu_axi_rdata,
input logic [ 1:0] lsu_axi_rresp,
input logic lsu_axi_rlast,
input logic lsu_bus_clk_en, // external drives a clock_en to control bus ratio
// DMA slave
input logic dma_dccm_req, // DMA read/write to dccm
input logic [2:0] dma_mem_tag, // DMA request tag
input logic [ 2:0] dma_mem_tag, // DMA request tag
input logic [31:0] dma_mem_addr, // DMA address
input logic [2:0] dma_mem_sz, // DMA access size
input logic [ 2:0] dma_mem_sz, // DMA access size
input logic dma_mem_write, // DMA access is a write
input logic [63:0] dma_mem_wdata, // DMA write data
output logic dccm_dma_rvalid, // lsu data valid for DMA dccm read
output logic dccm_dma_ecc_error, // DMA load had ecc error
output logic [2:0] dccm_dma_rtag, // DMA request tag
output logic [ 2:0] dccm_dma_rtag, // DMA request tag
output logic [63:0] dccm_dma_rdata, // lsu data for DMA dccm read
output logic dccm_ready, // lsu ready for DMA access
@ -179,7 +178,7 @@ import el2_pkg::*;
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l // reset, active low
);
);
logic lsu_dccm_rden_m;
logic lsu_dccm_rden_r;
@ -227,9 +226,9 @@ import el2_pkg::*;
logic stbuf_reqvld_any;
logic stbuf_reqvld_flushed_any;
logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any;
logic [ pt.LSU_SB_BITS-1:0] stbuf_addr_any;
logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any;
logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any;
logic [ pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any;
logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, sec_data_hi_r_ff;
logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, sec_data_ecc_lo_r_ff;
@ -249,7 +248,7 @@ import el2_pkg::*;
logic lsu_bus_buffer_empty_any;
logic lsu_bus_buffer_full_any;
logic lsu_busreq_m;
logic [31:0] bus_read_data_m;
logic [ 31:0] bus_read_data_m;
logic flush_m_up, flush_r;
logic is_sideeffects_m;
@ -330,7 +329,9 @@ import el2_pkg::*;
assign lsu_pmu_load_external_m = lsu_pkt_m.valid & lsu_pkt_m.load & addr_external_m;
assign lsu_pmu_store_external_m = lsu_pkt_m.valid & lsu_pkt_m.store & addr_external_m;
el2_lsu_dccm_ctl #(.pt(pt)) dccm_ctl (
el2_lsu_dccm_ctl #(
.pt(pt)
) dccm_ctl (
.lsu_addr_d(lsu_addr_d[31:0]),
.end_addr_d(end_addr_d[pt.DCCM_BITS-1:0]),
.lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),
@ -341,7 +342,9 @@ import el2_pkg::*;
.*
);
el2_lsu_stbuf #(.pt(pt)) stbuf (
el2_lsu_stbuf #(
.pt(pt)
) stbuf (
.lsu_addr_d(lsu_addr_d[pt.LSU_SB_BITS-1:0]),
.end_addr_d(end_addr_d[pt.LSU_SB_BITS-1:0]),
@ -349,7 +352,9 @@ import el2_pkg::*;
);
el2_lsu_ecc #(.pt(pt)) ecc (
el2_lsu_ecc #(
.pt(pt)
) ecc (
.lsu_addr_r(lsu_addr_r[pt.DCCM_BITS-1:0]),
.end_addr_r(end_addr_r[pt.DCCM_BITS-1:0]),
.lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),
@ -357,7 +362,9 @@ import el2_pkg::*;
.*
);
el2_lsu_trigger #(.pt(pt)) trigger (
el2_lsu_trigger #(
.pt(pt)
) trigger (
.store_data_m(store_data_m[31:0]),
.*
);
@ -366,7 +373,9 @@ import el2_pkg::*;
el2_lsu_clkdomain #(.pt(pt)) clkdomain (.*);
// Bus interface
el2_lsu_bus_intf #(.pt(pt)) bus_intf (
el2_lsu_bus_intf #(
.pt(pt)
) bus_intf (
.lsu_addr_m(lsu_addr_m[31:0] & {32{addr_external_m & lsu_pkt_m.valid}}),
.lsu_addr_r(lsu_addr_r[31:0] & {32{lsu_busreq_r}}),
@ -378,7 +387,17 @@ import el2_pkg::*;
);
//Flops
rvdff #(3) dma_mem_tag_mff (.*, .din(dma_mem_tag_d[2:0]), .dout(dma_mem_tag_m[2:0]), .clk(lsu_c1_m_clk));
rvdff #(2) lsu_raw_fwd_r_ff (.*, .din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}), .dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}), .clk(lsu_c2_r_clk));
rvdff #(3) dma_mem_tag_mff (
.*,
.din (dma_mem_tag_d[2:0]),
.dout(dma_mem_tag_m[2:0]),
.clk (lsu_c1_m_clk)
);
rvdff #(2) lsu_raw_fwd_r_ff (
.*,
.din ({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}),
.dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}),
.clk (lsu_c2_r_clk)
);
endmodule // el2_lsu

47
Flow/design/lsu/el2_lsu_addrcheck.sv
View File

@ -23,10 +23,10 @@
//
//********************************************************************************
module el2_lsu_addrcheck
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic lsu_c2_m_clk, // clock
input logic rst_l, // reset
@ -34,7 +34,7 @@ import el2_pkg::*;
input logic [31:0] end_addr_d, // end address for lsu
input el2_lsu_pkt_t lsu_pkt_d, // packet in d
input logic [31:0] dec_tlu_mrac_ff, // CSR read
input logic [3:0] rs1_region_d, // address rs operand [31:28]
input logic [ 3:0] rs1_region_d, // address rs operand [31:28]
input logic [31:0] rs1_d, // address rs operand
@ -48,7 +48,7 @@ import el2_pkg::*;
output logic [3:0] exc_mscause_d, // mscause for access/misaligned faults
output logic fir_dccm_access_error_d, // Fast interrupt dccm access error
output logic fir_nondccm_access_error_d,// Fast interrupt dccm access error
output logic fir_nondccm_access_error_d, // Fast interrupt dccm access error
input logic scan_mode // Scan mode
);
@ -69,23 +69,27 @@ import el2_pkg::*;
logic [3:0] access_fault_mscause_d;
logic [3:0] misaligned_fault_mscause_d;
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
// Start address check
rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)) start_addr_dccm_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)
) start_addr_dccm_rangecheck (
.addr(start_addr_d[31:0]),
.in_range(start_addr_in_dccm_d),
.in_region(start_addr_in_dccm_region_d)
);
// End address check
rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)) end_addr_dccm_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.DCCM_SADR),
.CCM_SIZE(pt.DCCM_SIZE)
) end_addr_dccm_rangecheck (
.addr(end_addr_d[31:0]),
.in_range(end_addr_in_dccm_d),
.in_region(end_addr_in_dccm_region_d)
);
end else begin: Gen_dccm_disable // block: Gen_dccm_enable
end else begin : Gen_dccm_disable // block: Gen_dccm_enable
assign start_addr_in_dccm_d = '0;
assign start_addr_in_dccm_region_d = '0;
assign end_addr_in_dccm_d = '0;
@ -100,16 +104,20 @@ import el2_pkg::*;
// PIC memory check
// Start address check
rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)) start_addr_pic_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)
) start_addr_pic_rangecheck (
.addr(start_addr_d[31:0]),
.in_range(start_addr_in_pic_d),
.in_region(start_addr_in_pic_region_d)
);
// End address check
rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)) end_addr_pic_rangecheck (
rvrangecheck #(
.CCM_SADR(pt.PIC_BASE_ADDR),
.CCM_SIZE(pt.PIC_SIZE)
) end_addr_pic_rangecheck (
.addr(end_addr_d[31:0]),
.in_range(end_addr_in_pic_d),
.in_region(end_addr_in_pic_region_d)
@ -186,6 +194,13 @@ import el2_pkg::*;
(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;
assign fir_nondccm_access_error_d = ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;
rvdff #(.WIDTH(1)) is_sideeffects_mff (.din(is_sideeffects_d), .dout(is_sideeffects_m), .clk(lsu_c2_m_clk), .*);
rvdff #(
.WIDTH(1)
) is_sideeffects_mff (
.din (is_sideeffects_d),
.dout(is_sideeffects_m),
.clk (lsu_c2_m_clk),
.*
);
endmodule // el2_lsu_addrcheck

926
Flow/design/lsu/el2_lsu_bus_buffer.sv
View File

File diff suppressed because it is too large Load Diff

95
Flow/design/lsu/el2_lsu_bus_intf.sv
View File

@ -23,10 +23,10 @@
//
//********************************************************************************
module el2_lsu_bus_intf
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic clk_override, // Override non-functional clock gating
input logic rst_l, // reset, active low
@ -67,7 +67,9 @@ import el2_pkg::*;
input logic is_sideeffects_m, // lsu attribute is side_effects
input logic flush_m_up, // flush
input logic flush_r, // flush
input logic ldst_dual_d, ldst_dual_m, ldst_dual_r,
input logic ldst_dual_d,
ldst_dual_m,
ldst_dual_r,
output logic lsu_busreq_r, // bus request is in r
output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
@ -86,7 +88,7 @@ import el2_pkg::*;
output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads
output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
output logic lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
output logic lsu_nonblock_load_data_error,// non block load has an error
output logic lsu_nonblock_load_data_error, // non block load has an error
output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
@ -100,46 +102,46 @@ import el2_pkg::*;
output logic lsu_axi_awvalid,
input logic lsu_axi_awready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
output logic [31:0] lsu_axi_awaddr,
output logic [3:0] lsu_axi_awregion,
output logic [7:0] lsu_axi_awlen,
output logic [2:0] lsu_axi_awsize,
output logic [1:0] lsu_axi_awburst,
output logic [ 31:0] lsu_axi_awaddr,
output logic [ 3:0] lsu_axi_awregion,
output logic [ 7:0] lsu_axi_awlen,
output logic [ 2:0] lsu_axi_awsize,
output logic [ 1:0] lsu_axi_awburst,
output logic lsu_axi_awlock,
output logic [3:0] lsu_axi_awcache,
output logic [2:0] lsu_axi_awprot,
output logic [3:0] lsu_axi_awqos,
output logic [ 3:0] lsu_axi_awcache,
output logic [ 2:0] lsu_axi_awprot,
output logic [ 3:0] lsu_axi_awqos,
output logic lsu_axi_wvalid,
input logic lsu_axi_wready,
output logic [63:0] lsu_axi_wdata,
output logic [7:0] lsu_axi_wstrb,
output logic [ 7:0] lsu_axi_wstrb,
output logic lsu_axi_wlast,
input logic lsu_axi_bvalid,
output logic lsu_axi_bready,
input logic [1:0] lsu_axi_bresp,
input logic [ 1:0] lsu_axi_bresp,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
// AXI Read Channels
output logic lsu_axi_arvalid,
input logic lsu_axi_arready,
output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
output logic [31:0] lsu_axi_araddr,
output logic [3:0] lsu_axi_arregion,
output logic [7:0] lsu_axi_arlen,
output logic [2:0] lsu_axi_arsize,
output logic [1:0] lsu_axi_arburst,
output logic [ 31:0] lsu_axi_araddr,
output logic [ 3:0] lsu_axi_arregion,
output logic [ 7:0] lsu_axi_arlen,
output logic [ 2:0] lsu_axi_arsize,
output logic [ 1:0] lsu_axi_arburst,
output logic lsu_axi_arlock,
output logic [3:0] lsu_axi_arcache,
output logic [2:0] lsu_axi_arprot,
output logic [3:0] lsu_axi_arqos,
output logic [ 3:0] lsu_axi_arcache,
output logic [ 2:0] lsu_axi_arprot,
output logic [ 3:0] lsu_axi_arqos,
input logic lsu_axi_rvalid,
output logic lsu_axi_rready,
input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
input logic [63:0] lsu_axi_rdata,
input logic [1:0] lsu_axi_rresp,
input logic [ 63:0] lsu_axi_rdata,
input logic [ 1:0] lsu_axi_rresp,
input logic lsu_bus_clk_en
@ -186,22 +188,20 @@ import el2_pkg::*;
({4{lsu_pkt_m.word}} & 4'b1111);
// Read/Write Buffer
el2_lsu_bus_buffer #(.pt(pt)) bus_buffer (
.*
);
el2_lsu_bus_buffer #(.pt(pt)) bus_buffer (.*);
// Logic to determine if dc5 store can be coalesced or not with younger stores. Bypass ibuf if cannot colaesced
assign addr_match_dw_lo_r_m = (lsu_addr_r[31:3] == lsu_addr_m[31:3]);
assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2]^lsu_addr_m[2]);
assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2] ^ lsu_addr_m[2]);
assign no_word_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_word_lo_r_m);
assign no_dword_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_dw_lo_r_m);
// Create Hi/Lo signals
assign ldst_byteen_ext_m[7:0] = {4'b0,ldst_byteen_m[3:0]} << lsu_addr_m[1:0];
assign ldst_byteen_ext_r[7:0] = {4'b0,ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
assign ldst_byteen_ext_m[7:0] = {4'b0, ldst_byteen_m[3:0]} << lsu_addr_m[1:0];
assign ldst_byteen_ext_r[7:0] = {4'b0, ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
assign store_data_ext_r[63:0] = {32'b0,store_data_r[31:0]} << {lsu_addr_r[1:0],3'b0};
assign store_data_ext_r[63:0] = {32'b0, store_data_r[31:0]} << {lsu_addr_r[1:0], 3'b0};
assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
@ -216,7 +216,7 @@ import el2_pkg::*;
assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
for (genvar i=0; i<4; i++) begin: GenBusBufFwd
for (genvar i = 0; i < 4; i++) begin : GenBusBufFwd
assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i];
assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i] & ldst_byteen_hi_m[i];
assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i] & ldst_byteen_lo_m[i];
@ -247,7 +247,7 @@ import el2_pkg::*;
always_comb begin
ld_full_hit_lo_m = 1'b1;
ld_full_hit_hi_m = 1'b1;
for (int i=0; i<4; i++) begin
for (int i = 0; i < 4; i++) begin
ld_full_hit_lo_m &= (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]);
ld_full_hit_hi_m &= (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]);
end
@ -256,15 +256,34 @@ import el2_pkg::*;
// This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf)
assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m;
assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]);
assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8 * lsu_addr_m[1:0]);
assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];
// Fifo flops
rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(active_clk), .*);
rvdff #(
.WIDTH(1)
) clken_ff (
.din (lsu_bus_clk_en),
.dout(lsu_bus_clk_en_q),
.clk (active_clk),
.*
);
rvdff #(.WIDTH(1)) is_sideeffects_rff (.din(is_sideeffects_m), .dout(is_sideeffects_r), .clk(lsu_c1_r_clk), .*);
rvdff #(
.WIDTH(1)
) is_sideeffects_rff (
.din (is_sideeffects_m),
.dout(is_sideeffects_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(4) lsu_byten_rff (.*, .din(ldst_byteen_m[3:0]), .dout(ldst_byteen_r[3:0]), .clk(lsu_c1_r_clk));
rvdff #(4) lsu_byten_rff (
.*,
.din (ldst_byteen_m[3:0]),
.dout(ldst_byteen_r[3:0]),
.clk (lsu_c1_r_clk)
);
endmodule // el2_lsu_bus_intf

103
Flow/design/lsu/el2_lsu_clkdomain.sv
View File

@ -24,10 +24,10 @@
module el2_lsu_clkdomain
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
@ -97,8 +97,8 @@ import el2_pkg::*;
assign lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | clk_override;
assign lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | clk_override;
assign lsu_store_c1_m_clken = ((lsu_c1_m_clken & lsu_pkt_d.store) | clk_override) ;
assign lsu_store_c1_r_clken = ((lsu_c1_r_clken & lsu_pkt_m.store) | clk_override) ;
assign lsu_store_c1_m_clken = ((lsu_c1_m_clken & lsu_pkt_d.store) | clk_override);
assign lsu_store_c1_r_clken = ((lsu_c1_r_clken & lsu_pkt_m.store) | clk_override);
assign lsu_stbuf_c1_clken = ldst_stbuf_reqvld_r | stbuf_reqvld_any | stbuf_reqvld_flushed_any | clk_override;
assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override;
@ -110,31 +110,94 @@ import el2_pkg::*;
assign lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | clk_override;
// Flops
rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), .dout(lsu_free_c1_clken_q), .clk(active_clk), .*);
rvdff #(1) lsu_free_c1_clkenff (
.din (lsu_free_c1_clken),
.dout(lsu_free_c1_clken_q),
.clk (active_clk),
.*
);
rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), .dout(lsu_c1_m_clken_q), .clk(lsu_free_c2_clk), .*);
rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), .dout(lsu_c1_r_clken_q), .clk(lsu_free_c2_clk), .*);
rvdff #(1) lsu_c1_m_clkenff (
.din (lsu_c1_m_clken),
.dout(lsu_c1_m_clken_q),
.clk (lsu_free_c2_clk),
.*
);
rvdff #(1) lsu_c1_r_clkenff (
.din (lsu_c1_r_clken),
.dout(lsu_c1_r_clken_q),
.clk (lsu_free_c2_clk),
.*
);
// Clock Headers
rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), .l1clk(lsu_c1_m_clk), .* );
rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), .l1clk(lsu_c1_r_clk), .* );
rvoclkhdr lsu_c1m_cgc (
.en(lsu_c1_m_clken),
.l1clk(lsu_c1_m_clk),
.*
);
rvoclkhdr lsu_c1r_cgc (
.en(lsu_c1_r_clken),
.l1clk(lsu_c1_r_clk),
.*
);
rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), .l1clk(lsu_c2_m_clk), .* );
rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), .l1clk(lsu_c2_r_clk), .* );
rvoclkhdr lsu_c2m_cgc (
.en(lsu_c2_m_clken),
.l1clk(lsu_c2_m_clk),
.*
);
rvoclkhdr lsu_c2r_cgc (
.en(lsu_c2_r_clken),
.l1clk(lsu_c2_r_clk),
.*
);
rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), .l1clk(lsu_store_c1_m_clk), .*);
rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), .l1clk(lsu_store_c1_r_clk), .*);
rvoclkhdr lsu_store_c1m_cgc (
.en(lsu_store_c1_m_clken),
.l1clk(lsu_store_c1_m_clk),
.*
);
rvoclkhdr lsu_store_c1r_cgc (
.en(lsu_store_c1_r_clken),
.l1clk(lsu_store_c1_r_clk),
.*
);
rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );
rvoclkhdr lsu_stbuf_c1_cgc (
.en(lsu_stbuf_c1_clken),
.l1clk(lsu_stbuf_c1_clk),
.*
);
rvoclkhdr lsu_bus_ibuf_c1_cgc (
.en(lsu_bus_ibuf_c1_clken),
.l1clk(lsu_bus_ibuf_c1_clk),
.*
);
rvoclkhdr lsu_bus_buf_c1_cgc (
.en(lsu_bus_buf_c1_clken),
.l1clk(lsu_bus_buf_c1_clk),
.*
);
assign lsu_busm_clken = (~lsu_bus_buffer_empty_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;
rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
rvclkhdr lsu_busm_cgc (.en(lsu_busm_clken), .l1clk(lsu_busm_clk), .*);
rvclkhdr lsu_bus_obuf_c1_cgc (
.en(lsu_bus_obuf_c1_clken),
.l1clk(lsu_bus_obuf_c1_clk),
.*
);
rvclkhdr lsu_busm_cgc (
.en(lsu_busm_clken),
.l1clk(lsu_busm_clk),
.*
);
rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);
rvoclkhdr lsu_free_cgc (
.en(lsu_free_c2_clken),
.l1clk(lsu_free_c2_clk),
.*
);
endmodule

239
Flow/design/lsu/el2_lsu_dccm_ctl.sv
View File

@ -27,11 +27,10 @@
// //********************************************************************************
module el2_lsu_dccm_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic lsu_c2_m_clk, // clocks
input logic lsu_c2_r_clk, // clocks
input logic lsu_c1_r_clk, // clocks
@ -42,22 +41,25 @@ import el2_pkg::*;
input logic rst_l, // reset, active low
input el2_lsu_pkt_t lsu_pkt_r,// lsu packets
input el2_lsu_pkt_t lsu_pkt_m,// lsu packets
input el2_lsu_pkt_t lsu_pkt_d,// lsu packets
input el2_lsu_pkt_t lsu_pkt_r, // lsu packets
input el2_lsu_pkt_t lsu_pkt_m, // lsu packets
input el2_lsu_pkt_t lsu_pkt_d, // lsu packets
input logic addr_in_dccm_d, // address maps to dccm
input logic addr_in_pic_d, // address maps to pic
input logic addr_in_pic_m, // address maps to pic
input logic addr_in_dccm_m, addr_in_dccm_r, // address in dccm per pipe stage
input logic addr_in_dccm_m,
addr_in_dccm_r, // address in dccm per pipe stage
input logic addr_in_pic_r, // address in pic per pipe stage
input logic lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
input logic lsu_raw_fwd_lo_r,
lsu_raw_fwd_hi_r,
input logic lsu_commit_r, // lsu instruction in r commits
input logic ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
input logic ldst_dual_m,
ldst_dual_r, // load/store is unaligned at 32 bit boundary per pipe stage
// lsu address down the pipe
input logic [31:0] lsu_addr_d,
input logic [ 31:0] lsu_addr_d,
input logic [pt.DCCM_BITS-1:0] lsu_addr_m,
input logic [31:0] lsu_addr_r,
input logic [ 31:0] lsu_addr_r,
// lsu address down the pipe - needed to check unaligned
input logic [pt.DCCM_BITS-1:0] end_addr_d,
@ -69,7 +71,7 @@ import el2_pkg::*;
input logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any, // stbuf address (aligned)
input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any, // the read out from stbuf
input logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any, // the encoded data with ECC bits
input logic [ pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any, // the encoded data with ECC bits
input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m, // stbuf fowarding to load
input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m, // stbuf fowarding to load
input logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m, // stbuf fowarding to load
@ -89,8 +91,8 @@ import el2_pkg::*;
input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r, // corrected dccm data
input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff, // corrected dccm data
input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, // corrected dccm data
input logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, // the encoded data with ECC bits
input logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff, // the encoded data with ECC bits
input logic [ pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, // the encoded data with ECC bits
input logic [ pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff, // the encoded data with ECC bits
output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // data from the dccm
output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // data from the dccm
@ -128,7 +130,7 @@ import el2_pkg::*;
output logic dccm_dma_rvalid, // dccm serviving the dma load
output logic dccm_dma_ecc_error, // DMA load had ecc error
output logic [2:0] dccm_dma_rtag, // DMA return tag
output logic [ 2:0] dccm_dma_rtag, // DMA return tag
output logic [63:0] dccm_dma_rdata, // dccm data to dma request
// DCCM ports
@ -165,7 +167,7 @@ import el2_pkg::*;
logic ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff;
logic lsu_double_ecc_error_r_ff;
logic [pt.DCCM_BITS-1:0] ld_sec_addr_lo_r_ff, ld_sec_addr_hi_r_ff;
logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r_in, store_data_hi_r_in ;
logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r_in, store_data_hi_r_in;
logic [63:0] picm_rd_data_m;
logic dccm_wr_bypass_d_m_hi, dccm_wr_bypass_d_r_hi;
@ -173,14 +175,14 @@ import el2_pkg::*;
logic kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
// byte_en flowing down
logic [3:0] store_byteen_m ,store_byteen_r;
logic [3:0] store_byteen_m, store_byteen_r;
logic [7:0] store_byteen_ext_m, store_byteen_ext_r;
if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
if (pt.LOAD_TO_USE_PLUS1 == 1) begin : L2U_Plus1_1
logic [63:0] lsu_rdata_r, lsu_rdata_corr_r;
logic [63:0] dccm_rdata_r, dccm_rdata_corr_r;
logic [63:0] stbuf_fwddata_r;
logic [7:0] stbuf_fwdbyteen_r;
logic [ 7:0] stbuf_fwdbyteen_r;
logic [31:0] stbuf_fwddata_lo_r, stbuf_fwddata_hi_r;
logic [3:0] stbuf_fwdbyteen_lo_r, stbuf_fwdbyteen_hi_r;
logic [31:0] lsu_rdata_lo_r, lsu_rdata_hi_r;
@ -197,34 +199,72 @@ import el2_pkg::*;
assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> 8*lsu_addr_r[1:0];
assign picm_rd_data_r[63:32] = picm_rd_data_r[31:0];
assign dccm_rdata_r[63:0] = {dccm_rdata_hi_r[31:0],dccm_rdata_lo_r[31:0]};
assign dccm_rdata_corr_r[63:0] = {sec_data_hi_r[31:0],sec_data_lo_r[31:0]};
assign dccm_rdata_r[63:0] = {dccm_rdata_hi_r[31:0], dccm_rdata_lo_r[31:0]};
assign dccm_rdata_corr_r[63:0] = {sec_data_hi_r[31:0], sec_data_lo_r[31:0]};
assign stbuf_fwddata_r[63:0] = {stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]};
assign stbuf_fwdbyteen_r[7:0] = {stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]};
assign stbuf_fwddata_en = (|stbuf_fwdbyteen_hi_m[3:0]) | (|stbuf_fwdbyteen_lo_m[3:0]) | clk_override;
for (genvar i=0; i<8; i++) begin: GenDMAData
for (genvar i = 0; i < 8; i++) begin : GenDMAData
assign lsu_rdata_corr_r[(8*i)+7:8*i] = stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8*i)+7:8*i] :
(addr_in_pic_r ? picm_rd_data_r[(8*i)+7:8*i] : ({8{addr_in_dccm_r}} & dccm_rdata_corr_r[(8*i)+7:8*i]));
assign lsu_rdata_r[(8*i)+7:8*i] = stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8*i)+7:8*i] :
(addr_in_pic_r ? picm_rd_data_r[(8*i)+7:8*i] : ({8{addr_in_dccm_r}} & dccm_rdata_r[(8*i)+7:8*i]));
end
rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_hi_r_ff (.*, .din(dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(dccm_rdata_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en((lsu_dccm_rden_m & ldst_dual_m) | clk_override));
rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_lo_r_ff (.*, .din(dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(dccm_rdata_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_dccm_rden_m | clk_override));
rvdffe #(2*pt.DCCM_ECC_WIDTH) dccm_data_ecc_r_ff (.*, .din({dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0]}),
.dout({dccm_data_ecc_hi_r[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_r[pt.DCCM_ECC_WIDTH-1:0]}), .en(lsu_dccm_rden_m | clk_override));
rvdff #(8) stbuf_fwdbyteen_ff (.*, .din({stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}), .dout({stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}), .clk(lsu_c2_r_clk));
rvdffe #(64) stbuf_fwddata_ff (.*, .din({stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}), .dout({stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}), .en(stbuf_fwddata_en));
rvdffe #(32) picm_rddata_rff (.*, .din(picm_rd_data_m[31:0]), .dout(picm_rd_data_r[31:0]), .en(addr_in_pic_m | clk_override));
rvdff #(3) dma_mem_tag_rff (.*, .din(dma_mem_tag_m[2:0]), .dout(dma_mem_tag_r[2:0]), .clk(lsu_c1_r_clk));
rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_hi_r_ff (
.*,
.din (dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0]),
.dout(dccm_rdata_hi_r[pt.DCCM_DATA_WIDTH-1:0]),
.en ((lsu_dccm_rden_m & ldst_dual_m) | clk_override)
);
rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_lo_r_ff (
.*,
.din (dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0]),
.dout(dccm_rdata_lo_r[pt.DCCM_DATA_WIDTH-1:0]),
.en (lsu_dccm_rden_m | clk_override)
);
rvdffe #(2 * pt.DCCM_ECC_WIDTH) dccm_data_ecc_r_ff (
.*,
.din({
dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0]
}),
.dout({
dccm_data_ecc_hi_r[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_r[pt.DCCM_ECC_WIDTH-1:0]
}),
.en(lsu_dccm_rden_m | clk_override)
);
rvdff #(8) stbuf_fwdbyteen_ff (
.*,
.din ({stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}),
.dout({stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}),
.clk (lsu_c2_r_clk)
);
rvdffe #(64) stbuf_fwddata_ff (
.*,
.din ({stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}),
.dout({stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}),
.en (stbuf_fwddata_en)
);
rvdffe #(32) picm_rddata_rff (
.*,
.din (picm_rd_data_m[31:0]),
.dout(picm_rd_data_r[31:0]),
.en (addr_in_pic_m | clk_override)
);
rvdff #(3) dma_mem_tag_rff (
.*,
.din (dma_mem_tag_m[2:0]),
.dout(dma_mem_tag_r[2:0]),
.clk (lsu_c1_r_clk)
);
end else begin: L2U_Plus1_0
end else begin : L2U_Plus1_0
logic [63:0] lsu_rdata_m, lsu_rdata_corr_m;
logic [63:0] dccm_rdata_m, dccm_rdata_corr_m;
logic [63:0] stbuf_fwddata_m;
logic [7:0] stbuf_fwdbyteen_m;
logic [ 7:0] stbuf_fwdbyteen_m;
logic [63:32] lsu_ld_data_m_nc, lsu_ld_data_corr_m_nc;
logic [31:0] lsu_ld_data_corr_m;
@ -235,12 +275,12 @@ import el2_pkg::*;
assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0];
assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0];
assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0],dccm_rdata_lo_m[31:0]};
assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0],sec_data_lo_m[31:0]};
assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0], dccm_rdata_lo_m[31:0]};
assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0], sec_data_lo_m[31:0]};
assign stbuf_fwddata_m[63:0] = {stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]};
assign stbuf_fwdbyteen_m[7:0] = {stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]};
for (genvar i=0; i<8; i++) begin: GenLoop
for (genvar i = 0; i < 8; i++) begin : GenLoop
assign lsu_rdata_corr_m[(8*i)+7:8*i] = stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8*i)+7:8*i] :
(addr_in_pic_m ? picm_rd_data_m[(8*i)+7:8*i] : ({8{addr_in_dccm_m}} & dccm_rdata_corr_m[(8*i)+7:8*i]));
@ -248,7 +288,12 @@ import el2_pkg::*;
(addr_in_pic_m ? picm_rd_data_m[(8*i)+7:8*i] : ({8{addr_in_dccm_m}} & dccm_rdata_m[(8*i)+7:8*i]));
end
rvdffe #(32) lsu_ld_data_corr_rff(.*, .din(lsu_ld_data_corr_m[31:0]), .dout(lsu_ld_data_corr_r[31:0]), .en((lsu_pkt_m.valid & lsu_pkt_m.load & (addr_in_pic_m | addr_in_dccm_m)) | clk_override));
rvdffe #(32) lsu_ld_data_corr_rff (
.*,
.din (lsu_ld_data_corr_m[31:0]),
.dout(lsu_ld_data_corr_r[31:0]),
.en ((lsu_pkt_m.valid & lsu_pkt_m.load & (addr_in_pic_m | addr_in_dccm_m)) | clk_override)
);
end
assign kill_ecc_corr_lo_r = (((lsu_addr_d[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2]) | (end_addr_d[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2])) & lsu_pkt_d.valid & lsu_pkt_d.store & lsu_pkt_d.dma & addr_in_dccm_d) |
@ -306,7 +351,7 @@ import el2_pkg::*;
({4{lsu_pkt_r.word}} & 4'b1111));
assign store_byteen_ext_m[7:0] = {4'b0,store_byteen_m[3:0]} << lsu_addr_m[1:0]; // The packet in m
assign store_byteen_ext_r[7:0] = {4'b0,store_byteen_r[3:0]} << lsu_addr_r[1:0];
assign store_byteen_ext_r[7:0] = {4'b0, store_byteen_r[3:0]} << lsu_addr_r[1:0];
@ -317,7 +362,7 @@ import el2_pkg::*;
assign dccm_wr_bypass_d_r_hi = (stbuf_addr_any[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2]) & addr_in_dccm_r;
if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U1_Plus1_1
if (pt.LOAD_TO_USE_PLUS1 == 1) begin : L2U1_Plus1_1
logic dccm_wren_Q;
logic [31:0] dccm_wr_data_Q;
logic dccm_wr_bypass_d_m_lo_Q, dccm_wr_bypass_d_m_hi_Q;
@ -325,7 +370,7 @@ import el2_pkg::*;
assign {store_data_pre_hi_r[31:0], store_data_pre_lo_r[31:0]} = {32'b0,store_data_r[31:0]} << 8*lsu_addr_r[1:0];
for (genvar i=0; i<4; i++) begin
for (genvar i = 0; i < 4; i++) begin
assign store_data_lo_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i] ? store_data_pre_lo_r[(8*i)+7:(8*i)] : ((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_lo_r[(8*i)+7:(8*i)]);
assign store_data_hi_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i+4] ? store_data_pre_hi_r[(8*i)+7:(8*i)] : ((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_hi_r[(8*i)+7:(8*i)]);
@ -335,19 +380,45 @@ import el2_pkg::*;
((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_hi_r[(8*i)+7:(8*i)]));
end
rvdff #(1) dccm_wren_ff (.*, .din(lsu_stbuf_commit_any), .dout(dccm_wren_Q), .clk(lsu_free_c2_clk)); // ECC load errors writing to dccm shouldn't fwd to stores in pipe
rvdffe #(32) dccm_wrdata_ff (.*, .din(stbuf_data_any[31:0]), .dout(dccm_wr_data_Q[31:0]), .en(lsu_stbuf_commit_any | clk_override), .clk(clk));
rvdff #(1) dccm_wrbyp_dm_loff (.*, .din(dccm_wr_bypass_d_m_lo), .dout(dccm_wr_bypass_d_m_lo_Q), .clk(lsu_free_c2_clk));
rvdff #(1) dccm_wrbyp_dm_hiff (.*, .din(dccm_wr_bypass_d_m_hi), .dout(dccm_wr_bypass_d_m_hi_Q), .clk(lsu_free_c2_clk));
rvdff #(32) store_data_rff (.*, .din(store_data_m[31:0]), .dout(store_data_r[31:0]), .clk(lsu_store_c1_r_clk));
rvdff #(1) dccm_wren_ff (
.*,
.din (lsu_stbuf_commit_any),
.dout(dccm_wren_Q),
.clk (lsu_free_c2_clk)
); // ECC load errors writing to dccm shouldn't fwd to stores in pipe
rvdffe #(32) dccm_wrdata_ff (
.*,
.din (stbuf_data_any[31:0]),
.dout(dccm_wr_data_Q[31:0]),
.en (lsu_stbuf_commit_any | clk_override),
.clk (clk)
);
rvdff #(1) dccm_wrbyp_dm_loff (
.*,
.din (dccm_wr_bypass_d_m_lo),
.dout(dccm_wr_bypass_d_m_lo_Q),
.clk (lsu_free_c2_clk)
);
rvdff #(1) dccm_wrbyp_dm_hiff (
.*,
.din (dccm_wr_bypass_d_m_hi),
.dout(dccm_wr_bypass_d_m_hi_Q),
.clk (lsu_free_c2_clk)
);
rvdff #(32) store_data_rff (
.*,
.din (store_data_m[31:0]),
.dout(store_data_r[31:0]),
.clk (lsu_store_c1_r_clk)
);
end else begin: L2U1_Plus1_0
end else begin : L2U1_Plus1_0
logic [31:0] store_data_hi_m, store_data_lo_m;
logic [63:0] store_data_mask;
assign {store_data_hi_m[31:0] , store_data_lo_m[31:0]} = {32'b0,store_data_m[31:0]} << 8*lsu_addr_m[1:0];
for (genvar i=0; i<4; i++) begin
for (genvar i = 0; i < 4; i++) begin
assign store_data_hi_r_in[(8*i)+7:(8*i)] = store_byteen_ext_m[i+4] ? store_data_hi_m[(8*i)+7:(8*i)] :
((lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi) ? stbuf_data_any[(8*i)+7:(8*i)] : sec_data_hi_m[(8*i)+7:(8*i)]);
assign store_data_lo_r_in[(8*i)+7:(8*i)] = store_byteen_ext_m[i] ? store_data_lo_m[(8*i)+7:(8*i)] :
@ -357,13 +428,24 @@ import el2_pkg::*;
assign store_datafn_hi_r[(8*i)+7:(8*i)] = (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & ~store_byteen_ext_r[i+4]) ? stbuf_data_any[(8*i)+7:(8*i)] : store_data_hi_r[(8*i)+7:(8*i)];
end // for (genvar i=0; i<BYTE_WIDTH; i++)
for (genvar i=0; i<4; i++) begin
for (genvar i = 0; i < 4; i++) begin
assign store_data_mask[(8*i)+7:(8*i)] = {8{store_byteen_r[i]}};
end
assign store_data_r[31:0] = 32'({store_data_hi_r[31:0],store_data_lo_r[31:0]} >> 8*lsu_addr_r[1:0]) & store_data_mask[31:0];
rvdffe #(pt.DCCM_DATA_WIDTH) store_data_hi_rff (.*, .din(store_data_hi_r_in[pt.DCCM_DATA_WIDTH-1:0]), .dout(store_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en((ldst_dual_m & lsu_pkt_m.valid & lsu_pkt_m.store) | clk_override), .clk(clk));
rvdff #(pt.DCCM_DATA_WIDTH) store_data_lo_rff (.*, .din(store_data_lo_r_in[pt.DCCM_DATA_WIDTH-1:0]), .dout(store_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .clk(lsu_store_c1_r_clk));
rvdffe #(pt.DCCM_DATA_WIDTH) store_data_hi_rff (
.*,
.din (store_data_hi_r_in[pt.DCCM_DATA_WIDTH-1:0]),
.dout(store_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]),
.en ((ldst_dual_m & lsu_pkt_m.valid & lsu_pkt_m.store) | clk_override),
.clk (clk)
);
rvdff #(pt.DCCM_DATA_WIDTH) store_data_lo_rff (
.*,
.din (store_data_lo_r_in[pt.DCCM_DATA_WIDTH-1:0]),
.dout(store_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]),
.clk (lsu_store_c1_r_clk)
);
end
@ -384,22 +466,59 @@ import el2_pkg::*;
assign picm_wr_data[31:0] = dma_pic_wen ? dma_mem_wdata[31:0] : store_datafn_lo_r[31:0];
assign picm_mask_data_m[31:0] = picm_rd_data_m[31:0];
assign picm_rd_data_m[63:0] = {picm_rd_data[31:0],picm_rd_data[31:0]};
assign picm_rd_data_m[63:0] = {picm_rd_data[31:0], picm_rd_data[31:0]};
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
rvdff #(1) dccm_rden_mff (.*, .din(lsu_dccm_rden_d), .dout(lsu_dccm_rden_m), .clk(lsu_c2_m_clk));
rvdff #(1) dccm_rden_rff (.*, .din(lsu_dccm_rden_m), .dout(lsu_dccm_rden_r), .clk(lsu_c2_r_clk));
if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
rvdff #(1) dccm_rden_mff (
.*,
.din (lsu_dccm_rden_d),
.dout(lsu_dccm_rden_m),
.clk (lsu_c2_m_clk)
);
rvdff #(1) dccm_rden_rff (
.*,
.din (lsu_dccm_rden_m),
.dout(lsu_dccm_rden_r),
.clk (lsu_c2_r_clk)
);
// ECC correction flops since dccm write happens next cycle
// We are writing to dccm in r+1 for ecc correction since fast_int needs to be blocked in decode - 1. We can probably write in r for plus0 configuration since we know ecc error in M.
// In that case these (_ff) flops are needed only in plus1 configuration
rvdff #(1) ld_double_ecc_error_rff (.*, .din(lsu_double_ecc_error_r), .dout(lsu_double_ecc_error_r_ff), .clk(lsu_free_c2_clk));
rvdff #(1) ld_single_ecc_error_hi_rff (.*, .din(ld_single_ecc_error_hi_r_ns), .dout(ld_single_ecc_error_hi_r_ff), .clk(lsu_free_c2_clk));
rvdff #(1) ld_single_ecc_error_lo_rff (.*, .din(ld_single_ecc_error_lo_r_ns), .dout(ld_single_ecc_error_lo_r_ff), .clk(lsu_free_c2_clk));
rvdffe #(pt.DCCM_BITS) ld_sec_addr_hi_rff (.*, .din(end_addr_r[pt.DCCM_BITS-1:0]), .dout(ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk));
rvdffe #(pt.DCCM_BITS) ld_sec_addr_lo_rff (.*, .din(lsu_addr_r[pt.DCCM_BITS-1:0]), .dout(ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk));
rvdff #(1) ld_double_ecc_error_rff (
.*,
.din (lsu_double_ecc_error_r),
.dout(lsu_double_ecc_error_r_ff),
.clk (lsu_free_c2_clk)
);
rvdff #(1) ld_single_ecc_error_hi_rff (
.*,
.din (ld_single_ecc_error_hi_r_ns),
.dout(ld_single_ecc_error_hi_r_ff),
.clk (lsu_free_c2_clk)
);
rvdff #(1) ld_single_ecc_error_lo_rff (
.*,
.din (ld_single_ecc_error_lo_r_ns),
.dout(ld_single_ecc_error_lo_r_ff),
.clk (lsu_free_c2_clk)
);
rvdffe #(pt.DCCM_BITS) ld_sec_addr_hi_rff (
.*,
.din (end_addr_r[pt.DCCM_BITS-1:0]),
.dout(ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0]),
.en (ld_single_ecc_error_r | clk_override),
.clk (clk)
);
rvdffe #(pt.DCCM_BITS) ld_sec_addr_lo_rff (
.*,
.din (lsu_addr_r[pt.DCCM_BITS-1:0]),
.dout(ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0]),
.en (ld_single_ecc_error_r | clk_override),
.clk (clk)
);
end else begin: Gen_dccm_disable
end else begin : Gen_dccm_disable
assign lsu_dccm_rden_m = '0;
assign lsu_dccm_rden_r = '0;

19
Flow/design/lsu/el2_lsu_dccm_mem.sv
View File

@ -27,17 +27,14 @@
// //********************************************************************************
`define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1), \
.RME(dccm_ext_in_pkt[i].RME), \
.RM(dccm_ext_in_pkt[i].RM), \
.LS(dccm_ext_in_pkt[i].LS), \
.DS(dccm_ext_in_pkt[i].DS), \
.SD(dccm_ext_in_pkt[i].SD), \
.TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM), \
.BC1(dccm_ext_in_pkt[i].BC1), \
.BC2(dccm_ext_in_pkt[i].BC2), \
`define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1),\
.RME(dccm_ext_in_pkt[i].RME),\
.RM(dccm_ext_in_pkt[i].RM),\
.LS(dccm_ext_in_pkt[i].LS),\
.DS(dccm_ext_in_pkt[i].DS),\
.SD(dccm_ext_in_pkt[i].SD),\
.TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM),\
.BC1(dccm_ext_in_pkt[i].BC1),.BC2(dccm_ext_in_pkt[i].BC2),
module el2_lsu_dccm_mem
import el2_pkg::*;

113
Flow/design/lsu/el2_lsu_ecc.sv
View File

@ -26,11 +26,10 @@
//
//********************************************************************************
module el2_lsu_ecc
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic lsu_c2_r_clk, // clock
input logic clk_override, // Override non-functional clock gating
@ -45,12 +44,12 @@ import el2_pkg::*;
input logic lsu_dccm_rden_r, // dccm rden
input logic addr_in_dccm_r, // address in dccm
input logic [pt.DCCM_BITS-1:0] lsu_addr_r, // start address
input logic [pt.DCCM_BITS-1:0] end_addr_r, // end address
input logic [ pt.DCCM_BITS-1:0] lsu_addr_r, // start address
input logic [ pt.DCCM_BITS-1:0] end_addr_r, // end address
input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r, // data from the dccm
input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r, // data from the dccm
input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc
input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r, // data from the dccm + ecc
input logic [ pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc
input logic [ pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r, // data from the dccm + ecc
output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r, // corrected dccm data R-stage
output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r, // corrected dccm data R-stage
output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff, // corrected dccm data R+1 stage
@ -60,12 +59,12 @@ import el2_pkg::*;
input logic ld_single_ecc_error_r_ff, // ld has a single ecc error
input logic lsu_dccm_rden_m, // dccm rden
input logic addr_in_dccm_m, // address in dccm
input logic [pt.DCCM_BITS-1:0] lsu_addr_m, // start address
input logic [pt.DCCM_BITS-1:0] end_addr_m, // end address
input logic [ pt.DCCM_BITS-1:0] lsu_addr_m, // start address
input logic [ pt.DCCM_BITS-1:0] end_addr_m, // end address
input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // raw data from mem
input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // raw data from mem
input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // ecc read out from mem
input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m, // ecc read out from mem
input logic [ pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // ecc read out from mem
input logic [ pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m, // ecc read out from mem
output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_m, // corrected dccm data M-stage
output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_m, // corrected dccm data M-stage
@ -87,7 +86,7 @@ import el2_pkg::*;
output logic lsu_single_ecc_error_m, // or of the 2
output logic lsu_double_ecc_error_m // double error detected
);
);
logic is_ldst_r;
logic is_ldst_hi_any, is_ldst_lo_any;
@ -105,7 +104,7 @@ import el2_pkg::*;
logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
if (pt.LOAD_TO_USE_PLUS1 == 1) begin : L2U_Plus1_1
logic ldst_dual_m, ldst_dual_r;
logic is_ldst_m;
logic is_ldst_hi_r, is_ldst_lo_r;
@ -132,7 +131,7 @@ import el2_pkg::*;
assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r;
assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r;
end else begin: L2U_Plus1_0
end else begin : L2U_Plus1_0
logic ldst_dual_m;
logic is_ldst_m;
@ -159,12 +158,50 @@ import el2_pkg::*;
assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m;
// Flops
rvdff #(1) lsu_single_ecc_err_r (.din(lsu_single_ecc_error_m), .dout(lsu_single_ecc_error_r), .clk(lsu_c2_r_clk), .*);
rvdff #(1) lsu_double_ecc_err_r (.din(lsu_double_ecc_error_m), .dout(lsu_double_ecc_error_r), .clk(lsu_c2_r_clk), .*);
rvdff #(.WIDTH(1)) ldst_sec_lo_rff (.din(single_ecc_error_lo_any), .dout(single_ecc_error_lo_r), .clk(lsu_c2_r_clk), .*);
rvdff #(.WIDTH(1)) ldst_sec_hi_rff (.din(single_ecc_error_hi_any), .dout(single_ecc_error_hi_r), .clk(lsu_c2_r_clk), .*);
rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rff (.din(sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);
rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rff (.din(sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);
rvdff #(1) lsu_single_ecc_err_r (
.din (lsu_single_ecc_error_m),
.dout(lsu_single_ecc_error_r),
.clk (lsu_c2_r_clk),
.*
);
rvdff #(1) lsu_double_ecc_err_r (
.din (lsu_double_ecc_error_m),
.dout(lsu_double_ecc_error_r),
.clk (lsu_c2_r_clk),
.*
);
rvdff #(
.WIDTH(1)
) ldst_sec_lo_rff (
.din (single_ecc_error_lo_any),
.dout(single_ecc_error_lo_r),
.clk (lsu_c2_r_clk),
.*
);
rvdff #(
.WIDTH(1)
) ldst_sec_hi_rff (
.din (single_ecc_error_hi_any),
.dout(single_ecc_error_hi_r),
.clk (lsu_c2_r_clk),
.*
);
rvdffe #(
.WIDTH(pt.DCCM_DATA_WIDTH)
) sec_data_hi_rff (
.din (sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0]),
.dout(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]),
.en (lsu_single_ecc_error_m | clk_override),
.*
);
rvdffe #(
.WIDTH(pt.DCCM_DATA_WIDTH)
) sec_data_lo_rff (
.din (sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0]),
.dout(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]),
.en (lsu_single_ecc_error_m | clk_override),
.*
);
end
@ -179,18 +216,18 @@ import el2_pkg::*;
assign dma_dccm_wdata_ecc_lo[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];
// Instantiate ECC blocks
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
//Detect/Repair for Hi
rvecc_decode lsu_ecc_decode_hi (
// Inputs
.en(is_ldst_hi_any),
.sed_ded (1'b0), // 1 : means only detection
.sed_ded(1'b0), // 1 : means only detection
.din(dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0]),
.ecc_in(dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0]),
// Outputs
.dout(sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0]),
.ecc_out (ecc_out_hi_nc[6:0]),
.ecc_out(ecc_out_hi_nc[6:0]),
.single_ecc_error(single_ecc_error_hi_any),
.double_ecc_error(double_ecc_error_hi_any),
.*
@ -200,12 +237,12 @@ import el2_pkg::*;
rvecc_decode lsu_ecc_decode_lo (
// Inputs
.en(is_ldst_lo_any),
.sed_ded (1'b0), // 1 : means only detection
.din(dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] ),
.sed_ded(1'b0), // 1 : means only detection
.din(dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0]),
.ecc_in(dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),
// Outputs
.dout(sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0]),
.ecc_out (ecc_out_lo_nc[6:0]),
.ecc_out(ecc_out_lo_nc[6:0]),
.single_ecc_error(single_ecc_error_lo_any),
.double_ecc_error(double_ecc_error_lo_any),
.*
@ -225,7 +262,7 @@ import el2_pkg::*;
.ecc_out(dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),
.*
);
end else begin: Gen_dccm_disable // block: Gen_dccm_enable
end else begin : Gen_dccm_disable // block: Gen_dccm_enable
assign sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0] = '0;
assign sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0] = '0;
assign single_ecc_error_hi_any = '0;
@ -234,8 +271,24 @@ import el2_pkg::*;
assign double_ecc_error_lo_any = '0;
end
rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rplus1ff (.din(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);
rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rplus1ff (.din(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);
rvdffe #(
.WIDTH(pt.DCCM_DATA_WIDTH)
) sec_data_hi_rplus1ff (
.din (sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]),
.dout(sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]),
.en (ld_single_ecc_error_r | clk_override),
.clk (clk),
.*
);
rvdffe #(
.WIDTH(pt.DCCM_DATA_WIDTH)
) sec_data_lo_rplus1ff (
.din (sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]),
.dout(sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]),
.en (ld_single_ecc_error_r | clk_override),
.clk (clk),
.*
);
endmodule // el2_lsu_ecc

263
Flow/design/lsu/el2_lsu_lsc_ctl.sv
View File

@ -26,10 +26,10 @@
//
//********************************************************************************
module el2_lsu_lsc_ctl
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
`include "el2_param.vh"
) (
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
@ -82,11 +82,11 @@ import el2_pkg::*;
output logic lsu_exc_m, // Access or misaligned fault
output logic is_sideeffects_m, // is sideffects space
output logic lsu_commit_r, // lsu instruction in r commits
output logic lsu_single_ecc_error_incr,// LSU inc SB error counter
output logic lsu_single_ecc_error_incr, // LSU inc SB error counter
output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet
output logic [31:1] lsu_fir_addr, // fast interrupt address
output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup
output logic [ 1:0] lsu_fir_error, // Error during fast interrupt lookup
// address in dccm/pic/external per pipe stage
output logic addr_in_dccm_d,
@ -102,7 +102,7 @@ import el2_pkg::*;
// DMA slave
input logic dma_dccm_req,
input logic [31:0] dma_mem_addr,
input logic [2:0] dma_mem_sz,
input logic [ 2:0] dma_mem_sz,
input logic dma_mem_write,
input logic [63:0] dma_mem_wdata,
@ -113,7 +113,7 @@ import el2_pkg::*;
input logic scan_mode // Scan mode
);
);
logic [31:3] end_addr_pre_m, end_addr_pre_r;
logic [31:0] full_addr_d;
@ -123,7 +123,7 @@ import el2_pkg::*;
logic [31:0] rs1_d;
logic [11:0] offset_d;
logic [12:0] end_addr_offset_d;
logic [2:0] addr_offset_d;
logic [ 2:0] addr_offset_d;
logic [63:0] dma_mem_wdata_shifted;
logic addr_external_d;
@ -153,7 +153,8 @@ import el2_pkg::*;
assign rs1_d[31:0] = (lsu_pkt_d.load_ldst_bypass_d) ? lsu_result_m[31:0] : rs1_d_raw[31:0];
// generate the ls address
rvlsadder lsadder (.rs1(rs1_d[31:0]),
rvlsadder lsadder (
.rs1(rs1_d[31:0]),
.offset(offset_d[11:0]),
.dout(full_addr_d[31:0])
);
@ -161,14 +162,14 @@ import el2_pkg::*;
// Module to generate the memory map of the address
el2_lsu_addrcheck addrcheck (
.start_addr_d(full_addr_d[31:0]),
.end_addr_d(full_end_addr_d[31:0]),
.end_addr_d (full_end_addr_d[31:0]),
.rs1_region_d(rs1_d[31:28]),
.*
);
// Calculate start/end address for load/store
assign addr_offset_d[2:0] = ({3{lsu_pkt_d.half}} & 3'b01) | ({3{lsu_pkt_d.word}} & 3'b11) | ({3{lsu_pkt_d.dword}} & 3'b111);
assign end_addr_offset_d[12:0] = {offset_d[11],offset_d[11:0]} + {9'b0,addr_offset_d[2:0]};
assign end_addr_offset_d[12:0] = {offset_d[11], offset_d[11:0]} + {9'b0, addr_offset_d[2:0]};
assign full_end_addr_d[31:0] = rs1_d[31:0] + {{19{end_addr_offset_d[12]}},end_addr_offset_d[12:0]};
assign end_addr_d[31:0] = full_end_addr_d[31:0];
assign lsu_exc_m = access_fault_m | misaligned_fault_m;
@ -176,7 +177,7 @@ import el2_pkg::*;
// Goes to TLU to increment the ECC error counter
assign lsu_single_ecc_error_incr = (lsu_single_ecc_error_r & ~lsu_double_ecc_error_r) & (lsu_commit_r | lsu_pkt_r.dma) & lsu_pkt_r.valid;
if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
if (pt.LOAD_TO_USE_PLUS1 == 1) begin : L2U_Plus1_1
logic access_fault_r, misaligned_fault_r;
logic [3:0] exc_mscause_r;
logic fir_dccm_access_error_r, fir_nondccm_access_error_r;
@ -191,13 +192,38 @@ import el2_pkg::*;
assign lsu_fir_error[1:0] = fir_nondccm_access_error_r ? 2'b11 : (fir_dccm_access_error_r ? 2'b10 : ((lsu_pkt_r.fast_int & lsu_double_ecc_error_r) ? 2'b01 : 2'b00));
rvdff #(1) access_fault_rff (.din(access_fault_m), .dout(access_fault_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) misaligned_fault_rff (.din(misaligned_fault_m), .dout(misaligned_fault_r), .clk(lsu_c1_r_clk), .*);
rvdff #(4) exc_mscause_rff (.din(exc_mscause_m[3:0]), .dout(exc_mscause_r[3:0]), .clk(lsu_c1_r_clk), .*);
rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_m), .dout(fir_dccm_access_error_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_m), .dout(fir_nondccm_access_error_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) access_fault_rff (
.din (access_fault_m),
.dout(access_fault_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) misaligned_fault_rff (
.din (misaligned_fault_m),
.dout(misaligned_fault_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(4) exc_mscause_rff (
.din (exc_mscause_m[3:0]),
.dout(exc_mscause_r[3:0]),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) fir_dccm_access_error_mff (
.din (fir_dccm_access_error_m),
.dout(fir_dccm_access_error_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) fir_nondccm_access_error_mff (
.din (fir_nondccm_access_error_m),
.dout(fir_nondccm_access_error_r),
.clk (lsu_c1_r_clk),
.*
);
end else begin: L2U_Plus1_0
end else begin : L2U_Plus1_0
logic [1:0] lsu_fir_error_m;
// Generate exception packet
@ -210,10 +236,32 @@ import el2_pkg::*;
assign lsu_fir_error_m[1:0] = fir_nondccm_access_error_m ? 2'b11 : (fir_dccm_access_error_m ? 2'b10 : ((lsu_pkt_m.fast_int & lsu_double_ecc_error_m) ? 2'b01 : 2'b00));
rvdff #(1) lsu_exc_valid_rff (.*, .din(lsu_error_pkt_m.exc_valid), .dout(lsu_error_pkt_r.exc_valid), .clk(lsu_c2_r_clk));
rvdff #(1) lsu_single_ecc_error_rff(.*, .din(lsu_error_pkt_m.single_ecc_error), .dout(lsu_error_pkt_r.single_ecc_error), .clk(lsu_c2_r_clk));
rvdffe #($bits(el2_lsu_error_pkt_t)-2) lsu_error_pkt_rff (.*, .din(lsu_error_pkt_m[$bits(el2_lsu_error_pkt_t)-1:2]), .dout(lsu_error_pkt_r[$bits(el2_lsu_error_pkt_t)-1:2]), .en(lsu_error_pkt_m.exc_valid | lsu_error_pkt_m.single_ecc_error | clk_override));
rvdff #(2) lsu_fir_error_rff (.*, .din(lsu_fir_error_m[1:0]), .dout(lsu_fir_error[1:0]), .clk(lsu_c2_r_clk));
rvdff #(1) lsu_exc_valid_rff (
.*,
.din (lsu_error_pkt_m.exc_valid),
.dout(lsu_error_pkt_r.exc_valid),
.clk (lsu_c2_r_clk)
);
rvdff #(1) lsu_single_ecc_error_rff (
.*,
.din (lsu_error_pkt_m.single_ecc_error),
.dout(lsu_error_pkt_r.single_ecc_error),
.clk (lsu_c2_r_clk)
);
rvdffe #($bits(
el2_lsu_error_pkt_t
) - 2) lsu_error_pkt_rff (
.*,
.din (lsu_error_pkt_m[$bits(el2_lsu_error_pkt_t)-1:2]),
.dout(lsu_error_pkt_r[$bits(el2_lsu_error_pkt_t)-1:2]),
.en (lsu_error_pkt_m.exc_valid | lsu_error_pkt_m.single_ecc_error | clk_override)
);
rvdff #(2) lsu_fir_error_rff (
.*,
.din (lsu_fir_error_m[1:0]),
.dout(lsu_fir_error[1:0]),
.clk (lsu_c2_r_clk)
);
end
//Create DMA packet
@ -236,19 +284,43 @@ import el2_pkg::*;
lsu_pkt_d.valid = (lsu_p.valid & ~(flush_m_up & ~lsu_p.fast_int)) | dma_dccm_req;
lsu_pkt_m_in.valid = lsu_pkt_d.valid & ~(flush_m_up & ~lsu_pkt_d.dma);
lsu_pkt_r_in.valid = lsu_pkt_m.valid & ~(flush_m_up & ~lsu_pkt_m.dma) ;
lsu_pkt_r_in.valid = lsu_pkt_m.valid & ~(flush_m_up & ~lsu_pkt_m.dma);
end
// C2 clock for valid and C1 for other bits of packet
rvdff #(1) lsu_pkt_vldmff (.*, .din(lsu_pkt_m_in.valid), .dout(lsu_pkt_m.valid), .clk(lsu_c2_m_clk));
rvdff #(1) lsu_pkt_vldrff (.*, .din(lsu_pkt_r_in.valid), .dout(lsu_pkt_r.valid), .clk(lsu_c2_r_clk));
rvdff #(1) lsu_pkt_vldmff (
.*,
.din (lsu_pkt_m_in.valid),
.dout(lsu_pkt_m.valid),
.clk (lsu_c2_m_clk)
);
rvdff #(1) lsu_pkt_vldrff (
.*,
.din (lsu_pkt_r_in.valid),
.dout(lsu_pkt_r.valid),
.clk (lsu_c2_r_clk)
);
rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_mff (.*, .din(lsu_pkt_m_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_m[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_m_clk));
rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_rff (.*, .din(lsu_pkt_r_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_r[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_r_clk));
rvdff #($bits(
el2_lsu_pkt_t
) - 1) lsu_pkt_mff (
.*,
.din (lsu_pkt_m_in[$bits(el2_lsu_pkt_t)-1:1]),
.dout(lsu_pkt_m[$bits(el2_lsu_pkt_t)-1:1]),
.clk (lsu_c1_m_clk)
);
rvdff #($bits(
el2_lsu_pkt_t
) - 1) lsu_pkt_rff (
.*,
.din (lsu_pkt_r_in[$bits(el2_lsu_pkt_t)-1:1]),
.dout(lsu_pkt_r[$bits(el2_lsu_pkt_t)-1:1]),
.clk (lsu_c1_r_clk)
);
if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U1_Plus1_1
if (pt.LOAD_TO_USE_PLUS1 == 1) begin : L2U1_Plus1_1
logic [31:0] lsu_ld_datafn_r, lsu_ld_datafn_corr_r;
assign lsu_ld_datafn_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_r[31:0];
@ -268,7 +340,7 @@ import el2_pkg::*;
({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |
({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]);
end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1
end else begin : L2U1_Plus1_0 // block: L2U1_Plus1_1
logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;
assign lsu_ld_datafn_m[31:0] = addr_external_m ? bus_read_data_m[31:0] : lsu_ld_data_m[31:0];
@ -306,36 +378,131 @@ import el2_pkg::*;
assign store_data_m[31:0] = (picm_mask_data_m[31:0] | {32{~addr_in_pic_m}}) & ((lsu_pkt_m.store_data_bypass_m) ? lsu_result_m[31:0] : store_data_pre_m[31:0]);
rvdff #(32) sdmff (.*, .din(store_data_m_in[31:0]), .dout(store_data_pre_m[31:0]), .clk(lsu_store_c1_m_clk));
rvdff #(32) sdmff (
.*,
.din (store_data_m_in[31:0]),
.dout(store_data_pre_m[31:0]),
.clk (lsu_store_c1_m_clk)
);
rvdff #(32) samff (.*, .din(lsu_addr_d[31:0]), .dout(lsu_addr_m[31:0]), .clk(lsu_c1_m_clk));
rvdff #(32) sarff (.*, .din(lsu_addr_m[31:0]), .dout(lsu_addr_r[31:0]), .clk(lsu_c1_r_clk));
rvdff #(32) samff (
.*,
.din (lsu_addr_d[31:0]),
.dout(lsu_addr_m[31:0]),
.clk (lsu_c1_m_clk)
);
rvdff #(32) sarff (
.*,
.din (lsu_addr_m[31:0]),
.dout(lsu_addr_r[31:0]),
.clk (lsu_c1_r_clk)
);
assign end_addr_m[31:3] = ldst_dual_m ? end_addr_pre_m[31:3] : lsu_addr_m[31:3]; // This is for power saving
assign end_addr_r[31:3] = ldst_dual_r ? end_addr_pre_r[31:3] : lsu_addr_r[31:3]; // This is for power saving
rvdffe #(29) end_addr_hi_mff (.*, .din(end_addr_d[31:3]), .dout(end_addr_pre_m[31:3]), .en((lsu_pkt_d.valid & ldst_dual_d) | clk_override));
rvdffe #(29) end_addr_hi_rff (.*, .din(end_addr_m[31:3]), .dout(end_addr_pre_r[31:3]), .en((lsu_pkt_m.valid & ldst_dual_m) | clk_override));
rvdffe #(29) end_addr_hi_mff (
.*,
.din (end_addr_d[31:3]),
.dout(end_addr_pre_m[31:3]),
.en ((lsu_pkt_d.valid & ldst_dual_d) | clk_override)
);
rvdffe #(29) end_addr_hi_rff (
.*,
.din (end_addr_m[31:3]),
.dout(end_addr_pre_r[31:3]),
.en ((lsu_pkt_m.valid & ldst_dual_m) | clk_override)
);
rvdff #(3) end_addr_lo_mff (.*, .din(end_addr_d[2:0]), .dout(end_addr_m[2:0]), .clk(lsu_c1_m_clk));
rvdff #(3) end_addr_lo_rff (.*, .din(end_addr_m[2:0]), .dout(end_addr_r[2:0]), .clk(lsu_c1_r_clk));
rvdff #(3) end_addr_lo_mff (
.*,
.din (end_addr_d[2:0]),
.dout(end_addr_m[2:0]),
.clk (lsu_c1_m_clk)
);
rvdff #(3) end_addr_lo_rff (
.*,
.din (end_addr_m[2:0]),
.dout(end_addr_r[2:0]),
.clk (lsu_c1_r_clk)
);
rvdff #(1) addr_in_dccm_mff(.din(addr_in_dccm_d), .dout(addr_in_dccm_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) addr_in_dccm_rff(.din(addr_in_dccm_m), .dout(addr_in_dccm_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) addr_in_dccm_mff (
.din (addr_in_dccm_d),
.dout(addr_in_dccm_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) addr_in_dccm_rff (
.din (addr_in_dccm_m),
.dout(addr_in_dccm_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) addr_in_pic_mff(.din(addr_in_pic_d), .dout(addr_in_pic_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) addr_in_pic_rff(.din(addr_in_pic_m), .dout(addr_in_pic_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) addr_in_pic_mff (
.din (addr_in_pic_d),
.dout(addr_in_pic_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) addr_in_pic_rff (
.din (addr_in_pic_m),
.dout(addr_in_pic_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) addr_external_mff(.din(addr_external_d), .dout(addr_external_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) addr_external_rff(.din(addr_external_m), .dout(addr_external_r), .clk(lsu_c1_r_clk), .*);
rvdff #(1) addr_external_mff (
.din (addr_external_d),
.dout(addr_external_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) addr_external_rff (
.din (addr_external_m),
.dout(addr_external_r),
.clk (lsu_c1_r_clk),
.*
);
rvdff #(1) access_fault_mff (.din(access_fault_d), .dout(access_fault_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) misaligned_fault_mff (.din(misaligned_fault_d), .dout(misaligned_fault_m), .clk(lsu_c1_m_clk), .*);
rvdff #(4) exc_mscause_mff (.din(exc_mscause_d[3:0]), .dout(exc_mscause_m[3:0]), .clk(lsu_c1_m_clk), .*);
rvdff #(1) access_fault_mff (
.din (access_fault_d),
.dout(access_fault_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) misaligned_fault_mff (
.din (misaligned_fault_d),
.dout(misaligned_fault_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(4) exc_mscause_mff (
.din (exc_mscause_d[3:0]),
.dout(exc_mscause_m[3:0]),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_d), .dout(fir_dccm_access_error_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_d), .dout(fir_nondccm_access_error_m), .clk(lsu_c1_m_clk), .*);
rvdff #(1) fir_dccm_access_error_mff (
.din (fir_dccm_access_error_d),
.dout(fir_dccm_access_error_m),
.clk (lsu_c1_m_clk),
.*
);
rvdff #(1) fir_nondccm_access_error_mff (
.din (fir_nondccm_access_error_d),
.dout(fir_nondccm_access_error_m),
.clk (lsu_c1_m_clk),
.*
);
rvdffe #(32) bus_read_data_r_ff (.*, .din(bus_read_data_m[31:0]), .dout(bus_read_data_r[31:0]), .en(addr_external_m | clk_override));
rvdffe #(32) bus_read_data_r_ff (
.*,
.din (bus_read_data_m[31:0]),
.dout(bus_read_data_r[31:0]),
.en (addr_external_m | clk_override)
);
endmodule

185
Flow/design/lsu/el2_lsu_stbuf.sv
View File

@ -28,11 +28,10 @@
module el2_lsu_stbuf
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)
(
`include "el2_param.vh"
) (
input logic clk, // core clock
input logic rst_l, // reset
@ -51,7 +50,7 @@ import el2_pkg::*;
// Store Buffer output
output logic stbuf_reqvld_any, // stbuf is draining
output logic stbuf_reqvld_flushed_any, // Top entry is flushed
output logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any, // address
output logic [ pt.LSU_SB_BITS-1:0] stbuf_addr_any, // address
output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any, // stbuf data
input logic lsu_stbuf_commit_any, // pop the stbuf as it commite
@ -60,14 +59,16 @@ import el2_pkg::*;
output logic ldst_stbuf_reqvld_r, // needed for clocking
input logic [pt.LSU_SB_BITS-1:0] lsu_addr_d, // lsu address D-stage
input logic [31:0] lsu_addr_m, // lsu address M-stage
input logic [31:0] lsu_addr_r, // lsu address R-stage
input logic [ 31:0] lsu_addr_m, // lsu address M-stage
input logic [ 31:0] lsu_addr_r, // lsu address R-stage
input logic [pt.LSU_SB_BITS-1:0] end_addr_d, // lsu end address D-stage - needed to check unaligned
input logic [31:0] end_addr_m, // lsu end address M-stage - needed to check unaligned
input logic [31:0] end_addr_r, // lsu end address R-stage - needed to check unaligned
input logic ldst_dual_d, ldst_dual_m, ldst_dual_r,
input logic ldst_dual_d,
ldst_dual_m,
ldst_dual_r,
input logic addr_in_dccm_m, // address is in dccm
input logic addr_in_dccm_r, // address is in dccm
@ -92,21 +93,21 @@ import el2_pkg::*;
localparam DEPTH_LOG2 = $clog2(DEPTH);
// These are the fields in the store queue
logic [DEPTH-1:0] stbuf_vld;
logic [DEPTH-1:0] stbuf_dma_kill;
logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addr;
logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteen;
logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_data;
logic [ DEPTH-1:0] stbuf_vld;
logic [ DEPTH-1:0] stbuf_dma_kill;
logic [ DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addr;
logic [ DEPTH-1:0][ BYTE_WIDTH-1:0] stbuf_byteen;
logic [ DEPTH-1:0][ DATA_WIDTH-1:0] stbuf_data;
logic [DEPTH-1:0] sel_lo;
logic [DEPTH-1:0] stbuf_wr_en;
logic [DEPTH-1:0] stbuf_dma_kill_en;
logic [DEPTH-1:0] stbuf_reset;
logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_datain;
logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteenin;
logic [ DEPTH-1:0] sel_lo;
logic [ DEPTH-1:0] stbuf_wr_en;
logic [ DEPTH-1:0] stbuf_dma_kill_en;
logic [ DEPTH-1:0] stbuf_reset;
logic [ DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
logic [ DEPTH-1:0][ DATA_WIDTH-1:0] stbuf_datain;
logic [ DEPTH-1:0][ BYTE_WIDTH-1:0] stbuf_byteenin;
logic [7:0] store_byteen_ext_r;
logic [ 7:0] store_byteen_ext_r;
logic [BYTE_WIDTH-1:0] store_byteen_hi_r;
logic [BYTE_WIDTH-1:0] store_byteen_lo_r;
@ -130,7 +131,8 @@ import el2_pkg::*;
logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_pre_m, stbuf_fwdbyteen_lo_pre_m;
// logic to detect matching from the pipe - needed for store - load forwarding
logic [BYTE_WIDTH-1:0] ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
logic [BYTE_WIDTH-1:0]
ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
logic [BYTE_WIDTH-1:0] ld_byte_hit_lo, ld_byte_rhit_lo;
@ -139,11 +141,11 @@ import el2_pkg::*;
logic [BYTE_WIDTH-1:0] ldst_byteen_hi_r;
logic [BYTE_WIDTH-1:0] ldst_byteen_lo_r;
// byte_en flowing down
logic [7:0] ldst_byteen_r;
logic [7:0] ldst_byteen_ext_r;
logic [ 7:0] ldst_byteen_r;
logic [ 7:0] ldst_byteen_ext_r;
// fwd data through the pipe
logic [31:0] ld_fwddata_rpipe_lo;
logic [31:0] ld_fwddata_rpipe_hi;
logic [ 31:0] ld_fwddata_rpipe_lo;
logic [ 31:0] ld_fwddata_rpipe_hi;
// coalescing signals
logic [DEPTH-1:0] store_matchvec_lo_r, store_matchvec_hi_r;
@ -166,23 +168,31 @@ import el2_pkg::*;
assign ldst_stbuf_reqvld_r = ((lsu_commit_r | lsu_pkt_r.dma) & store_stbuf_reqvld_r);
// Store Buffer coalescing
for (genvar i=0; i<DEPTH; i++) begin: FindMatchEntry
assign store_matchvec_lo_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == lsu_addr_r[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & ~stbuf_reset[i];
assign store_matchvec_hi_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == end_addr_r[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & dual_stbuf_write_r & ~stbuf_reset[i];
end: FindMatchEntry
for (genvar i = 0; i < DEPTH; i++) begin : FindMatchEntry
assign store_matchvec_lo_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)] == lsu_addr_r[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & ~stbuf_reset[i];
assign store_matchvec_hi_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)] == end_addr_r[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & dual_stbuf_write_r & ~stbuf_reset[i];
end : FindMatchEntry
assign store_coalesce_lo_r = |store_matchvec_lo_r[DEPTH-1:0];
assign store_coalesce_hi_r = |store_matchvec_hi_r[DEPTH-1:0];
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
// Allocate new in this entry if :
// 1. wrptr, single allocate, lo did not coalesce
// 2. wrptr, double allocate, lo ^ hi coalesced
// 3. wrptr + 1, double alloacte, niether lo or hi coalesced
// Also update if there is a hi or a lo coalesce to this entry
// Store Buffer instantiation
for (genvar i=0; i<DEPTH; i++) begin: GenStBuf
for (genvar i = 0; i < DEPTH; i++) begin : GenStBuf
assign stbuf_wr_en[i] = ldst_stbuf_reqvld_r & (
( (i == WrPtr[DEPTH_LOG2-1:0]) & ~store_coalesce_lo_r) | // Allocate : new Lo
( (i == WrPtr[DEPTH_LOG2-1:0]) & dual_stbuf_write_r & ~store_coalesce_hi_r) | // Allocate : only 1 new Write Either
@ -204,13 +214,54 @@ import el2_pkg::*;
assign stbuf_datain[i][31:24] = sel_lo[i] ? ((~stbuf_byteen[i][3] | store_byteen_lo_r[3]) ? store_datafn_lo_r[31:24] : stbuf_data[i][31:24]) :
((~stbuf_byteen[i][3] | store_byteen_hi_r[3]) ? store_datafn_hi_r[31:24] : stbuf_data[i][31:24]);
rvdffsc #(.WIDTH(1)) stbuf_vldff (.din(1'b1), .dout(stbuf_vld[i]), .en(stbuf_wr_en[i]), .clear(stbuf_reset[i]), .clk(lsu_free_c2_clk), .*);
rvdffsc #(.WIDTH(1)) stbuf_killff (.din(1'b1), .dout(stbuf_dma_kill[i]), .en(stbuf_dma_kill_en[i]), .clear(stbuf_reset[i]), .clk(lsu_free_c2_clk), .*);
rvdffe #(.WIDTH(pt.LSU_SB_BITS)) stbuf_addrff (.din(stbuf_addrin[i][pt.LSU_SB_BITS-1:0]), .dout(stbuf_addr[i][pt.LSU_SB_BITS-1:0]), .en(stbuf_wr_en[i]), .*);
rvdffsc #(.WIDTH(BYTE_WIDTH)) stbuf_byteenff (.din(stbuf_byteenin[i][BYTE_WIDTH-1:0]), .dout(stbuf_byteen[i][BYTE_WIDTH-1:0]), .en(stbuf_wr_en[i]), .clear(stbuf_reset[i]), .clk(lsu_stbuf_c1_clk), .*);
rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_dataff (.din(stbuf_datain[i][DATA_WIDTH-1:0]), .dout(stbuf_data[i][DATA_WIDTH-1:0]), .en(stbuf_wr_en[i]), .*);
rvdffsc #(
.WIDTH(1)
) stbuf_vldff (
.din(1'b1),
.dout(stbuf_vld[i]),
.en(stbuf_wr_en[i]),
.clear(stbuf_reset[i]),
.clk(lsu_free_c2_clk),
.*
);
rvdffsc #(
.WIDTH(1)
) stbuf_killff (
.din(1'b1),
.dout(stbuf_dma_kill[i]),
.en(stbuf_dma_kill_en[i]),
.clear(stbuf_reset[i]),
.clk(lsu_free_c2_clk),
.*
);
rvdffe #(
.WIDTH(pt.LSU_SB_BITS)
) stbuf_addrff (
.din (stbuf_addrin[i][pt.LSU_SB_BITS-1:0]),
.dout(stbuf_addr[i][pt.LSU_SB_BITS-1:0]),
.en (stbuf_wr_en[i]),
.*
);
rvdffsc #(
.WIDTH(BYTE_WIDTH)
) stbuf_byteenff (
.din(stbuf_byteenin[i][BYTE_WIDTH-1:0]),
.dout(stbuf_byteen[i][BYTE_WIDTH-1:0]),
.en(stbuf_wr_en[i]),
.clear(stbuf_reset[i]),
.clk(lsu_stbuf_c1_clk),
.*
);
rvdffe #(
.WIDTH(DATA_WIDTH)
) stbuf_dataff (
.din (stbuf_datain[i][DATA_WIDTH-1:0]),
.dout(stbuf_data[i][DATA_WIDTH-1:0]),
.en (stbuf_wr_en[i]),
.*
);
end
end else begin: Gen_dccm_disable
end else begin : Gen_dccm_disable
assign stbuf_wr_en[DEPTH-1:0] = '0;
assign stbuf_reset[DEPTH-1:0] = '0;
assign stbuf_vld[DEPTH-1:0] = '0;
@ -236,7 +287,7 @@ import el2_pkg::*;
always_comb begin
stbuf_numvld_any[3:0] = '0;
for (int i=0; i<DEPTH; i++) begin
for (int i = 0; i < DEPTH; i++) begin
stbuf_numvld_any[3:0] += {3'b0, stbuf_vld[i]};
end
end
@ -245,30 +296,42 @@ import el2_pkg::*;
assign isdccmst_m = lsu_pkt_m.valid & lsu_pkt_m.store & addr_in_dccm_m & ~lsu_pkt_m.dma;
assign isdccmst_r = lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r & ~lsu_pkt_r.dma;
assign stbuf_specvld_m[1:0] = {1'b0,isdccmst_m} << (isdccmst_m & ldst_dual_m);
assign stbuf_specvld_r[1:0] = {1'b0,isdccmst_r} << (isdccmst_r & ldst_dual_r);
assign stbuf_specvld_m[1:0] = {1'b0, isdccmst_m} << (isdccmst_m & ldst_dual_m);
assign stbuf_specvld_r[1:0] = {1'b0, isdccmst_r} << (isdccmst_r & ldst_dual_r);
assign stbuf_specvld_any[3:0] = stbuf_numvld_any[3:0] + {2'b0, stbuf_specvld_m[1:0]} + {2'b0, stbuf_specvld_r[1:0]};
assign lsu_stbuf_full_any = (~ldst_dual_d & dec_lsu_valid_raw_d) ? (stbuf_specvld_any[3:0] >= DEPTH) : (stbuf_specvld_any[3:0] >= (DEPTH-1));
assign lsu_stbuf_empty_any = (stbuf_numvld_any[3:0] == 4'b0);
// Load forwarding logic from the store queue
assign cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] = end_addr_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)];
assign cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)] = end_addr_m[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)];
assign cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] = lsu_addr_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)];
assign cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)] = lsu_addr_m[pt.LSU_SB_BITS-1:$clog2(
BYTE_WIDTH
)];
always_comb begin: GenLdFwd
always_comb begin : GenLdFwd
stbuf_fwdbyteen_hi_pre_m[BYTE_WIDTH-1:0] = '0;
stbuf_fwdbyteen_lo_pre_m[BYTE_WIDTH-1:0] = '0;
for (int i=0; i<DEPTH; i++) begin
stbuf_match_hi[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
stbuf_match_lo[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
for (int i = 0; i < DEPTH; i++) begin
stbuf_match_hi[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] ==
cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) &
stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
stbuf_match_lo[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] ==
cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) &
stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
// Kill the store buffer entry if there is a dma store since it already updated the dccm
stbuf_dma_kill_en[i] = (stbuf_match_hi[i] | stbuf_match_lo[i]) & lsu_pkt_m.valid & lsu_pkt_m.dma & lsu_pkt_m.store;
for (int j=0; j<BYTE_WIDTH; j++) begin
for (int j = 0; j < BYTE_WIDTH; j++) begin
stbuf_fwdbyteenvec_hi[i][j] = stbuf_match_hi[i] & stbuf_byteen[i][j] & stbuf_vld[i];
stbuf_fwdbyteen_hi_pre_m[j] |= stbuf_fwdbyteenvec_hi[i][j];
@ -278,11 +341,11 @@ import el2_pkg::*;
end
end // block: GenLdFwd
always_comb begin: GenLdData
always_comb begin : GenLdData
stbuf_fwddata_hi_pre_m[31:0] = '0;
stbuf_fwddata_lo_pre_m[31:0] = '0;
for (int i=0; i<DEPTH; i++) begin
for (int i = 0; i < DEPTH; i++) begin
stbuf_fwddata_hi_pre_m[31:0] |= {32{stbuf_match_hi[i]}} & stbuf_data[i][31:0];
stbuf_fwddata_lo_pre_m[31:0] |= {32{stbuf_match_lo[i]}} & stbuf_data[i][31:0];
@ -306,7 +369,7 @@ import el2_pkg::*;
assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma & dual_stbuf_write_r;
assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma & dual_stbuf_write_r;
for (genvar i=0; i<BYTE_WIDTH; i++) begin
for (genvar i = 0; i < BYTE_WIDTH; i++) begin
assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i];
assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i];
assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i];
@ -333,8 +396,24 @@ import el2_pkg::*;
end
// Flops
rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff (.din(NxtWrPtr[DEPTH_LOG2-1:0]), .dout(WrPtr[DEPTH_LOG2-1:0]), .en(WrPtrEn), .clk(lsu_stbuf_c1_clk), .*);
rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff (.din(NxtRdPtr[DEPTH_LOG2-1:0]), .dout(RdPtr[DEPTH_LOG2-1:0]), .en(RdPtrEn), .clk(lsu_stbuf_c1_clk), .*);
rvdffs #(
.WIDTH(DEPTH_LOG2)
) WrPtrff (
.din (NxtWrPtr[DEPTH_LOG2-1:0]),
.dout(WrPtr[DEPTH_LOG2-1:0]),
.en (WrPtrEn),
.clk (lsu_stbuf_c1_clk),
.*
);
rvdffs #(
.WIDTH(DEPTH_LOG2)
) RdPtrff (
.din (NxtRdPtr[DEPTH_LOG2-1:0]),
.dout(RdPtr[DEPTH_LOG2-1:0]),
.en (RdPtrEn),
.clk (lsu_stbuf_c1_clk),
.*
);
endmodule

23
Flow/design/lsu/el2_lsu_trigger.sv
View File

@ -23,11 +23,11 @@
//
//********************************************************************************
module el2_lsu_trigger
import el2_pkg::*;
import el2_pkg::*;
#(
`include "el2_param.vh"
)(
input el2_trigger_pkt_t [3:0] trigger_pkt_any, // trigger packet from dec
`include "el2_param.vh"
) (
input el2_trigger_pkt_t [ 3:0] trigger_pkt_any, // trigger packet from dec
input el2_lsu_pkt_t lsu_pkt_m, // lsu packet
input logic [31:0] lsu_addr_m, // address
input logic [31:0] store_data_m, // store data
@ -36,15 +36,15 @@ import el2_pkg::*;
);
logic trigger_enable;
logic [3:0][31:0] lsu_match_data;
logic [3:0] lsu_trigger_data_match;
logic [ 3:0][31:0] lsu_match_data;
logic [ 3:0] lsu_trigger_data_match;
logic [31:0] store_data_trigger_m;
logic [31:0] ldst_addr_trigger_m;
// Generate the trigger enable (This is for power)
always_comb begin
trigger_enable = 1'b0;
for (int i=0; i<4; i++) begin
for (int i = 0; i < 4; i++) begin
trigger_enable |= trigger_pkt_any[i].m;
end
end
@ -53,11 +53,16 @@ import el2_pkg::*;
assign ldst_addr_trigger_m[31:0] = lsu_addr_m[31:0] & {32{trigger_enable}};
for (genvar i=0; i<4; i++) begin
for (genvar i = 0; i < 4; i++) begin
assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |
({32{trigger_pkt_any[i].select & trigger_pkt_any[i].store}} & store_data_trigger_m[31:0]);
rvmaskandmatch trigger_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(lsu_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(lsu_trigger_data_match[i]));
rvmaskandmatch trigger_match (
.mask (trigger_pkt_any[i].tdata2[31:0]),
.data (lsu_match_data[i][31:0]),
.masken(trigger_pkt_any[i].match),
.match (lsu_trigger_data_match[i])
);
assign lsu_trigger_match_m[i] = lsu_pkt_m.valid & ~lsu_pkt_m.dma & trigger_enable &
((trigger_pkt_any[i].store & lsu_pkt_m.store) | (trigger_pkt_any[i].load & lsu_pkt_m.load & ~trigger_pkt_any[i].select)) &