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This commit is contained in:
Joseph Rahmeh 2019-08-13 12:48:48 -07:00
parent 85a510db19
commit 7ff8d7fb5a
35 changed files with 3042 additions and 3042 deletions
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96
design/dbg/dbg.sv
View File

@ -121,7 +121,7 @@ module dbg (
state_t dbg_state;
state_t dbg_nxtstate;
logic dbg_state_en;
logic dbg_state_en;
// these are the registers that the debug module implements
logic [31:0] dmstatus_reg; // [26:24]-dmerr, [17:16]-resume ack, [9:8]-halted, [3:0]-version
logic [31:0] dmcontrol_reg; // dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive.
@ -167,13 +167,13 @@ module dbg (
//System bus section
logic sbcs_wren;
logic sbcs_sbbusy_wren;
logic sbcs_sbbusy_wren;
logic sbcs_sbbusy_din;
logic sbcs_sbbusyerror_wren;
logic sbcs_sbbusyerror_wren;
logic sbcs_sbbusyerror_din;
logic sbcs_sberror_wren;
logic [2:0] sbcs_sberror_din;
logic [2:0] sbcs_sberror_din;
logic sbcs_unaligned;
logic sbcs_illegal_size;
@ -192,7 +192,7 @@ module dbg (
logic sbaddress0_reg_wren1;
logic sbaddress0_reg_wren;
logic [31:0] sbaddress0_reg_din;
logic [3:0] sbaddress0_incr;
logic [3:0] sbaddress0_incr;
logic sbreadonaddr_access;
logic sbreadondata_access;
logic sbdata0wr_access;
@ -268,8 +268,8 @@ module dbg (
assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'b000)}} & 4'b0001) |
({4{(sbcs_reg[19:17] == 3'b001)}} & 4'b0010) |
({4{(sbcs_reg[19:17] == 3'b010)}} & 4'b0100) |
({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000);
({4{(sbcs_reg[19:17] == 3'b010)}} & 4'b0100) |
({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000);
// sbdata
//assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 32'h3c);
@ -350,7 +350,7 @@ module dbg (
assign abstractcs_error_sel4 = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en &
( ((dmi_reg_wdata[22:20] == 3'b001) & data1_reg[0]) |
((dmi_reg_wdata[22:20] == 3'b010) & (|data1_reg[1:0])) |
dmi_reg_wdata[22] | (dmi_reg_wdata[22:20] == 3'b011)
dmi_reg_wdata[22] | (dmi_reg_wdata[22:20] == 3'b011)
);
assign abstractcs_error_sel5 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;
@ -361,7 +361,7 @@ module dbg (
({3{abstractcs_error_sel1}} & 3'b010) | // writing a non-zero command to cmd field of command
({3{abstractcs_error_sel2}} & 3'b011) | // exception while running command
({3{abstractcs_error_sel3}} & 3'b100) | // writing a comnand when not in the halted state
({3{abstractcs_error_sel4}} & 3'b111) | // unaligned abstract memory command
({3{abstractcs_error_sel4}} & 3'b111) | // unaligned abstract memory command
({3{abstractcs_error_sel5}} & ~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) | // W1C
({3{~abstractcs_error_selor}} & abstractcs_reg[10:8]); // hold
@ -414,37 +414,37 @@ module dbg (
HALTING : begin
dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK
dbg_state_en = dmstatus_reg[9]; // core indicates halted
end
end
HALTED: begin
// wait for halted to go away before send to resume. Else start of new command
dbg_nxtstate = (dmstatus_reg[9] & ~dmcontrol_reg[1]) ? ((dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START) :
(dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case
//dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START; // wait for halted to go away before send to resume. Else start of new command
dbg_state_en = (dmstatus_reg[9] & dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q) | command_wren | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
dbg_state_en = (dmstatus_reg[9] & dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q) | command_wren | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
abstractcs_busy_wren = dbg_state_en & (dbg_nxtstate == CMD_START); // write busy when a new command was written by jtag
abstractcs_busy_din = 1'b1;
dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming
end
end
CMD_START: begin
dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : CMD_WAIT; // new command sent to the core
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]);
end
end
CMD_WAIT: begin
dbg_nxtstate = CMD_DONE;
dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command
end
CMD_DONE: begin
CMD_DONE: begin
dbg_nxtstate = HALTED;
dbg_state_en = 1'b1;
abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
abstractcs_busy_din = 1'b0;
end
RESUMING : begin
dbg_nxtstate = IDLE;
RESUMING : begin
dbg_nxtstate = IDLE;
dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register
end
default : begin
dbg_nxtstate = IDLE;
dbg_nxtstate = IDLE;
dbg_state_en = 1'b0;
abstractcs_busy_wren = 1'b0;
abstractcs_busy_din = 1'b0;
@ -461,7 +461,7 @@ module dbg (
({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) |
({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) |
({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) |
({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) |
({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) |
({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) |
({32{dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0]) |
({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);
@ -495,58 +495,58 @@ module dbg (
case (sb_state)
SBIDLE: begin
sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD;
sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access;
sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command
sbcs_sbbusy_din = 1'b1;
sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access;
sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command
sbcs_sbbusy_din = 1'b1;
sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits
sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
end
WAIT_RD: begin
sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
end
WAIT_WR: begin
sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR;
sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
end
CMD_RD : begin
sb_nxtstate = RSP_RD;
CMD_RD : begin
sb_nxtstate = RSP_RD;
sb_state_en = sb_axi_arvalid_q & sb_axi_arready_q & dbg_bus_clk_en;
end
CMD_WR : begin
sb_nxtstate = (sb_axi_awready_q & sb_axi_wready_q) ? RSP_WR : (sb_axi_awready_q ? CMD_WR_DATA : CMD_WR_ADDR);
end
CMD_WR : begin
sb_nxtstate = (sb_axi_awready_q & sb_axi_wready_q) ? RSP_WR : (sb_axi_awready_q ? CMD_WR_DATA : CMD_WR_ADDR);
sb_state_en = ((sb_axi_awvalid_q & sb_axi_awready_q) | (sb_axi_wvalid_q & sb_axi_wready_q)) & dbg_bus_clk_en;
end
CMD_WR_ADDR : begin
sb_nxtstate = RSP_WR;
end
CMD_WR_ADDR : begin
sb_nxtstate = RSP_WR;
sb_state_en = sb_axi_awvalid_q & sb_axi_awready_q & dbg_bus_clk_en;
end
CMD_WR_DATA : begin
sb_nxtstate = RSP_WR;
end
CMD_WR_DATA : begin
sb_nxtstate = RSP_WR;
sb_state_en = sb_axi_wvalid_q & sb_axi_wready_q & dbg_bus_clk_en;
end
RSP_RD: begin
end
RSP_RD: begin
sb_nxtstate = DONE;
sb_state_en = sb_axi_rvalid_q & sb_axi_rready_q & dbg_bus_clk_en;
sb_state_en = sb_axi_rvalid_q & sb_axi_rready_q & dbg_bus_clk_en;
sbcs_sberror_wren = sb_state_en & sb_axi_rresp_q[1];
sbcs_sberror_din[2:0] = 3'b010;
end
RSP_WR: begin
sbcs_sberror_din[2:0] = 3'b010;
end
RSP_WR: begin
sb_nxtstate = DONE;
sb_state_en = sb_axi_bvalid_q & sb_axi_bready_q & dbg_bus_clk_en;
sb_state_en = sb_axi_bvalid_q & sb_axi_bready_q & dbg_bus_clk_en;
sbcs_sberror_wren = sb_state_en & sb_axi_bresp_q[1];
sbcs_sberror_din[2:0] = 3'b010;
end
DONE: begin
sbcs_sberror_din[2:0] = 3'b010;
end
DONE: begin
sb_nxtstate = SBIDLE;
sb_state_en = 1'b1;
sbcs_sbbusy_wren = 1'b1; // reset the single read
sbcs_sbbusy_wren = 1'b1; // reset the single read
sbcs_sbbusy_din = 1'b0;
sbaddress0_reg_wren1 = sbcs_reg[16]; // auto increment was set. Update to new address after completing the current command
sbaddress0_reg_wren1 = sbcs_reg[16]; // auto increment was set. Update to new address after completing the current command
end
default : begin
sb_nxtstate = SBIDLE;

192
design/dec/dec.sv
View File

@ -41,7 +41,7 @@ module dec
input logic [31:1] rst_vec, // reset vector, from core pins
input logic nmi_int, // NMI pin
input logic [31:1] nmi_vec, // NMI vector, from pins
input logic [31:1] nmi_vec, // NMI vector, from pins
input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
input logic i_cpu_run_req, // Asynchronous Restart request to CPU
@ -66,17 +66,17 @@ module dec
input logic exu_pmu_i0_br_misp, // slot 0 branch misp
input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken
input logic exu_pmu_i0_pc4, // slot 0 4 byte branch
input logic exu_pmu_i1_br_misp, // slot 1 branch misp
input logic exu_pmu_i1_br_misp, // slot 1 branch misp
input logic exu_pmu_i1_br_ataken, // slot 1 branch actual taken
input logic exu_pmu_i1_pc4, // slot 1 4 byte branch
input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3
input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag
input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5
input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag
input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
input logic lsu_nonblock_load_data_error, // nonblock load bus error
input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3
input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag
input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5
input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag
input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
input logic lsu_nonblock_load_data_error, // nonblock load bus error
input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag
input logic [31:0] lsu_nonblock_load_data, // nonblock load data
@ -104,15 +104,15 @@ module dec
input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i
input logic ifu_i0_icaf, // icache access fault
input logic ifu_i1_icaf,
input logic ifu_i0_icaf, // icache access fault
input logic ifu_i1_icaf,
input logic ifu_i0_icaf_f1, // i0 has access fault on second fetch group
input logic ifu_i1_icaf_f1,
input logic ifu_i0_perr, // icache parity error
input logic ifu_i1_perr,
input logic ifu_i0_sbecc, // icache/iccm single-bit error
input logic ifu_i1_sbecc,
input logic ifu_i0_dbecc, // icache/iccm double-bit error
input logic ifu_i0_perr, // icache parity error
input logic ifu_i1_perr,
input logic ifu_i0_sbecc, // icache/iccm single-bit error
input logic ifu_i1_sbecc,
input logic ifu_i0_dbecc, // icache/iccm double-bit error
input logic ifu_i1_dbecc,
input logic lsu_freeze_dc3, // freeze pipe: decode -> dc3
@ -168,7 +168,7 @@ module dec
input logic [31:0] exu_i1_result_e4,
input logic ifu_i0_valid, ifu_i1_valid, // fetch valids to instruction buffer
input logic ifu_i0_valid, ifu_i1_valid, // fetch valids to instruction buffer
input logic [31:0] ifu_i0_instr, ifu_i1_instr, // fetch inst's to instruction buffer
input logic [31:1] ifu_i0_pc, ifu_i1_pc, // pc's for instruction buffer
input logic ifu_i0_pc4, ifu_i1_pc4, // indication of 4B or 2B for corresponding inst
@ -245,42 +245,42 @@ module dec
`ifdef RV_BTB_48
input logic [1:0] exu_i1_br_way_e4, // way hit or repl
input logic [1:0] exu_i0_br_way_e4, // way hit or repl
`else
`else
input logic exu_i1_br_way_e4, // way hit or repl
input logic exu_i0_br_way_e4, // way hit or repl
`endif
`endif
output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data
output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data
output logic [31:0] gpr_i1_rs1_d,
output logic [31:0] gpr_i1_rs2_d,
output logic [31:0] gpr_i1_rs1_d,
output logic [31:0] gpr_i1_rs2_d,
output logic [31:0] dec_i0_immed_d, // immediate data
output logic [31:0] dec_i1_immed_d,
output logic [31:0] dec_i1_immed_d,
output logic [12:1] dec_i0_br_immed_d, // br immediate data
output logic [12:1] dec_i1_br_immed_d,
output alu_pkt_t i0_ap, // alu packet
output alu_pkt_t i1_ap,
output alu_pkt_t i0_ap, // alu packet
output alu_pkt_t i1_ap,
output logic dec_i0_alu_decode_d, // alu schedule on primary alu
output logic dec_i1_alu_decode_d,
output logic dec_i0_alu_decode_d, // alu schedule on primary alu
output logic dec_i1_alu_decode_d,
output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's
output logic dec_i1_select_pc_d,
output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's
output logic dec_i1_select_pc_d,
output logic [31:1] dec_i0_pc_d, dec_i1_pc_d, // pc's at decode
output logic dec_i0_rs1_bypass_en_d, // rs1 bypass enable
output logic dec_i0_rs2_bypass_en_d, // rs2 bypass enable
output logic dec_i1_rs1_bypass_en_d,
output logic dec_i1_rs2_bypass_en_d,
output logic dec_i0_rs1_bypass_en_d, // rs1 bypass enable
output logic dec_i0_rs2_bypass_en_d, // rs2 bypass enable
output logic dec_i1_rs1_bypass_en_d,
output logic dec_i1_rs2_bypass_en_d,
output logic [31:0] i0_rs1_bypass_data_d, // rs1 bypass data
output logic [31:0] i0_rs2_bypass_data_d, // rs2 bypass data
output logic [31:0] i1_rs1_bypass_data_d,
output logic [31:0] i1_rs2_bypass_data_d,
output logic dec_ib3_valid_d, // ib3 buffer valid
output logic dec_ib3_valid_d, // ib3 buffer valid
output logic dec_ib2_valid_d, // ib2 buffer valid
output lsu_pkt_t lsu_p, // lsu packet
@ -402,29 +402,29 @@ module dec
logic dec_tlu_dec_clk_override; // to and from dec blocks
logic clk_override;
logic dec_ib1_valid_d;
logic dec_ib0_valid_d;
logic dec_ib1_valid_d;
logic dec_ib0_valid_d;
logic [1:0] dec_pmu_instr_decoded;
logic dec_pmu_decode_stall;
logic dec_pmu_presync_stall;
logic dec_pmu_postsync_stall;
logic [1:0] dec_pmu_instr_decoded;
logic dec_pmu_decode_stall;
logic dec_pmu_presync_stall;
logic dec_pmu_postsync_stall;
logic dec_tlu_wr_pause_wb; // CSR write to pause reg is at WB.
logic dec_i0_rs1_en_d;
logic dec_i0_rs2_en_d;
logic dec_i0_rs1_en_d;
logic dec_i0_rs2_en_d;
logic dec_fence_pending; // tell TLU to stall DMA
logic [4:0] dec_i0_rs1_d;
logic [4:0] dec_i0_rs2_d;
logic [4:0] dec_i0_rs1_d;
logic [4:0] dec_i0_rs2_d;
logic dec_i1_rs1_en_d;
logic dec_i1_rs2_en_d;
logic dec_i1_rs1_en_d;
logic dec_i1_rs2_en_d;
logic [4:0] dec_i1_rs1_d;
logic [4:0] dec_i1_rs2_d;
logic [4:0] dec_i1_rs1_d;
logic [4:0] dec_i1_rs2_d;
logic [31:0] dec_i0_instr_d, dec_i1_instr_d;
@ -433,12 +433,12 @@ module dec
logic dec_tlu_dual_issue_disable;
logic [4:0] dec_i0_waddr_wb;
logic dec_i0_wen_wb;
logic [4:0] dec_i0_waddr_wb;
logic dec_i0_wen_wb;
logic [31:0] dec_i0_wdata_wb;
logic [4:0] dec_i1_waddr_wb;
logic dec_i1_wen_wb;
logic [4:0] dec_i1_waddr_wb;
logic dec_i1_wen_wb;
logic [31:0] dec_i1_wdata_wb;
logic dec_csr_wen_wb; // csr write enable at wb
@ -448,7 +448,7 @@ module dec
logic [31:0] dec_csr_wrdata_wb; // csr write data at wb
logic [31:0] dec_csr_rddata_d; // csr read data at wb
logic dec_csr_legal_d; // csr indicates legal operation
logic dec_csr_legal_d; // csr indicates legal operation
logic dec_csr_wen_unq_d; // valid csr with write - for csr legal
logic dec_csr_any_unq_d; // valid csr - for csr legal
@ -458,10 +458,10 @@ module dec
trap_pkt_t dec_tlu_packet_e4;
logic dec_i0_pc4_d, dec_i1_pc4_d;
logic dec_tlu_presync_d;
logic dec_tlu_postsync_d;
logic dec_tlu_debug_stall;
logic dec_i0_pc4_d, dec_i1_pc4_d;
logic dec_tlu_presync_d;
logic dec_tlu_postsync_d;
logic dec_tlu_debug_stall;
logic [31:0] dec_illegal_inst;
@ -470,33 +470,33 @@ module dec
logic wen_bank_id;
logic [GPR_BANKS_LOG2-1:0] wr_bank_id;
logic dec_i0_icaf_d;
logic dec_i1_icaf_d;
logic dec_i0_perr_d;
logic dec_i1_perr_d;
logic dec_i0_sbecc_d;
logic dec_i1_sbecc_d;
logic dec_i0_dbecc_d;
logic dec_i1_dbecc_d;
logic dec_i0_icaf_d;
logic dec_i1_icaf_d;
logic dec_i0_perr_d;
logic dec_i1_perr_d;
logic dec_i0_sbecc_d;
logic dec_i1_sbecc_d;
logic dec_i0_dbecc_d;
logic dec_i1_dbecc_d;
logic dec_i0_icaf_f1_d;
logic dec_i0_icaf_f1_d;
logic dec_i0_decode_d;
logic dec_i1_decode_d;
logic dec_i0_decode_d;
logic dec_i1_decode_d;
logic [3:0] dec_i0_trigger_match_d;
logic [3:0] dec_i1_trigger_match_d;
logic [3:0] dec_i0_trigger_match_d;
logic [3:0] dec_i1_trigger_match_d;
logic dec_debug_fence_d;
logic dec_debug_fence_d;
logic dec_nonblock_load_wen;
logic [4:0] dec_nonblock_load_waddr;
logic dec_tlu_flush_pause_wb;
logic dec_nonblock_load_wen;
logic [4:0] dec_nonblock_load_waddr;
logic dec_tlu_flush_pause_wb;
logic dec_i0_load_e4;
logic dec_i0_load_e4;
logic dec_pause_state;
logic dec_pause_state;
br_pkt_t dec_i0_brp;
br_pkt_t dec_i1_brp;
@ -507,7 +507,7 @@ module dec
assign dec_dbg_rddata[31:0] = dec_i0_wdata_wb[31:0];
dec_ib_ctl instbuff (.*
);
);
dec_decode_ctl decode (.*);
@ -521,20 +521,20 @@ module dec
dec_gpr_ctl #(.GPR_BANKS(GPR_BANKS),
.GPR_BANKS_LOG2(GPR_BANKS_LOG2)) arf (.*,
// inputs
// inputs
.raddr0(dec_i0_rs1_d[4:0]), .rden0(dec_i0_rs1_en_d),
.raddr1(dec_i0_rs2_d[4:0]), .rden1(dec_i0_rs2_en_d),
.raddr2(dec_i1_rs1_d[4:0]), .rden2(dec_i1_rs1_en_d),
.raddr3(dec_i1_rs2_d[4:0]), .rden3(dec_i1_rs2_en_d),
.waddr0(dec_i0_waddr_wb[4:0]), .wen0(dec_i0_wen_wb), .wd0(dec_i0_wdata_wb[31:0]),
.waddr1(dec_i1_waddr_wb[4:0]), .wen1(dec_i1_wen_wb), .wd1(dec_i1_wdata_wb[31:0]),
.waddr2(dec_nonblock_load_waddr[4:0]), .wen2(dec_nonblock_load_wen), .wd2(lsu_nonblock_load_data[31:0]),
// outputs
.waddr0(dec_i0_waddr_wb[4:0]), .wen0(dec_i0_wen_wb), .wd0(dec_i0_wdata_wb[31:0]),
.waddr1(dec_i1_waddr_wb[4:0]), .wen1(dec_i1_wen_wb), .wd1(dec_i1_wdata_wb[31:0]),
.waddr2(dec_nonblock_load_waddr[4:0]), .wen2(dec_nonblock_load_wen), .wd2(lsu_nonblock_load_data[31:0]),
// outputs
.rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0]),
.rd2(gpr_i1_rs1_d[31:0]), .rd3(gpr_i1_rs2_d[31:0])
);
);
// Trigger
@ -543,19 +543,19 @@ module dec
// trace
logic [15:0] dec_i0_cinst_d;
logic [15:0] dec_i1_cinst_d;
logic [31:0] dec_i0_inst_wb1;
logic [31:0] dec_i1_inst_wb1;
logic [31:1] dec_i0_pc_wb1;
logic [31:1] dec_i1_pc_wb1;
logic [31:0] dec_i0_inst_wb1;
logic [31:0] dec_i1_inst_wb1;
logic [31:1] dec_i0_pc_wb1;
logic [31:1] dec_i1_pc_wb1;
logic dec_tlu_i1_valid_wb1, dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
logic [4:0] dec_tlu_exc_cause_wb1;
logic [31:0] dec_tlu_mtval_wb1;
logic dec_tlu_i0_exc_valid_wb1, dec_tlu_i1_exc_valid_wb1;
logic dec_tlu_i0_exc_valid_wb1, dec_tlu_i1_exc_valid_wb1;
// also need retires_p==3
@ -563,9 +563,9 @@ module dec
assign trace_rv_trace_pkt.trace_rv_i_address_ip = { 32'b0, dec_i1_pc_wb1[31:1], 1'b0, dec_i0_pc_wb1[31:1], 1'b0 };
assign trace_rv_trace_pkt.trace_rv_i_valid_ip = {dec_tlu_int_valid_wb1, // always int
dec_tlu_i1_valid_wb1 | dec_tlu_i1_exc_valid_wb1, // not interrupts
dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1
};
dec_tlu_i1_valid_wb1 | dec_tlu_i1_exc_valid_wb1, // not interrupts
dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1
};
assign trace_rv_trace_pkt.trace_rv_i_exception_ip = {dec_tlu_int_valid_wb1, dec_tlu_i1_exc_valid_wb1, dec_tlu_i0_exc_valid_wb1};
assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports
assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = {dec_tlu_int_valid_wb1,2'b0};

1122
design/dec/dec_decode_ctl.sv
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12
design/dec/dec_gpr_ctl.sv
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@ -14,7 +14,7 @@
// limitations under the License.
module dec_gpr_ctl #(parameter GPR_BANKS = 1,
GPR_BANKS_LOG2 = 1) (
GPR_BANKS_LOG2 = 1) (
input logic active_clk,
input logic [4:0] raddr0, // logical read addresses
@ -91,17 +91,17 @@ module dec_gpr_ctl #(parameter GPR_BANKS = 1,
rd2[31:0] |= ({32{rden2 & (raddr2[4:0]== 5'(j)) & (gpr_bank_id[GPR_BANKS_LOG2-1:0] == 1'(i))}} & gpr_out[i][j][31:0]);
rd3[31:0] |= ({32{rden3 & (raddr3[4:0]== 5'(j)) & (gpr_bank_id[GPR_BANKS_LOG2-1:0] == 1'(i))}} & gpr_out[i][j][31:0]);
end
end
end
// GPR Write logic
for (int j=1; j<32; j++ ) begin
w0v[j] = wen0 & (waddr0[4:0]== 5'(j) );
w1v[j] = wen1 & (waddr1[4:0]== 5'(j) );
w2v[j] = wen2 & (waddr2[4:0]== 5'(j) );
gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |
({32{w1v[j]}} & wd1[31:0]) |
({32{w2v[j]}} & wd2[31:0]);
end
gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |
({32{w1v[j]}} & wd1[31:0]) |
({32{w2v[j]}} & wd2[31:0]);
end
end // always_comb begin
`ifdef ASSERT_ON

168
design/dec/dec_ib_ctl.sv
View File

@ -19,12 +19,12 @@ module dec_ib_ctl
input logic free_clk, // free clk
input logic active_clk, // active clk if not halt / pause
input logic dbg_cmd_valid, // valid dbg cmd
input logic dbg_cmd_valid, // valid dbg cmd
input logic dbg_cmd_write, // dbg cmd is write
input logic dbg_cmd_write, // dbg cmd is write
input logic [1:0] dbg_cmd_type, // dbg type
input logic [1:0] dbg_cmd_size, // 00 - 1B, 01 - 2B, 10 - 4B, 11 - reserved
input logic [31:0] dbg_cmd_addr, // expand to 31:0
input logic [31:0] dbg_cmd_addr, // expand to 31:0
input logic exu_flush_final, // all flush sources: primary/secondary alu's, trap
@ -37,18 +37,18 @@ module dec_ib_ctl
input logic ifu_i0_pc4, // i0 is 4B inst else 2B
input logic ifu_i1_pc4,
input logic ifu_i0_valid, // i0 valid from ifu
input logic ifu_i0_valid, // i0 valid from ifu
input logic ifu_i1_valid,
input logic ifu_i0_icaf, // i0 instruction access fault
input logic ifu_i0_icaf, // i0 instruction access fault
input logic ifu_i1_icaf,
input logic ifu_i0_icaf_f1, // i0 has access fault on second fetch group
input logic ifu_i1_icaf_f1,
input logic ifu_i0_perr, // i0 instruction parity error
input logic ifu_i0_perr, // i0 instruction parity error
input logic ifu_i1_perr,
input logic ifu_i0_sbecc, // i0 single-bit error
input logic ifu_i0_sbecc, // i0 single-bit error
input logic ifu_i1_sbecc,
input logic ifu_i0_dbecc, // i0 double-bit error
input logic ifu_i0_dbecc, // i0 double-bit error
input logic ifu_i1_dbecc,
input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner
@ -57,12 +57,12 @@ module dec_ib_ctl
input logic [31:1] ifu_i0_pc, // i0 pc from the aligner
input logic [31:1] ifu_i1_pc,
input logic dec_i0_decode_d, // i0 decode
input logic dec_i1_decode_d,
input logic dec_i0_decode_d, // i0 decode
input logic dec_i1_decode_d,
input logic rst_l, // test stuff
input logic clk,
input logic rst_l, // test stuff
input logic clk,
output logic dec_ib3_valid_d, // ib3 valid
@ -108,9 +108,9 @@ module dec_ib_ctl
`include "global.h"
logic flush_final;
logic flush_final;
logic [3:0] ibval_in, ibval;
logic [3:0] ibval_in, ibval;
logic [31:0] ib3_in, ib2_in, ib1_in, ib0_in;
logic [31:0] ib3, ib2, ib1, ib0;
@ -121,49 +121,49 @@ module dec_ib_ctl
logic [15:0] cinst3_in, cinst2_in, cinst1_in, cinst0_in;
logic [15:0] cinst3, cinst2, cinst1, cinst0;
logic write_i1_ib3, write_i0_ib3;
logic write_i1_ib2, write_i0_ib2;
logic write_i1_ib1, write_i0_ib1;
logic write_i0_ib0;
logic write_i1_ib3, write_i0_ib3;
logic write_i1_ib2, write_i0_ib2;
logic write_i1_ib1, write_i0_ib1;
logic write_i0_ib0;
logic shift2, shift1, shift0;
logic shift2, shift1, shift0;
logic shift_ib1_ib0, shift_ib2_ib1, shift_ib3_ib2;
logic shift_ib2_ib0;
logic shift_ib3_ib1;
logic shift_ib1_ib0, shift_ib2_ib1, shift_ib3_ib2;
logic shift_ib2_ib0;
logic shift_ib3_ib1;
logic ifu_i0_val, ifu_i1_val;
logic debug_valid;
logic [4:0] dreg;
logic ifu_i0_val, ifu_i1_val;
logic debug_valid;
logic [4:0] dreg;
logic [11:0] dcsr;
logic [31:0] ib0_debug_in;
// logic debug_read_mem;
// logic debug_write_mem;
logic debug_read;
logic debug_write;
logic debug_read_gpr;
logic debug_write_gpr;
logic debug_read_csr;
logic debug_write_csr;
// logic debug_read_mem;
// logic debug_write_mem;
logic debug_read;
logic debug_write;
logic debug_read_gpr;
logic debug_write_gpr;
logic debug_read_csr;
logic debug_write_csr;
rvdff #(1) flush_upperff (.*, .clk(free_clk), .din(exu_flush_final), .dout(flush_final));
logic [3:0] ibvalid;
logic [3:0] ibvalid;
logic [3:0] i0_wen;
logic [3:1] i1_wen;
logic [3:0] shift_ibval;
logic [3:0] ibwrite;
logic [3:0] i0_wen;
logic [3:1] i1_wen;
logic [3:0] shift_ibval;
logic [3:0] ibwrite;
assign ibvalid[3:0] = ibval[3:0] | i0_wen[3:0] | {i1_wen[3:1],1'b0};
assign ibval_in[3:0] = (({4{shift0}} & ibvalid[3:0]) |
({4{shift1}} & {1'b0, ibvalid[3:1]}) |
({4{shift2}} & {2'b0, ibvalid[3:2]})) & ~{4{flush_final}};
({4{shift1}} & {1'b0, ibvalid[3:1]}) |
({4{shift2}} & {2'b0, ibvalid[3:2]})) & ~{4{flush_final}};
rvdff #(4) ibvalff (.*, .clk(active_clk), .din(ibval_in[3:0]), .dout(ibval[3:0]));
@ -192,13 +192,13 @@ module dec_ib_ctl
if (DEC_INSTBUF_DEPTH==4) begin
assign cinst3_in[15:0] = ({16{write_i0_ib3}} & ifu_i0_cinst[15:0]) |
({16{write_i1_ib3}} & ifu_i1_cinst[15:0]);
({16{write_i1_ib3}} & ifu_i1_cinst[15:0]);
rvdffe #(16) cinst3ff (.*, .en(ibwrite[3]), .din(cinst3_in[15:0]), .dout(cinst3[15:0]));
assign cinst2_in[15:0] = ({16{write_i0_ib2}} & ifu_i0_cinst[15:0]) |
({16{write_i1_ib2}} & ifu_i1_cinst[15:0]) |
({16{shift_ib3_ib2}} & cinst3[15:0]);
({16{write_i1_ib2}} & ifu_i1_cinst[15:0]) |
({16{shift_ib3_ib2}} & cinst3[15:0]);
rvdffe #(16) cinst2ff (.*, .en(ibwrite[2]), .din(cinst2_in[15:0]), .dout(cinst2[15:0]));
end // if (DEC_INSTBUF_DEPTH==4)
@ -208,16 +208,16 @@ module dec_ib_ctl
end
assign cinst1_in[15:0] = ({16{write_i0_ib1}} & ifu_i0_cinst[15:0]) |
({16{write_i1_ib1}} & ifu_i1_cinst[15:0]) |
({16{shift_ib2_ib1}} & cinst2[15:0]) |
({16{shift_ib3_ib1}} & cinst3[15:0]);
({16{write_i1_ib1}} & ifu_i1_cinst[15:0]) |
({16{shift_ib2_ib1}} & cinst2[15:0]) |
({16{shift_ib3_ib1}} & cinst3[15:0]);
rvdffe #(16) cinst1ff (.*, .en(ibwrite[1]), .din(cinst1_in[15:0]), .dout(cinst1[15:0]));
assign cinst0_in[15:0] = ({16{write_i0_ib0}} & ifu_i0_cinst[15:0]) |
({16{shift_ib1_ib0}} & cinst1[15:0]) |
({16{shift_ib2_ib0}} & cinst2[15:0]);
({16{shift_ib1_ib0}} & cinst1[15:0]) |
({16{shift_ib2_ib0}} & cinst2[15:0]);
rvdffe #(16) cinst0ff (.*, .en(ibwrite[0]), .din(cinst0_in[15:0]), .dout(cinst0[15:0]));
@ -232,27 +232,27 @@ module dec_ib_ctl
assign ibwrite[3:0] = { write_i0_ib3 | write_i1_ib3,
write_i0_ib2 | write_i1_ib2 | shift_ib3_ib2,
write_i0_ib1 | write_i1_ib1 | shift_ib2_ib1 | shift_ib3_ib1,
write_i0_ib0 | shift_ib1_ib0 | shift_ib2_ib0
};
write_i0_ib2 | write_i1_ib2 | shift_ib3_ib2,
write_i0_ib1 | write_i1_ib1 | shift_ib2_ib1 | shift_ib3_ib1,
write_i0_ib0 | shift_ib1_ib0 | shift_ib2_ib0
};
logic [36:0] ifu_i1_pcdata, ifu_i0_pcdata;
assign ifu_i1_pcdata[36:0] = { ifu_i1_icaf_f1, ifu_i1_dbecc, ifu_i1_sbecc, ifu_i1_perr, ifu_i1_icaf,
ifu_i1_pc[31:1], ifu_i1_pc4 };
ifu_i1_pc[31:1], ifu_i1_pc4 };
assign ifu_i0_pcdata[36:0] = { ifu_i0_icaf_f1, ifu_i0_dbecc, ifu_i0_sbecc, ifu_i0_perr, ifu_i0_icaf,
ifu_i0_pc[31:1], ifu_i0_pc4 };
ifu_i0_pc[31:1], ifu_i0_pc4 };
if (DEC_INSTBUF_DEPTH==4) begin
assign pc3_in[36:0] = ({37{write_i0_ib3}} & ifu_i0_pcdata[36:0]) |
({37{write_i1_ib3}} & ifu_i1_pcdata[36:0]);
({37{write_i1_ib3}} & ifu_i1_pcdata[36:0]);
rvdffe #(37) pc3ff (.*, .en(ibwrite[3]), .din(pc3_in[36:0]), .dout(pc3[36:0]));
assign pc2_in[36:0] = ({37{write_i0_ib2}} & ifu_i0_pcdata[36:0]) |
({37{write_i1_ib2}} & ifu_i1_pcdata[36:0]) |
({37{shift_ib3_ib2}} & pc3[36:0]);
({37{write_i1_ib2}} & ifu_i1_pcdata[36:0]) |
({37{shift_ib3_ib2}} & pc3[36:0]);
rvdffe #(37) pc2ff (.*, .en(ibwrite[2]), .din(pc2_in[36:0]), .dout(pc2[36:0]));
end // if (DEC_INSTBUF_DEPTH==4)
@ -262,16 +262,16 @@ module dec_ib_ctl
end
assign pc1_in[36:0] = ({37{write_i0_ib1}} & ifu_i0_pcdata[36:0]) |
({37{write_i1_ib1}} & ifu_i1_pcdata[36:0]) |
({37{shift_ib2_ib1}} & pc2[36:0]) |
({37{shift_ib3_ib1}} & pc3[36:0]);
({37{write_i1_ib1}} & ifu_i1_pcdata[36:0]) |
({37{shift_ib2_ib1}} & pc2[36:0]) |
({37{shift_ib3_ib1}} & pc3[36:0]);
rvdffe #(37) pc1ff (.*, .en(ibwrite[1]), .din(pc1_in[36:0]), .dout(pc1[36:0]));
assign pc0_in[36:0] = ({37{write_i0_ib0}} & ifu_i0_pcdata[36:0]) |
({37{shift_ib1_ib0}} & pc1[36:0]) |
({37{shift_ib2_ib0}} & pc2[36:0]);
({37{shift_ib1_ib0}} & pc1[36:0]) |
({37{shift_ib2_ib0}} & pc2[36:0]);
rvdffe #(37) pc0ff (.*, .en(ibwrite[0]), .din(pc0_in[36:0]), .dout(pc0[36:0]));
@ -301,13 +301,13 @@ module dec_ib_ctl
if (DEC_INSTBUF_DEPTH==4) begin
assign bp3_in = ({$bits(br_pkt_t){write_i0_ib3}} & i0_brp) |
({$bits(br_pkt_t){write_i1_ib3}} & i1_brp);
({$bits(br_pkt_t){write_i1_ib3}} & i1_brp);
rvdffe #($bits(br_pkt_t)) bp3ff (.*, .en(ibwrite[3]), .din(bp3_in), .dout(bp3));
assign bp2_in = ({$bits(br_pkt_t){write_i0_ib2}} & i0_brp) |
({$bits(br_pkt_t){write_i1_ib2}} & i1_brp) |
({$bits(br_pkt_t){shift_ib3_ib2}} & bp3);
({$bits(br_pkt_t){write_i1_ib2}} & i1_brp) |
({$bits(br_pkt_t){shift_ib3_ib2}} & bp3);
rvdffe #($bits(br_pkt_t)) bp2ff (.*, .en(ibwrite[2]), .din(bp2_in), .dout(bp2));
end // if (DEC_INSTBUF_DEPTH==4)
@ -317,17 +317,17 @@ module dec_ib_ctl
end
assign bp1_in = ({$bits(br_pkt_t){write_i0_ib1}} & i0_brp) |
({$bits(br_pkt_t){write_i1_ib1}} & i1_brp) |
({$bits(br_pkt_t){shift_ib2_ib1}} & bp2) |
({$bits(br_pkt_t){shift_ib3_ib1}} & bp3);
({$bits(br_pkt_t){write_i1_ib1}} & i1_brp) |
({$bits(br_pkt_t){shift_ib2_ib1}} & bp2) |
({$bits(br_pkt_t){shift_ib3_ib1}} & bp3);
rvdffe #($bits(br_pkt_t)) bp1ff (.*, .en(ibwrite[1]), .din(bp1_in), .dout(bp1));
assign bp0_in = ({$bits(br_pkt_t){write_i0_ib0}} & i0_brp) |
({$bits(br_pkt_t){shift_ib1_ib0}} & bp1) |
({$bits(br_pkt_t){shift_ib2_ib0}} & bp2);
({$bits(br_pkt_t){shift_ib1_ib0}} & bp1) |
({$bits(br_pkt_t){shift_ib2_ib0}} & bp2);
rvdffe #($bits(br_pkt_t)) bp0ff (.*, .en(ibwrite[0]), .din(bp0_in), .dout(bp0));
@ -335,13 +335,13 @@ module dec_ib_ctl
if (DEC_INSTBUF_DEPTH==4) begin
assign ib3_in[31:0] = ({32{write_i0_ib3}} & ifu_i0_instr[31:0]) |
({32{write_i1_ib3}} & ifu_i1_instr[31:0]);
({32{write_i1_ib3}} & ifu_i1_instr[31:0]);
rvdffe #(32) ib3ff (.*, .en(ibwrite[3]), .din(ib3_in[31:0]), .dout(ib3[31:0]));
assign ib2_in[31:0] = ({32{write_i0_ib2}} & ifu_i0_instr[31:0]) |
({32{write_i1_ib2}} & ifu_i1_instr[31:0]) |
({32{shift_ib3_ib2}} & ib3[31:0]);
({32{write_i1_ib2}} & ifu_i1_instr[31:0]) |
({32{shift_ib3_ib2}} & ib3[31:0]);
rvdffe #(32) ib2ff (.*, .en(ibwrite[2]), .din(ib2_in[31:0]), .dout(ib2[31:0]));
end // if (DEC_INSTBUF_DEPTH==4)
@ -351,9 +351,9 @@ module dec_ib_ctl
end
assign ib1_in[31:0] = ({32{write_i0_ib1}} & ifu_i0_instr[31:0]) |
({32{write_i1_ib1}} & ifu_i1_instr[31:0]) |
({32{shift_ib2_ib1}} & ib2[31:0]) |
({32{shift_ib3_ib1}} & ib3[31:0]);
({32{write_i1_ib1}} & ifu_i1_instr[31:0]) |
({32{shift_ib2_ib1}} & ib2[31:0]) |
({32{shift_ib3_ib1}} & ib3[31:0]);
rvdffe #(32) ib1ff (.*, .en(ibwrite[1]), .din(ib1_in[31:0]), .dout(ib1[31:0]));
@ -392,9 +392,9 @@ module dec_ib_ctl
assign ib0_debug_in[31:0] = ({32{debug_read_gpr}} & {12'b000000000000,dreg[4:0],15'b110000000110011}) |
({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) |
({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) |
({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011});
({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) |
({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) |
({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011});
// machine is in halted state, pipe empty, write will always happen next cycle
@ -403,7 +403,7 @@ module dec_ib_ctl
// special fence csr for use only in debug mode
logic debug_fence_in;
logic debug_fence_in;
assign debug_fence_in = debug_write_csr & (dcsr[11:0] == 12'h7c4);
@ -411,8 +411,8 @@ module dec_ib_ctl
assign ib0_in[31:0] = ({32{write_i0_ib0}} & ((debug_valid) ? ib0_debug_in[31:0] : ifu_i0_instr[31:0])) |
({32{shift_ib1_ib0}} & ib1[31:0]) |
({32{shift_ib2_ib0}} & ib2[31:0]);
({32{shift_ib1_ib0}} & ib1[31:0]) |
({32{shift_ib2_ib0}} & ib2[31:0]);
rvdffe #(32) ib0ff (.*, .en(ibwrite[0]), .din(ib0_in[31:0]), .dout(ib0[31:0]));
@ -438,8 +438,8 @@ module dec_ib_ctl
// compute shifted ib valids to determine where to write
assign shift_ibval[3:0] = ({4{shift1}} & {1'b0, ibval[3:1] }) |
({4{shift2}} & {2'b0, ibval[3:2]}) |
({4{shift0}} & ibval[3:0]);
({4{shift2}} & {2'b0, ibval[3:2]}) |
({4{shift0}} & ibval[3:0]);
assign write_i0_ib0 = ~shift_ibval[0] & (ifu_i0_val | debug_valid);
assign write_i0_ib1 = shift_ibval[0] & ~shift_ibval[1] & ifu_i0_val;

732
design/dec/dec_tlu_ctl.sv
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6
design/dec/dec_trigger.sv
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@ -25,15 +25,15 @@
module dec_trigger
import swerv_types::*;
(
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
input trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match
input logic [31:1] dec_i0_pc_d, // i0 pc
input logic [31:1] dec_i1_pc_d, // i1 pc
output logic [3:0] dec_i0_trigger_match_d,
output logic [3:0] dec_i1_trigger_match_d
output logic [3:0] dec_i1_trigger_match_d
);
logic [3:0][31:0] dec_i0_match_data;

32
design/dma_ctrl.sv
View File

@ -67,7 +67,7 @@ module dma_ctrl (
output logic [1:0] dma_axi_rresp,
output logic dma_axi_rlast,
output logic dma_slv_algn_err,
output logic dma_slv_algn_err,
// Debug signals
input logic [31:0] dbg_cmd_addr,
input logic [31:0] dbg_cmd_wrdata,
@ -105,7 +105,7 @@ module dma_ctrl (
input logic dec_tlu_stall_dma, // stall dma accesses, tlu is attempting to enter halt/debug mode
input logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:15]
input logic scan_mode
input logic scan_mode
);
`include "global.h"
@ -133,17 +133,17 @@ module dma_ctrl (
logic [DEPTH-1:0][63:0] fifo_data;
logic [DEPTH-1:0][DMA_BUS_TAG-1:0] fifo_tag;
logic [DEPTH-1:0] fifo_cmd_en;
logic [DEPTH-1:0] fifo_valid_en;
logic [DEPTH-1:0] fifo_data_en;
logic [DEPTH-1:0] fifo_data_bus_en;
logic [DEPTH-1:0] fifo_pend_en;
logic [DEPTH-1:0] fifo_done_en;
logic [DEPTH-1:0] fifo_done_bus_en;
logic [DEPTH-1:0] fifo_error_en;
logic [DEPTH-1:0] fifo_error_bus_en;
//logic [DEPTH-1:0] fifo_rsp_done_en;
logic [DEPTH-1:0] fifo_reset;
logic [DEPTH-1:0] fifo_cmd_en;
logic [DEPTH-1:0] fifo_valid_en;
logic [DEPTH-1:0] fifo_data_en;
logic [DEPTH-1:0] fifo_data_bus_en;
logic [DEPTH-1:0] fifo_pend_en;
logic [DEPTH-1:0] fifo_done_en;
logic [DEPTH-1:0] fifo_done_bus_en;
logic [DEPTH-1:0] fifo_error_en;
logic [DEPTH-1:0] fifo_error_bus_en;
//logic [DEPTH-1:0] fifo_rsp_done_en;
logic [DEPTH-1:0] fifo_reset;
logic [DEPTH-1:0][1:0] fifo_error_in;
logic [DEPTH-1:0][63:0] fifo_data_in;
@ -164,7 +164,7 @@ module dma_ctrl (
logic fifo_full, fifo_full_spec, fifo_empty;
logic dma_address_error, dma_alignment_error;
logic [3:0] num_fifo_vld;
logic [3:0] num_fifo_vld;
logic dma_mem_req;
logic dma_addr_in_dccm;
logic dma_addr_in_iccm;
@ -174,7 +174,7 @@ module dma_ctrl (
logic dma_addr_in_iccm_region_nc;
logic [2:0] dma_nack_count_csr;
logic [2:0] dma_nack_count, dma_nack_count_d;
logic [2:0] dma_nack_count, dma_nack_count_d;
logic dma_buffer_c1_clken;
logic dma_free_clken;
@ -247,7 +247,7 @@ module dma_ctrl (
(i == WrPtr[DEPTH_PTR-1:0]);
assign fifo_data_en[i] = (((axi_mstr_valid & (axi_mstr_write | dma_address_error | dma_alignment_error) & dma_bus_clk_en) |
(dbg_cmd_valid & dbg_cmd_type[1] & dbg_cmd_write)) & (i == WrPtr[DEPTH_PTR-1:0])) |
((dccm_dma_rvalid & (i == RdPtr_Q3[DEPTH_PTR-1:0]))| (iccm_dma_rvalid & (i == RdPtr_Q2[DEPTH_PTR-1:0])));
((dccm_dma_rvalid & (i == RdPtr_Q3[DEPTH_PTR-1:0]))| (iccm_dma_rvalid & (i == RdPtr_Q2[DEPTH_PTR-1:0])));
assign fifo_data_bus_en[i] = (fifo_data_en[i] | fifo_data_valid[i]) & dma_bus_clk_en;
assign fifo_pend_en[i] = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write & (i == RdPtr[DEPTH_PTR-1:0]);
assign fifo_error_en[i] = fifo_cmd_en[i] | (((dccm_dma_rvalid & dccm_dma_ecc_error & (i == RdPtr_Q3[DEPTH_PTR-1:0])) | (iccm_dma_rvalid & iccm_dma_ecc_error & (i == RdPtr_Q2[DEPTH_PTR-1:0]))));

90
design/ifu/ifu.sv
View File

@ -111,8 +111,8 @@ module ifu
input logic dma_mem_write,
input logic [63:0] dma_mem_wdata,
output logic iccm_dma_ecc_error,
output logic iccm_dma_rvalid,
output logic iccm_dma_ecc_error,
output logic iccm_dma_rvalid,
output logic [63:0] iccm_dma_rdata,
output logic iccm_ready,
@ -176,18 +176,18 @@ module ifu
output logic ifu_pmu_bus_trxn, // iside bus transactions
output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode
output logic ifu_i1_valid, // Instruction 1 valid. From Aligner to Decode
output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
output logic ifu_i1_icaf, // Instruction 1 access fault. From Aligner to Decode
output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode
output logic ifu_i1_valid, // Instruction 1 valid. From Aligner to Decode
output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
output logic ifu_i1_icaf, // Instruction 1 access fault. From Aligner to Decode
output logic ifu_i0_icaf_f1, // Instruction 0 has access fault on second fetch group
output logic ifu_i1_icaf_f1, // Instruction 1 has access fault on second fetch group
output logic ifu_i0_perr, // Instruction 0 parity error. From Aligner to Decode
output logic ifu_i1_perr, // Instruction 1 parity error. From Aligner to Decode
output logic ifu_i0_sbecc, // Instruction 0 has single bit ecc error
output logic ifu_i1_sbecc, // Instruction 1 has single bit ecc error
output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
output logic ifu_i1_dbecc, // Instruction 1 has double bit ecc error
output logic ifu_i0_perr, // Instruction 0 parity error. From Aligner to Decode
output logic ifu_i1_perr, // Instruction 1 parity error. From Aligner to Decode
output logic ifu_i0_sbecc, // Instruction 0 has single bit ecc error
output logic ifu_i1_sbecc, // Instruction 1 has single bit ecc error
output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
output logic ifu_i1_dbecc, // Instruction 1 has double bit ecc error
output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
output logic[31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
output logic[31:0] ifu_i1_instr, // Instruction 1 . From Aligner to Decode
@ -237,17 +237,17 @@ module ifu
localparam TAGWIDTH = 2 ;
localparam IDWIDTH = 2 ;
logic ifu_fb_consume1, ifu_fb_consume2;
logic [31:1] ifc_fetch_addr_f2;
logic ifu_fb_consume1, ifu_fb_consume2;
logic [31:1] ifc_fetch_addr_f2;
logic ifc_fetch_uncacheable_f1;
logic [7:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
logic [7:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
logic [31:1] ifu_fetch_pc; // starting pc of fetch
logic [31:1] ifc_fetch_addr_f1;
logic ic_crit_wd_rdy;
logic ic_write_stall;
logic ic_crit_wd_rdy;
logic ic_write_stall;
logic ic_dma_active;
logic ifc_dma_access_ok;
logic ifc_iccm_access_f1;
@ -260,23 +260,23 @@ module ifu
// fetch control
ifu_ifc_ctl ifc (.*
);
);
`ifdef RV_BTB_48
logic [7:0][1:0] ifu_bp_way_f2; // way indication; right justified
`else
logic [7:0] ifu_bp_way_f2; // way indication; right justified
logic [7:0] ifu_bp_way_f2; // way indication; right justified
`endif
logic ifu_bp_kill_next_f2; // kill next fetch; taken target found
logic [31:1] ifu_bp_btb_target_f2; // predicted target PC
logic [7:1] ifu_bp_inst_mask_f2; // tell ic which valids to kill because of a taken branch; right justified
logic [7:0] ifu_bp_hist1_f2; // history counters for all 4 potential branches; right justified
logic [7:0] ifu_bp_hist0_f2; // history counters for all 4 potential branches; right justified
logic [7:1] ifu_bp_inst_mask_f2; // tell ic which valids to kill because of a taken branch; right justified
logic [7:0] ifu_bp_hist1_f2; // history counters for all 4 potential branches; right justified
logic [7:0] ifu_bp_hist0_f2; // history counters for all 4 potential branches; right justified
logic [11:0] ifu_bp_poffset_f2; // predicted target
logic [7:0] ifu_bp_ret_f2; // predicted ret ; right justified
logic [7:0] ifu_bp_pc4_f2; // pc4 indication; right justified
logic [7:0] ifu_bp_valid_f2; // branch valid, right justified
logic [7:0] ifu_bp_ret_f2; // predicted ret ; right justified
logic [7:0] ifu_bp_pc4_f2; // pc4 indication; right justified
logic [7:0] ifu_bp_valid_f2; // branch valid, right justified
logic [`RV_BHT_GHR_RANGE] ifu_bp_fghr_f2;
// branch predictor
@ -320,7 +320,7 @@ module ifu
//
//
`ifdef DUMP_BTB_ON
logic exu_mp_valid; // conditional branch mispredict
logic exu_mp_valid; // conditional branch mispredict
logic exu_mp_way; // conditional branch mispredict
logic exu_mp_ataken; // direction is actual taken
logic exu_mp_boffset; // branch offsett
@ -331,7 +331,7 @@ module ifu
logic [1:0] exu_mp_hist; // new history
logic [11:0] exu_mp_tgt; // target offset
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
logic [1:0] exu_mp_bank; // write bank; based on branch PC[3:2]
logic [1:0] exu_mp_bank; // write bank; based on branch PC[3:2]
logic [`RV_BTB_BTAG_SIZE-1:0] exu_mp_btag; // branch tag
logic [`RV_BHT_GHR_RANGE] exu_mp_fghr; // original fetch ghr (for correcting dir)
@ -363,36 +363,36 @@ logic [2:0] tmp_bnk;
assign tmp_bnk[2:0] = encode8_3(bp.btb_sel_f2[7:0]);
always @(negedge clk) begin
if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
$display("BTB_CONFIG: %d",`RV_BTB_ARRAY_DEPTH*4);
`ifndef BP_NOGSHARE
$display("BHT_CONFIG: %d gshare: 1",`RV_BHT_ARRAY_DEPTH*4);
`else
$display("BHT_CONFIG: %d gshare: 0",`RV_BHT_ARRAY_DEPTH*4);
`endif
$display("RS_CONFIG: %d", `RV_RET_STACK_SIZE);
$display("BTB_CONFIG: %d",`RV_BTB_ARRAY_DEPTH*4);
`ifndef BP_NOGSHARE
$display("BHT_CONFIG: %d gshare: 1",`RV_BHT_ARRAY_DEPTH*4);
`else
$display("BHT_CONFIG: %d gshare: 0",`RV_BHT_ARRAY_DEPTH*4);
`endif
$display("RS_CONFIG: %d", `RV_RET_STACK_SIZE);
end
if(exu_flush_final & ~(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error | dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
$display("%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO], exu_mp_bank[1:0], exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_pkt.btag[`RV_BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[`RV_BHT_GHR_RANGE], exu_mp_valid, bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
$display("%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO], exu_mp_bank[1:0], exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_pkt.btag[`RV_BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[`RV_BHT_GHR_RANGE], exu_mp_valid, bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
for(int i = 0; i < 8; i++) begin
if(ifu_bp_valid_f2[i] & ifc_fetch_req_f2)
$display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f2[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],encode8_3(bp.btb_sel_f2[7:0]), bp.btb_rd_call_f2, bp.btb_rd_ret_f2, ifu_bp_hist1_f2[tmp_bnk], ifu_bp_hist0_f2[tmp_bnk], bp.fetch_rd_tag_f2[`RV_BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f2[31:1], 1'b0}, bp.fghr[`RV_BHT_GHR_RANGE], bp.bht_rd_addr_f1, ifu_bp_way_f2[tmp_bnk]);
$display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f2[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],encode8_3(bp.btb_sel_f2[7:0]), bp.btb_rd_call_f2, bp.btb_rd_ret_f2, ifu_bp_hist1_f2[tmp_bnk], ifu_bp_hist0_f2[tmp_bnk], bp.fetch_rd_tag_f2[`RV_BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f2[31:1], 1'b0}, bp.fghr[`RV_BHT_GHR_RANGE], bp.bht_rd_addr_f1, ifu_bp_way_f2[tmp_bnk]);
end
`ifdef RV_BTB_48
for(int y = 0; y < 4; y++) begin
for(int z = 0; z < 4; z++) begin
if(bp.lru_bank_sel[y][z])
$display("%7d BTB_LRU: index: %0h bank: %0h newlru %h", `DEC.tlu.mcyclel[31:0]+32'ha, z,y,bp.lru_bank_wr_data[y][z]);
end
for(int z = 0; z < 4; z++) begin
if(bp.lru_bank_sel[y][z])
$display("%7d BTB_LRU: index: %0h bank: %0h newlru %h", `DEC.tlu.mcyclel[31:0]+32'ha, z,y,bp.lru_bank_wr_data[y][z]);
end
end
`endif
if(dec_tlu_br0_wb_pkt.valid & ~(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error))
$display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br0_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br0_wb_pkt.bank[1:0],dec_tlu_br0_wb_pkt.middle}, dec_tlu_br0_wb_pkt.hist, dec_tlu_br0_wb_pkt.way);
$display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br0_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br0_wb_pkt.bank[1:0],dec_tlu_br0_wb_pkt.middle}, dec_tlu_br0_wb_pkt.hist, dec_tlu_br0_wb_pkt.way);
if(dec_tlu_br1_wb_pkt.valid & ~(dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error))
$display("%7d BTB_UPD1: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br1_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br1_wb_pkt.bank[1:0],dec_tlu_br1_wb_pkt.middle}, dec_tlu_br1_wb_pkt.hist, dec_tlu_br1_wb_pkt.way);
$display("%7d BTB_UPD1: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br1_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br1_wb_pkt.bank[1:0],dec_tlu_br1_wb_pkt.middle}, dec_tlu_br1_wb_pkt.hist, dec_tlu_br1_wb_pkt.way);
if(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error)
$display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br0_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br0_wb_pkt.bank[1:0], dec_tlu_br0_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_wb_pkt.way);
$display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br0_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br0_wb_pkt.bank[1:0], dec_tlu_br0_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_wb_pkt.way);
if(dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error)
$display("%7d BTB_ERR1: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br1_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br1_wb_pkt.bank[1:0], dec_tlu_br1_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br1_wb_pkt.way);
$display("%7d BTB_ERR1: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br1_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br1_wb_pkt.bank[1:0], dec_tlu_br1_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br1_wb_pkt.way);
end // always @ (negedge clk)
function [2:0] encode8_3;
input [7:0] in;
@ -401,6 +401,6 @@ assign tmp_bnk[2:0] = encode8_3(bp.btb_sel_f2[7:0]);
encode8_3[1] = in[7] | in[6] | in[3] | in[2];
encode8_3[0] = in[7] | in[5] | in[3] | in[1];
endfunction
endfunction
`endif
endmodule // ifu

900
design/ifu/ifu_aln_ctl.sv
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File diff suppressed because it is too large Load Diff

908
design/ifu/ifu_bp_ctl.sv
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File diff suppressed because it is too large Load Diff

64
design/ifu/ifu_compress_ctl.sv
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@ -34,7 +34,7 @@ module ifu_compress_ctl
assign i[15:0] = din[15:0];
logic [4:0] rs2d,rdd,rdpd,rs2pd;
logic [4:0] rs2d,rdd,rdpd,rs2pd;
logic rdrd;
logic rdrs1;
@ -86,25 +86,25 @@ logic uswspimm7_2;
assign l1[6:0] = o[6:0];
assign l1[11:7] = o[11:7] |
({5{rdrd}} & rdd[4:0]) |
({5{rdprd}} & rdpd[4:0]) |
({5{rs2prd}} & rs2pd[4:0]) |
({5{rdeq1}} & 5'd1) |
({5{rdeq2}} & 5'd2);
({5{rdrd}} & rdd[4:0]) |
({5{rdprd}} & rdpd[4:0]) |
({5{rs2prd}} & rs2pd[4:0]) |
({5{rdeq1}} & 5'd1) |
({5{rdeq2}} & 5'd2);
// rs1
// rs1
assign l1[14:12] = o[14:12];
assign l1[19:15] = o[19:15] |
({5{rdrs1}} & rdd[4:0]) |
({5{rdprs1}} & rdpd[4:0]) |
({5{rs1eq2}} & 5'd2);
({5{rdrs1}} & rdd[4:0]) |
({5{rdprs1}} & rdpd[4:0]) |
({5{rs1eq2}} & 5'd2);
// rs2
assign l1[24:20] = o[24:20] |
({5{rs2rs2}} & rs2d[4:0]) |
({5{rs2prs2}} & rs2pd[4:0]);
({5{rs2rs2}} & rs2d[4:0]) |
({5{rs2prs2}} & rs2pd[4:0]);
assign l1[31:25] = o[31:25];
@ -143,20 +143,20 @@ logic uswspimm7_2;
assign l2[31:20] = ( l1[31:20] ) |
( {12{simm5_0}} & {{7{simm5d[5]}},simm5d[4:0]} ) |
( {12{uimm9_2}} & {2'b0,uimm9d[9:2],2'b0} ) |
( {12{simm9_4}} & {{3{simm9d[9]}},simm9d[8:4],4'b0} ) |
( {12{ulwimm6_2}} & {5'b0,ulwimm6d[6:2],2'b0} ) |
( {12{ulwspimm7_2}} & {4'b0,ulwspimm7d[7:2],2'b0} ) |
( {12{uimm5_0}} & {6'b0,uimm5d[5:0]} ) |
( {12{sjaloffset11_1}} & {sjald[20],sjald[10:1],sjald[11]} ) |
( {12{sluimm17_12}} & sluimmd[31:20] );
( {12{simm5_0}} & {{7{simm5d[5]}},simm5d[4:0]} ) |
( {12{uimm9_2}} & {2'b0,uimm9d[9:2],2'b0} ) |
( {12{simm9_4}} & {{3{simm9d[9]}},simm9d[8:4],4'b0} ) |
( {12{ulwimm6_2}} & {5'b0,ulwimm6d[6:2],2'b0} ) |
( {12{ulwspimm7_2}} & {4'b0,ulwspimm7d[7:2],2'b0} ) |
( {12{uimm5_0}} & {6'b0,uimm5d[5:0]} ) |
( {12{sjaloffset11_1}} & {sjald[20],sjald[10:1],sjald[11]} ) |
( {12{sluimm17_12}} & sluimmd[31:20] );
assign l2[19:12] = ( l1[19:12] ) |
( {8{sjaloffset11_1}} & sjald[19:12] ) |
( {8{sluimm17_12}} & sluimmd[19:12] );
( {8{sjaloffset11_1}} & sjald[19:12] ) |
( {8{sluimm17_12}} & sluimmd[19:12] );
assign l2[11:0] = l1[11:0];
@ -164,9 +164,9 @@ logic uswspimm7_2;
// merge in branch offset and store immediates
logic [8:1] sbr8d;
logic [6:2] uswimm6d;
logic [7:2] uswspimm7d;
logic [8:1] sbr8d;
logic [6:2] uswimm6d;
logic [7:2] uswspimm7d;
assign sbr8d[8:1] = { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
@ -176,17 +176,17 @@ logic uswspimm7_2;
assign uswspimm7d[7:2] = { i[8:7], i[12:9] };
assign l3[31:25] = ( l2[31:25] ) |
( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) |
( {7{uswimm6_2}} & { 5'b0, uswimm6d[6:5] } ) |
( {7{uswspimm7_2}} & { 4'b0, uswspimm7d[7:5] } );
( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) |
( {7{uswimm6_2}} & { 5'b0, uswimm6d[6:5] } ) |
( {7{uswspimm7_2}} & { 4'b0, uswspimm7d[7:5] } );
assign l3[24:12] = l2[24:12];
assign l3[11:7] = ( l2[11:7] ) |
( {5{sbroffset8_1}} & { sbr8d[4:1], sbr8d[8] } ) |
( {5{uswimm6_2}} & { uswimm6d[4:2], 2'b0 } ) |
( {5{uswspimm7_2}} & { uswspimm7d[4:2], 2'b0 } );
( {5{sbroffset8_1}} & { sbr8d[4:1], sbr8d[8] } ) |
( {5{uswimm6_2}} & { uswimm6d[4:2], 2'b0 } ) |
( {5{uswspimm7_2}} & { uswspimm7d[4:2], 2'b0 } );
assign l3[6:0] = l2[6:0];

62
design/ifu/ifu_ic_mem.sv
View File

@ -212,12 +212,12 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
logic ic_debug_rd_en_ff;
rvdff #(2) adr_ff (.*,
.din ({ic_rw_addr_q[5:4]}),
.dout({ic_rw_addr_ff[5:4]}));
.din ({ic_rw_addr_q[5:4]}),
.dout({ic_rw_addr_ff[5:4]}));
rvdff #(5) debug_rd_wy_ff (.*,
.din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}),
.dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff}));
.din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}),
.dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff}));
localparam NUM_WAYS=4 ;
localparam NUM_SUBBANKS=4 ;
@ -225,29 +225,29 @@ localparam NUM_SUBBANKS=4 ;
for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS
rvoclkhdr bank_way_c1_cgc ( .en(ic_bank_way_clken[i]), .l1clk(ic_bank_way_clk[i]), .* );
rvoclkhdr bank_way_c1_cgc ( .en(ic_bank_way_clken[i]), .l1clk(ic_bank_way_clk[i]), .* );
for (genvar k=0; k<NUM_SUBBANKS; k++) begin: SUBBANKS // 16B subbank
for (genvar k=0; k<NUM_SUBBANKS; k++) begin: SUBBANKS // 16B subbank
`ifdef RV_ICACHE_ECC
`RV_ICACHE_DATA_CELL ic_bank_sb_way_data (
.CLK(ic_bank_way_clk[i]),
.WE (ic_b_sb_wren[k][i]),
.WE (ic_b_sb_wren[k][i]),
.D (ic_sb_wr_data[k][41:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
.Q (wb_dout[i][(k+1)*42-1:k*42])
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
.Q (wb_dout[i][(k+1)*42-1:k*42])
);
`else
`RV_ICACHE_DATA_CELL ic_bank_sb_way_data (
.CLK(ic_bank_way_clk[i]),
.WE (ic_b_sb_wren[k][i]),
.WE (ic_b_sb_wren[k][i]),
.D (ic_sb_wr_data[k][33:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
.Q (wb_dout[i][(k+1)*34-1:k*34])
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
.Q (wb_dout[i][(k+1)*34-1:k*34])
);
`endif
end // block: SUBBANKS
end
@ -374,8 +374,8 @@ module IC_TAG #(parameter ICACHE_TAG_HIGH = 16 ,
assign ic_tag_clken[3:0] = {4{ic_rd_en | clk_override}} | ic_wr_en[3:0] | ic_debug_wr_way_en[3:0] | ic_debug_rd_way_en[3:0];
rvdff #(32-ICACHE_TAG_HIGH) adr_ff (.*,
.din ({ic_rw_addr[31:ICACHE_TAG_HIGH]}),
.dout({ic_rw_addr_ff[31:ICACHE_TAG_HIGH]}));
.din ({ic_rw_addr[31:ICACHE_TAG_HIGH]}),
.dout({ic_rw_addr_ff[31:ICACHE_TAG_HIGH]}));
localparam TOP_BITS = 21+ICACHE_TAG_HIGH-33 ;
@ -436,8 +436,8 @@ end
rvdff #(4) tag_rd_wy_ff (.*,
.din ({ic_debug_rd_way_en[3:0]}),
.dout({ic_debug_rd_way_en_ff[3:0]}));
.din ({ic_debug_rd_way_en[3:0]}),
.dout({ic_debug_rd_way_en_ff[3:0]}));
@ -448,11 +448,11 @@ end
`ifdef RV_ICACHE_ECC
ram_64x25 ic_way_tag (
.CLK(ic_tag_clk[i]),
.WE (ic_tag_wren_q[i]),
.WE (ic_tag_wren_q[i]),
.D (ic_tag_wr_data[24:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][24:0])
);
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][24:0])
);
assign w_tout[i][31:ICACHE_TAG_HIGH] = ic_tag_data_raw[i][31-ICACHE_TAG_HIGH:0] ;
@ -472,11 +472,11 @@ end
`else
ram_64x21 ic_way_tag (
.CLK(ic_tag_clk[i]),
.WE (ic_tag_wren_q[i]),
.WE (ic_tag_wren_q[i]),
.D (ic_tag_wr_data[20:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][20:0])
);
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][20:0])
);
assign w_tout[i][31:ICACHE_TAG_HIGH] = ic_tag_data_raw[i][31-ICACHE_TAG_HIGH:0] ;
assign w_tout[i][32] = ic_tag_data_raw[i][20] ;
@ -494,8 +494,8 @@ end
.CLK(ic_tag_clk[i]),
.WE (ic_tag_wren_q[i]),
.D (ic_tag_wr_data[24:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][24:0])
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q (ic_tag_data_raw[i][24:0])
);
assign w_tout[i][31:ICACHE_TAG_HIGH] = ic_tag_data_raw[i][31-ICACHE_TAG_HIGH:0] ;
@ -518,8 +518,8 @@ end
.CLK(ic_tag_clk[i]),
.WE (ic_tag_wren_q[i]),
.D (ic_tag_wr_data[20:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q ({ic_tag_data_raw[i][20:0]})
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW]),
.Q ({ic_tag_data_raw[i][20:0]})
);
assign w_tout[i][31:ICACHE_TAG_HIGH] = ic_tag_data_raw[i][31-ICACHE_TAG_HIGH:0] ;
@ -539,8 +539,8 @@ end // block: WAYS
({25{ic_debug_rd_way_en_ff[1]}} & ic_tag_data_raw[1] ) |
({25{ic_debug_rd_way_en_ff[2]}} & ic_tag_data_raw[2] ) |
({25{ic_debug_rd_way_en_ff[3]}} & ic_tag_data_raw[3] ) ;
`else
`else
assign ictag_debug_rd_data[20:0] = ({21{ic_debug_rd_way_en_ff[0]}} & ic_tag_data_raw[0] ) |
({21{ic_debug_rd_way_en_ff[1]}} & ic_tag_data_raw[1] ) |
({21{ic_debug_rd_way_en_ff[2]}} & ic_tag_data_raw[2] ) |

38
design/ifu/ifu_iccm_mem.sv
View File

@ -23,9 +23,9 @@ module ifu_iccm_mem
import swerv_types::*;
(
input logic clk,
input logic rst_l,
input logic clk_override,
input logic clk,
input logic rst_l,
input logic clk_override,
input logic iccm_wren,
input logic iccm_rden,
@ -33,8 +33,8 @@ module ifu_iccm_mem
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [155:0] iccm_rd_data,
input logic scan_mode
@ -43,22 +43,22 @@ module ifu_iccm_mem
`include "global.h"
logic [ICCM_NUM_BANKS/4-1:0] wren_bank;
logic [ICCM_NUM_BANKS/4-1:0] rden_bank;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clk ;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank;
logic [ICCM_NUM_BANKS/4-1:0] rden_bank;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clken;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clk ;
logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clk ;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi0;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo0;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi1;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo1;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi0;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo0;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi1;
logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo1;
logic [ICCM_NUM_BANKS/4-1:0] [ICCM_INDEX_BITS-1:0] addr_bank;

132
design/ifu/ifu_ifc_ctl.sv
View File

@ -57,9 +57,9 @@ module ifu_ifc_ctl
output logic [31:1] ifc_fetch_addr_f1, // fetch addr F1
output logic [31:1] ifc_fetch_addr_f2, // fetch addr F2
output logic ifc_fetch_req_f1, // fetch request valid F1
output logic ifc_fetch_req_f1, // fetch request valid F1
output logic ifc_fetch_req_f1_raw, // for clock-gating in mem_ctl
output logic ifc_fetch_req_f2, // fetch request valid F2
output logic ifc_fetch_req_f2, // fetch request valid F2
output logic ifu_pmu_fetch_stall, // pmu event measuring fetch stall
@ -73,29 +73,29 @@ module ifu_ifc_ctl
logic [31:1] fetch_addr_bf, miss_addr, ifc_fetch_addr_f1_raw;
logic [31:1] fetch_addr_next;
logic [31:1] miss_addr_ns;
logic [4:0] cacheable_select;
logic [3:0] fb_write_f1, fb_write_ns;
logic [4:0] cacheable_select;
logic [3:0] fb_write_f1, fb_write_ns;
logic ifc_fetch_req_bf;
logic overflow_nc;
logic fb_full_f1_ns, fb_full_f1;
logic fb_right, fb_right2, fb_right3, fb_left, wfm, fetch_ns, idle;
logic fetch_req_f2_ns;
logic missff_en;
logic fetch_crit_word, ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2;
logic reset_delayed, reset_detect, reset_detected;
logic sel_last_addr_bf, sel_miss_addr_bf, sel_btb_addr_bf, sel_next_addr_bf;
logic miss_f2, miss_a;
logic flush_fb, dma_iccm_stall_any_f;
logic dec_tlu_halted_f;
logic mb_empty_mod, goto_idle, leave_idle;
logic ic_crit_wd_rdy_mod;
logic miss_sel_flush;
logic miss_sel_f2;
logic miss_sel_f1;
logic miss_sel_bf;
logic fetch_bf_en;
logic ifc_fetch_req_f2_raw;
logic ifc_fetch_req_bf;
logic overflow_nc;
logic fb_full_f1_ns, fb_full_f1;
logic fb_right, fb_right2, fb_right3, fb_left, wfm, fetch_ns, idle;
logic fetch_req_f2_ns;
logic missff_en;
logic fetch_crit_word, ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2;
logic reset_delayed, reset_detect, reset_detected;
logic sel_last_addr_bf, sel_miss_addr_bf, sel_btb_addr_bf, sel_next_addr_bf;
logic miss_f2, miss_a;
logic flush_fb, dma_iccm_stall_any_f;
logic dec_tlu_halted_f;
logic mb_empty_mod, goto_idle, leave_idle;
logic ic_crit_wd_rdy_mod;
logic miss_sel_flush;
logic miss_sel_f2;
logic miss_sel_f1;
logic miss_sel_bf;
logic fetch_bf_en;
logic ifc_fetch_req_f2_raw;
logic ifc_f2_clk;
rvoclkhdr ifu_fa2_cgc ( .en(ifc_fetch_req_f1 | clk_override), .l1clk(ifc_f2_clk), .* );
@ -127,11 +127,11 @@ module ifu_ifc_ctl
assign miss_sel_bf = ~miss_sel_f2 & ~miss_sel_f1 & ~miss_sel_flush;
assign miss_addr_ns[31:1] = ( ({31{miss_sel_flush}} & exu_flush_path_final[31:1]) |
({31{miss_sel_f2}} & ifc_fetch_addr_f2[31:1]) |
({31{miss_sel_f1}} & ifc_fetch_addr_f1[31:1]) |
({31{miss_sel_bf}} & fetch_addr_bf[31:1]));
({31{miss_sel_f2}} & ifc_fetch_addr_f2[31:1]) |
({31{miss_sel_f1}} & ifc_fetch_addr_f1[31:1]) |
({31{miss_sel_bf}} & fetch_addr_bf[31:1]));
rvdffe #(31) faddmiss_ff (.*, .en(missff_en), .din(miss_addr_ns[31:1]), .dout(miss_addr[31:1]));
@ -148,10 +148,10 @@ module ifu_ifc_ctl
assign fetch_addr_bf[31:1] = ( ({31{miss_sel_flush}} & exu_flush_path_final[31:1]) | // FLUSH path
({31{sel_miss_addr_bf}} & miss_addr[31:1]) | // MISS path
({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f2[31:1]})| // BTB target
({31{sel_last_addr_bf}} & {ifc_fetch_addr_f1[31:1]})| // Last cycle
({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
({31{sel_miss_addr_bf}} & miss_addr[31:1]) | // MISS path
({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f2[31:1]})| // BTB target
({31{sel_last_addr_bf}} & {ifc_fetch_addr_f1[31:1]})| // Last cycle
({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
assign {overflow_nc, fetch_addr_next[31:1]} = {({1'b0, ifc_fetch_addr_f1[31:4]} + 29'b1), 3'b0};
@ -178,42 +178,42 @@ module ifu_ifc_ctl
//-- 0--1- 00
//00 0--00 00
//00 0--01 01
//
//
//01 01-0- 11
//01 00-0- 01
//
//
//11 0-10- 01
//11 0-00- 11
assign next_state[1] = (~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) |
(state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle);
(state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle);
assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle) |
(reset_delayed);
(reset_delayed);
assign flush_fb = exu_flush_final;
// model fb write logic to mass balance the fetch buffers
assign fb_right = (~ifu_fb_consume1 & ~ifu_fb_consume2 & miss_f2) | // F2 cache miss, repair mass balance
( ifu_fb_consume1 & ~ifu_fb_consume2 & ~ifc_fetch_req_f1 & ~miss_f2) | // Consumed and no new fetch
(ifu_fb_consume2 & ifc_fetch_req_f1 & ~miss_f2); // Consumed 2 and new fetch
( ifu_fb_consume1 & ~ifu_fb_consume2 & ~ifc_fetch_req_f1 & ~miss_f2) | // Consumed and no new fetch
(ifu_fb_consume2 & ifc_fetch_req_f1 & ~miss_f2); // Consumed 2 and new fetch
assign fb_right2 = (ifu_fb_consume1 & ~ifu_fb_consume2 & miss_f2) | // consume 1 and miss 1
(ifu_fb_consume2 & ~ifc_fetch_req_f1); // Consumed 2 and no new fetch
(ifu_fb_consume2 & ~ifc_fetch_req_f1); // Consumed 2 and no new fetch
assign fb_right3 = (ifu_fb_consume2 & miss_f2); // consume 2 and miss
assign fb_left = ifc_fetch_req_f1 & ~(ifu_fb_consume1 | ifu_fb_consume2) & ~miss_f2;
assign fb_write_ns[3:0] = ( ({4{(flush_fb & ~ifc_fetch_req_f1)}} & 4'b0001) |
({4{(flush_fb & ifc_fetch_req_f1)}} & 4'b0010) |
({4{~flush_fb & fb_right }} & {1'b0, fb_write_f1[3:1]}) |
({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f1[3:2]}) |
({4{~flush_fb & fb_right3}} & {3'b0, fb_write_f1[3]} ) |
({4{~flush_fb & fb_left }} & {fb_write_f1[2:0], 1'b0}) |
({4{~flush_fb & ~fb_right & ~fb_right2 & ~fb_left & ~fb_right3}} & fb_write_f1[3:0]));
({4{(flush_fb & ifc_fetch_req_f1)}} & 4'b0010) |
({4{~flush_fb & fb_right }} & {1'b0, fb_write_f1[3:1]}) |
({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f1[3:2]}) |
({4{~flush_fb & fb_right3}} & {3'b0, fb_write_f1[3]} ) |
({4{~flush_fb & fb_left }} & {fb_write_f1[2:0], 1'b0}) |
({4{~flush_fb & ~fb_right & ~fb_right2 & ~fb_left & ~fb_right3}} & fb_write_f1[3:0]));
assign fb_full_f1_ns = fb_write_ns[3];
@ -225,16 +225,16 @@ module ifu_ifc_ctl
rvdff #(5) fbwrite_ff (.*, .clk(active_clk), .din({fb_full_f1_ns, fb_write_ns[3:0]}), .dout({fb_full_f1, fb_write_f1[3:0]}));
assign ifu_pmu_fetch_stall = wfm |
(ifc_fetch_req_f1_raw &
( (fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) |
dma_stall));
(ifc_fetch_req_f1_raw &
( (fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) |
dma_stall));
// BTB hit kills this fetch
assign ifc_fetch_req_f1 = ( ifc_fetch_req_f1_raw &
~ifu_bp_kill_next_f2 &
~(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) &
~dma_stall &
~ic_write_stall &
~dec_tlu_flush_noredir_wb );
~ifu_bp_kill_next_f2 &
~(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) &
~dma_stall &
~ic_write_stall &
~dec_tlu_flush_noredir_wb );
// kill F2 request if we flush or if the prior fetch missed the cache/mem
assign fetch_req_f2_ns = ifc_fetch_req_f1 & ~miss_f2;
@ -247,28 +247,28 @@ module ifu_ifc_ctl
rvdff #(31) faddrf2_ff (.*, .clk(ifc_f2_clk), .din(ifc_fetch_addr_f1[31:1]), .dout(ifc_fetch_addr_f2[31:1]));
assign ifc_fetch_addr_f1[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) |
({31{~exu_flush_final}} & ifc_fetch_addr_f1_raw[31:1]));
({31{~exu_flush_final}} & ifc_fetch_addr_f1_raw[31:1]));
rvdff #(3) iccrit_ff (.*, .clk(active_clk), .din({ic_crit_wd_rdy_mod, fetch_crit_word, fetch_crit_word_d1}),
.dout({ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2}));
.dout({ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2}));
`ifdef RV_ICCM_ENABLE
logic iccm_acc_in_region_f1;
logic iccm_acc_in_range_f1;
rvrangecheck #( .CCM_SADR (`RV_ICCM_SADR),
.CCM_SIZE (`RV_ICCM_SIZE) ) iccm_rangecheck (
.addr ({ifc_fetch_addr_f1[31:1],1'b0}) ,
.in_range (iccm_acc_in_range_f1) ,
.in_region(iccm_acc_in_region_f1)
);
.addr ({ifc_fetch_addr_f1[31:1],1'b0}) ,
.in_range (iccm_acc_in_range_f1) ,
.in_region(iccm_acc_in_region_f1)
);
assign ifc_iccm_access_f1 = iccm_acc_in_range_f1 ;
assign ifc_dma_access_ok = ( (~ifc_iccm_access_f1 |
(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1)) |
wfm |
idle ) & ~exu_flush_final) |
dma_iccm_stall_any_f;
(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1)) |
wfm |
idle ) & ~exu_flush_final) |
dma_iccm_stall_any_f;
assign ifc_region_acc_fault_f1 = ~iccm_acc_in_range_f1 & iccm_acc_in_region_f1 ;
`else

80
design/ifu/ifu_mem_ctl.sv
View File

@ -34,7 +34,7 @@ module ifu_mem_ctl
input logic [31:1] fetch_addr_f1, // Fetch Address byte aligned always. F1 stage.
input logic ifc_fetch_uncacheable_f1, // The fetch request is uncacheable space. F1 stage
input logic ifc_fetch_req_f1, // Fetch request. Comes with the address. F1 stage
input logic ifc_fetch_req_f1, // Fetch request. Comes with the address. F1 stage
input logic ifc_fetch_req_f1_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage
input logic ifc_iccm_access_f1, // This request is to the ICCM. Do not generate misses to the bus.
input logic ifc_region_acc_fault_f1, // Access fault. in ICCM region but offset is outside defined ICCM.
@ -116,7 +116,7 @@ module ifu_mem_ctl
input logic [63:0] dma_mem_wdata, // write data
output logic iccm_dma_ecc_error,// Data read from iccm has an ecc error
output logic iccm_dma_rvalid, // Data read from iccm is valid
output logic iccm_dma_rvalid, // Data read from iccm is valid
output logic [63:0] iccm_dma_rdata, // dma data read from iccm
output logic iccm_ready, // iccm ready to accept new command.
@ -490,8 +490,8 @@ module ifu_mem_ctl
rvdffe #(31) ifu_fetch_addr_f2_ff (.*,
.en (fetch_f1_f2_c1_clken),
.din ({fetch_addr_f1[31:1]}),
.dout({ifu_fetch_addr_int_f2[31:1]}));
.din ({fetch_addr_f1[31:1]}),
.dout({ifu_fetch_addr_int_f2[31:1]}));
assign vaddr_f2[3:1] = ifu_fetch_addr_int_f2[3:1] ;
@ -684,13 +684,13 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
assign bp_mask[7:0] = {ifu_bp_inst_mask_f2[7:1], 1'b1};
assign ic_bp_mem_mask[7:0] = ({8{fetch_mask[0]}} & bp_mask[7:0]) | // unrotate the bpmask
({8{fetch_mask[1]}} & {bp_mask[6:0],1'b0}) |
({8{fetch_mask[2]}} & {bp_mask[5:0],2'b0}) |
({8{fetch_mask[3]}} & {bp_mask[4:0],3'b0}) |
({8{fetch_mask[4]}} & {bp_mask[3:0],4'b0}) |
({8{fetch_mask[5]}} & {bp_mask[2:0],5'b0}) |
({8{fetch_mask[6]}} & {bp_mask[1:0],6'b0}) |
({8{fetch_mask[7]}} & {bp_mask[0] ,7'b0});
({8{fetch_mask[1]}} & {bp_mask[6:0],1'b0}) |
({8{fetch_mask[2]}} & {bp_mask[5:0],2'b0}) |
({8{fetch_mask[3]}} & {bp_mask[4:0],3'b0}) |
({8{fetch_mask[4]}} & {bp_mask[3:0],4'b0}) |
({8{fetch_mask[5]}} & {bp_mask[2:0],5'b0}) |
({8{fetch_mask[6]}} & {bp_mask[1:0],6'b0}) |
({8{fetch_mask[7]}} & {bp_mask[0] ,7'b0});
assign ic_fetch_val_mem_f2[7:0] = {8{fetch_req_f2_qual}} & ic_bp_mem_mask[7:0] & ic_fetch_mem_val[7:0];
@ -734,40 +734,40 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
// First Half flops
rvdffe #(64) byp_data_first_half (.*,
.en(byp_data_first_c1_clken),
.din (ifu_wr_data_new[63:0]),
.dout(ifu_byp_data_first_half[63:0]));
.din (ifu_wr_data_new[63:0]),
.dout(ifu_byp_data_first_half[63:0]));
assign ifu_byp_data_error_first_half_in = write_byp_first_data ? ifu_wr_data_error : (ifu_byp_data_error_first_half & ~ic_act_miss_f2) ;
rvdff #(1) byp_data_first_half_err (.*,
.clk(free_clk),
.din (ifu_byp_data_error_first_half_in),
.dout(ifu_byp_data_error_first_half));
.din (ifu_byp_data_error_first_half_in),
.dout(ifu_byp_data_error_first_half));
assign ifu_byp_data_first_half_valid_in = write_byp_first_data ? 1'b1 : (ifu_byp_data_first_half_valid & ~ic_act_miss_f2) ;
rvdff #(1) byp_data_first_half_val (.*,
.clk(free_clk),
.din (ifu_byp_data_first_half_valid_in),
.dout(ifu_byp_data_first_half_valid));
.din (ifu_byp_data_first_half_valid_in),
.dout(ifu_byp_data_first_half_valid));
// Second Half flops
rvdffe #(64) byp_data_second_half (.*,
.en(byp_data_second_c1_clken),
.din (ifu_wr_data_new[63:0]),
.dout(ifu_byp_data_second_half[63:0]));
.din (ifu_wr_data_new[63:0]),
.dout(ifu_byp_data_second_half[63:0]));
assign ifu_byp_data_error_second_half_in = write_byp_second_data ? ifu_wr_data_error : (ifu_byp_data_error_second_half & ~ic_act_miss_f2) ;
rvdff #(1) byp_data_second_half_err (.*,
.clk(free_clk),
.din (ifu_byp_data_error_second_half_in),
.dout(ifu_byp_data_error_second_half));
.din (ifu_byp_data_error_second_half_in),
.dout(ifu_byp_data_error_second_half));
assign ifu_byp_data_second_half_valid_in = write_byp_second_data ? 1'b1 : (ifu_byp_data_second_half_valid & ~ic_act_miss_f2) ;
rvdff #(1) byp_data_second_half_val (.*,
.clk(free_clk),
.din (ifu_byp_data_second_half_valid_in),
.dout(ifu_byp_data_second_half_valid));
.din (ifu_byp_data_second_half_valid_in),
.dout(ifu_byp_data_second_half_valid));
assign ic_byp_data_only[127:0] = { ifu_byp_data_second_half[63:0] , ifu_byp_data_first_half[63:0] } ;
assign ifu_byp_data_err = ifu_byp_data_error_second_half | ifu_byp_data_error_first_half ;
@ -840,10 +840,10 @@ logic ifu_icache_sb_error_val_ff ;
perr_nxtstate = (~dec_tlu_flush_err_wb & exu_flush_final ) ? ERR_IDLE : ECC_CORR ;
perr_state_en = exu_flush_final ;
end
DMA_SB_ERR : begin : dma_sb_ecc
DMA_SB_ERR : begin : dma_sb_ecc
perr_nxtstate = ECC_CORR;
perr_state_en = 1'b1;
end
perr_state_en = 1'b1;
end
ECC_CORR: begin : ecc_corr
perr_nxtstate = ERR_IDLE ;
perr_state_en = 1'b1 ;
@ -882,7 +882,7 @@ for (i=0; i < 4 ; i++) begin : ICCM_ECC_CHECK
assign iccm_ecc_word_enable[i] = ((|ic_fetch_val_mem_f2[(2*i+1):(2*i)] & ~exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & ~dec_tlu_core_ecc_disable;
rvecc_decode ecc_decode (
.en(iccm_ecc_word_enable[i]),
.sed_ded ( 1'b0 ), // 1 : means only detection
.sed_ded ( 1'b0 ), // 1 : means only detection
.din(iccm_rd_data[(39*i+31):(39*i)]),
.ecc_in(iccm_rd_data[(39*i+38):(39*i+32)]),
.dout(iccm_corrected_data[i][31:0]),
@ -1088,7 +1088,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
rvdff #(3) axi_cmd_beat_ff (.*, .clk(axiclk_reset), .din ({axi_new_cmd_beat_count[2:0]}),
.dout({axi_cmd_beat_count[2:0]}));
.dout({axi_cmd_beat_count[2:0]}));
assign req_addr_count[2:0] = axi_new_rd_addr_count[2:0] ;
@ -1354,13 +1354,13 @@ assign ifu_ic_rw_int_addr_w_debug[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW] = ((ic_debug
rvdff #(5) ifu_pmu_sigs_ff (.*,
.clk (active_clk),
.din ({ifu_pmu_ic_miss_in,
.din ({ifu_pmu_ic_miss_in,
ifu_pmu_ic_hit_in,
ifu_pmu_bus_error_in,
ifu_pmu_bus_busy_in,
ifu_pmu_bus_trxn_in
}),
.dout({ifu_pmu_ic_miss,
.dout({ifu_pmu_ic_miss,
ifu_pmu_ic_hit,
ifu_pmu_bus_error,
ifu_pmu_bus_busy,
@ -1411,14 +1411,14 @@ assign ic_debug_ic_array_sel_word3_in = (ic_debug_addr[3:2] == 2'b11) & ic_debug
assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array ;
rvdffe #(09) ifu_debug_sel_ff (.*, .en (debug_c1_clken),
.din ({ic_debug_ic_array_sel_word0_in,
.din ({ic_debug_ic_array_sel_word0_in,
ic_debug_ic_array_sel_word1_in,
ic_debug_ic_array_sel_word2_in,
ic_debug_ic_array_sel_word3_in,
ic_debug_ict_array_sel_in,
ic_debug_way[3:0]
}),
.dout({ic_debug_ic_array_sel_word0,
.dout({ic_debug_ic_array_sel_word0,
ic_debug_ic_array_sel_word1,
ic_debug_ic_array_sel_word2,
ic_debug_ic_array_sel_word3,
@ -1428,10 +1428,10 @@ rvdffe #(09) ifu_debug_sel_ff (.*, .en (debug_c1_clken),
rvdff #(1) ifu_debug_rd_en_ff (.*,.clk(free_clk),
.din ({
.din ({
ic_debug_rd_en
}),
.dout({
.dout({
ic_debug_rd_en_ff
}));
@ -1445,10 +1445,10 @@ assign ifu_ic_debug_rd_data_in[41:0] = ( {42{ic_debug_ict_array_sel_ff }} & {
( {42{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [167:126]}) ;
rvdffe #(42) ifu_debug_data_ff (.*, .en (debug_data_clken),
.din ({
.din ({
ifu_ic_debug_rd_data_in[41:0]
}),
.dout({
.dout({
ifu_ic_debug_rd_data
}));
@ -1461,10 +1461,10 @@ assign ifu_ic_debug_rd_data_in[33:0] = ( {34{ic_debug_ict_array_sel_ff }} & {
( {34{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [135:102]}) ;
rvdffe #(34) ifu_debug_data_ff (.*, .en (debug_data_clken),
.din ({
.din ({
ifu_ic_debug_rd_data_in[33:0]
}),
.dout({
.dout({
ifu_ic_debug_rd_data
}));
@ -1473,10 +1473,10 @@ assign debug_data_clken = ic_debug_rd_en_ff;
rvclkhdr debug_data_c1_cgc ( .en(debug_data_clken), .l1clk(debug_data_clk), .* );
rvdff #(1) ifu_debug_valid_ff (.*, .clk(free_clk),
.din ({
.din ({
ic_debug_rd_en_ff
}),
.dout({
.dout({
ifu_ic_debug_rd_data_valid
}));

466
design/include/swerv_types.sv
View File

@ -16,162 +16,162 @@ package swerv_types;
// performance monitor stuff
typedef struct packed {
logic [2:0] trace_rv_i_valid_ip;
logic [95:0] trace_rv_i_insn_ip;
logic [95:0] trace_rv_i_address_ip;
logic [2:0] trace_rv_i_exception_ip;
logic [4:0] trace_rv_i_ecause_ip;
logic [2:0] trace_rv_i_interrupt_ip;
logic [31:0] trace_rv_i_tval_ip;
} trace_pkt_t;
logic [2:0] trace_rv_i_valid_ip;
logic [95:0] trace_rv_i_insn_ip;
logic [95:0] trace_rv_i_address_ip;
logic [2:0] trace_rv_i_exception_ip;
logic [4:0] trace_rv_i_ecause_ip;
logic [2:0] trace_rv_i_interrupt_ip;
logic [31:0] trace_rv_i_tval_ip;
} trace_pkt_t;
typedef enum logic [3:0] {
NULL = 4'b0000,
MUL = 4'b0001,
LOAD = 4'b0010,
STORE = 4'b0011,
ALU = 4'b0100,
CSRREAD = 4'b0101,
CSRWRITE = 4'b0110,
CSRRW = 4'b0111,
EBREAK = 4'b1000,
ECALL = 4'b1001,
FENCE = 4'b1010,
FENCEI = 4'b1011,
MRET = 4'b1100,
CONDBR = 4'b1101,
JAL = 4'b1110
} inst_t;
NULL = 4'b0000,
MUL = 4'b0001,
LOAD = 4'b0010,
STORE = 4'b0011,
ALU = 4'b0100,
CSRREAD = 4'b0101,
CSRWRITE = 4'b0110,
CSRRW = 4'b0111,
EBREAK = 4'b1000,
ECALL = 4'b1001,
FENCE = 4'b1010,
FENCEI = 4'b1011,
MRET = 4'b1100,
CONDBR = 4'b1101,
JAL = 4'b1110
} inst_t;
typedef struct packed {
`ifdef RV_ICACHE_ECC
logic [39:0] ecc;
`ifdef RV_ICACHE_ECC
logic [39:0] ecc;
`else
logic [7:0] parity;
logic [7:0] parity;
`endif
} icache_err_pkt_t;
} icache_err_pkt_t;
typedef struct packed {
logic valid;
logic wb;
logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] tag;
logic [4:0] rd;
} load_cam_pkt_t;
logic valid;
logic wb;
logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] tag;
logic [4:0] rd;
} load_cam_pkt_t;
typedef struct packed {
logic pc0_call;
logic pc0_ret;
logic pc0_pc4;
logic pc1_call;
logic pc1_ret;
logic pc1_pc4;
} rets_pkt_t;
logic pc0_call;
logic pc0_ret;
logic pc0_pc4;
logic pc1_call;
logic pc1_ret;
logic pc1_pc4;
} rets_pkt_t;
typedef struct packed {
logic valid;
logic [11:0] toffset;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic [31:1] prett; // predicted ret target
logic [`RV_BHT_GHR_RANGE] fghr;
logic valid;
logic [11:0] toffset;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic [31:1] prett; // predicted ret target
logic [`RV_BHT_GHR_RANGE] fghr;
`ifdef RV_BTB_48
logic [1:0] way;
logic [1:0] way;
`else
logic way;
logic way;
`endif
logic ret;
logic [`RV_BTB_BTAG_SIZE-1:0] btag;
} br_pkt_t;
logic ret;
logic [`RV_BTB_BTAG_SIZE-1:0] btag;
} br_pkt_t;
typedef struct packed {
logic valid;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic [`RV_BHT_GHR_RANGE] fghr;
logic valid;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic [`RV_BHT_GHR_RANGE] fghr;
`ifdef RV_BTB_48
logic [1:0] way;
logic [1:0] way;
`else
logic way;
logic way;
`endif
logic middle;
} br_tlu_pkt_t;
logic middle;
} br_tlu_pkt_t;
typedef struct packed {
logic misp;
logic ataken;
logic boffset;
logic pc4;
logic [1:0] hist;
logic [11:0] toffset;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic valid;
logic br_error;
logic br_start_error;
logic [31:1] prett;
logic pcall;
logic pret;
logic pja;
logic [`RV_BTB_BTAG_SIZE-1:0] btag;
logic [`RV_BHT_GHR_RANGE] fghr;
logic misp;
logic ataken;
logic boffset;
logic pc4;
logic [1:0] hist;
logic [11:0] toffset;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index;
logic [1:0] bank;
logic valid;
logic br_error;
logic br_start_error;
logic [31:1] prett;
logic pcall;
logic pret;
logic pja;
logic [`RV_BTB_BTAG_SIZE-1:0] btag;
logic [`RV_BHT_GHR_RANGE] fghr;
`ifdef RV_BTB_48
logic [1:0] way;
logic [1:0] way;
`else
logic way;
logic way;
`endif
} predict_pkt_t;
} predict_pkt_t;
typedef struct packed {
logic legal;
logic icaf;
logic icaf_f1;
logic perr;
logic sbecc;
logic fence_i;
logic [3:0] i0trigger;
logic [3:0] i1trigger;
inst_t pmu_i0_itype; // pmu - instruction type
inst_t pmu_i1_itype; // pmu - instruction type
logic pmu_i0_br_unpred; // pmu
logic pmu_i1_br_unpred; // pmu
logic pmu_divide;
logic pmu_lsu_misaligned;
} trap_pkt_t;
logic legal;
logic icaf;
logic icaf_f1;
logic perr;
logic sbecc;
logic fence_i;
logic [3:0] i0trigger;
logic [3:0] i1trigger;
inst_t pmu_i0_itype; // pmu - instruction type
inst_t pmu_i1_itype; // pmu - instruction type
logic pmu_i0_br_unpred; // pmu
logic pmu_i1_br_unpred; // pmu
logic pmu_divide;
logic pmu_lsu_misaligned;
} trap_pkt_t;
typedef struct packed {
logic [4:0] i0rd;
logic i0mul;
logic i0load;
logic i0store;
logic i0div;
logic i0v;
logic i0valid;
logic i0secondary;
logic [1:0] i0rs1bype2;
logic [1:0] i0rs2bype2;
logic [3:0] i0rs1bype3;
logic [3:0] i0rs2bype3;
logic [4:0] i1rd;
logic i1mul;
logic i1load;
logic i1store;
logic i1v;
logic i1valid;
logic csrwen;
logic csrwonly;
logic [11:0] csrwaddr;
logic i1secondary;
logic [1:0] i1rs1bype2;
logic [1:0] i1rs2bype2;
logic [6:0] i1rs1bype3;
logic [6:0] i1rs2bype3;
} dest_pkt_t;
logic [4:0] i0rd;
logic i0mul;
logic i0load;
logic i0store;
logic i0div;
logic i0v;
logic i0valid;
logic i0secondary;
logic [1:0] i0rs1bype2;
logic [1:0] i0rs2bype2;
logic [3:0] i0rs1bype3;
logic [3:0] i0rs2bype3;
logic [4:0] i1rd;
logic i1mul;
logic i1load;
logic i1store;
logic i1v;
logic i1valid;
logic csrwen;
logic csrwonly;
logic [11:0] csrwaddr;
logic i1secondary;
logic [1:0] i1rs1bype2;
logic [1:0] i1rs2bype2;
logic [6:0] i1rs1bype3;
logic [6:0] i1rs2bype3;
} dest_pkt_t;
typedef struct packed {
logic mul;
@ -181,132 +181,132 @@ typedef struct packed {
} class_pkt_t;
typedef struct packed {
logic [4:0] rs1;
logic [4:0] rs2;
logic [4:0] rd;
} reg_pkt_t;
logic [4:0] rs1;
logic [4:0] rs2;
logic [4:0] rd;
} reg_pkt_t;
typedef struct packed {
logic valid;
logic valid;
logic land;
logic lor;
logic lxor;
logic sll;
logic srl;
logic sra;
logic beq;
logic bne;
logic blt;
logic bge;
logic add;
logic sub;
logic slt;
logic unsign;
logic jal;
logic predict_t;
logic predict_nt;
logic csr_write;
logic csr_imm;
} alu_pkt_t;
logic lor;
logic lxor;
logic sll;
logic srl;
logic sra;
logic beq;
logic bne;
logic blt;
logic bge;
logic add;
logic sub;
logic slt;
logic unsign;
logic jal;
logic predict_t;
logic predict_nt;
logic csr_write;
logic csr_imm;
} alu_pkt_t;
typedef struct packed {
logic by;
logic half;
logic word;
logic dword; // for dma
logic load;
logic store;
logic unsign;
logic by;
logic half;
logic word;
logic dword; // for dma
logic load;
logic store;
logic unsign;
logic dma; // dma pkt
logic store_data_bypass_c1;
logic load_ldst_bypass_c1;
logic store_data_bypass_c2;
logic store_data_bypass_i0_e2_c2;
logic [1:0] store_data_bypass_e4_c1;
logic [1:0] store_data_bypass_e4_c2;
logic [1:0] store_data_bypass_e4_c3;
logic valid;
} lsu_pkt_t;
logic store_data_bypass_c1;
logic load_ldst_bypass_c1;
logic store_data_bypass_c2;
logic store_data_bypass_i0_e2_c2;
logic [1:0] store_data_bypass_e4_c1;
logic [1:0] store_data_bypass_e4_c2;
logic [1:0] store_data_bypass_e4_c3;
logic valid;
} lsu_pkt_t;
typedef struct packed {
logic exc_valid;
logic single_ecc_error;
logic inst_type; //0: Load, 1: Store
logic inst_pipe; //0: i0, 1: i1
logic dma_valid;
logic dma_valid;
logic exc_type; //0: MisAligned, 1: Access Fault
logic [31:0] addr;
} lsu_error_pkt_t;
typedef struct packed {
logic alu;
logic rs1;
logic rs2;
logic imm12;
logic rd;
logic shimm5;
logic imm20;
logic pc;
logic load;
logic store;
logic lsu;
logic add;
logic sub;
logic land;
logic lor;
logic lxor;
logic sll;
logic sra;
logic srl;
logic slt;
logic unsign;
logic condbr;
logic beq;
logic bne;
logic bge;
logic blt;
logic jal;
logic by;
logic half;
logic word;
logic csr_read;
logic csr_clr;
logic csr_set;
logic csr_write;
logic csr_imm;
logic presync;
logic postsync;
logic ebreak;
logic ecall;
logic mret;
logic mul;
logic rs1_sign;
logic rs2_sign;
logic low;
logic div;
logic rem;
logic fence;
logic fence_i;
logic pm_alu;
logic legal;
} dec_pkt_t;
logic alu;
logic rs1;
logic rs2;
logic imm12;
logic rd;
logic shimm5;
logic imm20;
logic pc;
logic load;
logic store;
logic lsu;
logic add;
logic sub;
logic land;
logic lor;
logic lxor;
logic sll;
logic sra;
logic srl;
logic slt;
logic unsign;
logic condbr;
logic beq;
logic bne;
logic bge;
logic blt;
logic jal;
logic by;
logic half;
logic word;
logic csr_read;
logic csr_clr;
logic csr_set;
logic csr_write;
logic csr_imm;
logic presync;
logic postsync;
logic ebreak;
logic ecall;
logic mret;
logic mul;
logic rs1_sign;
logic rs2_sign;
logic low;
logic div;
logic rem;
logic fence;
logic fence_i;
logic pm_alu;
logic legal;
} dec_pkt_t;
typedef struct packed {
logic valid;
logic rs1_sign;
logic rs2_sign;
logic low;
logic load_mul_rs1_bypass_e1;
logic load_mul_rs2_bypass_e1;
} mul_pkt_t;
logic valid;
logic rs1_sign;
logic rs2_sign;
logic low;
logic load_mul_rs1_bypass_e1;
logic load_mul_rs2_bypass_e1;
} mul_pkt_t;
typedef struct packed {
logic valid;
logic unsign;
logic rem;
} div_pkt_t;
logic valid;
logic unsign;
logic rem;
} div_pkt_t;
typedef struct packed {
@ -314,14 +314,14 @@ typedef struct packed {
logic match;
logic store;
logic load;
logic execute;
logic m;
logic execute;
logic m;
logic [31:0] tdata2;
} trigger_pkt_t;
typedef struct packed {
`ifdef RV_ICACHE_ECC
`ifdef RV_ICACHE_ECC
logic [41:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]}
`else
logic [33:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]}

26
design/lib/ahb_to_axi4.sv
View File

@ -76,7 +76,7 @@ module ahb_to_axi4 #(parameter TAG = 1) (
input logic ahb_hwrite, // ahb bus write
input logic [63:0] ahb_hwdata, // ahb bus write data
input logic ahb_hsel, // this slave was selected
input logic ahb_hreadyin, // previous hready was accepted or not
input logic ahb_hreadyin, // previous hready was accepted or not
output logic [63:0] ahb_hrdata, // ahb bus read data
output logic ahb_hreadyout, // slave ready to accept transaction
@ -92,7 +92,7 @@ module ahb_to_axi4 #(parameter TAG = 1) (
PEND = 2'b11 // Waiting on Read Data from core
} state_t;
state_t buf_state, buf_nxtstate;
logic buf_state_en;
logic buf_state_en;
// Buffer signals (one entry buffer)
logic buf_read_error_in, buf_read_error;
@ -111,7 +111,7 @@ module ahb_to_axi4 #(parameter TAG = 1) (
logic ahb_addr_in_dccm, ahb_addr_in_iccm, ahb_addr_in_pic;
logic ahb_addr_in_dccm_region_nc, ahb_addr_in_iccm_region_nc, ahb_addr_in_pic_region_nc;
// signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
logic buf_rdata_en;
logic buf_rdata_en;
logic ahb_bus_addr_clk_en, buf_rdata_clk_en;
logic ahb_clk, ahb_addr_clk, buf_rdata_clk;
@ -140,20 +140,20 @@ module ahb_to_axi4 #(parameter TAG = 1) (
end
WR: begin // Write command recieved last cycle
buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : (ahb_hwrite ? WR : RD);
buf_state_en = (~cmdbuf_full | ahb_hresp) ;
buf_state_en = (~cmdbuf_full | ahb_hresp) ;
cmdbuf_wr_en = ~cmdbuf_full & ~(ahb_hresp | ((ahb_htrans[1:0] == 2'b01) & ahb_hsel)); // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
end
RD: begin // Read command recieved last cycle.
buf_nxtstate = ahb_hresp ? IDLE :PEND; // If error go to idle, else wait for read data
buf_state_en = (~cmdbuf_full | ahb_hresp); // only when command can go, or if its an error
cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full; // send command only when no error
end
end
RD: begin // Read command recieved last cycle.
buf_nxtstate = ahb_hresp ? IDLE :PEND; // If error go to idle, else wait for read data
buf_state_en = (~cmdbuf_full | ahb_hresp); // only when command can go, or if its an error
cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full; // send command only when no error
end
PEND: begin // Read Command has been sent. Waiting on Data.
buf_nxtstate = IDLE; // go back for next command and present data next cycle
buf_state_en = axi_rvalid & ~cmdbuf_write; // read data is back
buf_nxtstate = IDLE; // go back for next command and present data next cycle
buf_state_en = axi_rvalid & ~cmdbuf_write; // read data is back
buf_rdata_en = buf_state_en; // buffer the read data coming back from core
buf_read_error_in = buf_state_en & |axi_rresp[1:0]; // buffer error flag if return has Error ( ECC )
end
end
endcase
end // always_comb begin

32
design/lib/axi4_to_ahb.sv
View File

@ -62,7 +62,7 @@ module axi4_to_ahb #(parameter TAG = 1) (
output logic [TAG-1:0] axi_rid,
output logic [63:0] axi_rdata,
output logic [1:0] axi_rresp,
output logic axi_rlast,
output logic axi_rlast,
// AHB-Lite signals
output logic [31:0] ahb_haddr, // ahb bus address
@ -146,7 +146,7 @@ module axi4_to_ahb #(parameter TAG = 1) (
logic slave_valid_pre;
logic ahb_hready_q;
logic ahb_hresp_q;
logic [1:0] ahb_htrans_q;
logic [1:0] ahb_htrans_q;
logic ahb_hwrite_q;
logic [63:0] ahb_hrdata_q;
@ -288,30 +288,30 @@ module axi4_to_ahb #(parameter TAG = 1) (
ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
end
CMD_RD: begin
buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;
cmd_done = buf_state_en & ~master_valid;
slvbuf_wr_en = buf_state_en;
master_ready = buf_state_en & (buf_nxtstate == STREAM_RD);
slvbuf_wr_en = buf_state_en;
master_ready = buf_state_en & (buf_nxtstate == STREAM_RD);
buf_wr_en = master_ready;
bypass_en = master_ready & master_valid;
buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];
ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en | bypass_en}};
ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en | bypass_en}};
end
STREAM_RD: begin
master_ready = (ahb_hready_q & ~ahb_hresp_q) & ~(master_valid & master_opc[2:1] == 2'b01);
buf_wr_en = (master_valid & master_ready & (master_opc[2:0] == 3'b000)); // update the fifo if we are streaming the read commands
buf_wr_en = (master_valid & master_ready & (master_opc[2:0] == 3'b000)); // update the fifo if we are streaming the read commands
buf_nxtstate = ahb_hresp_q ? STREAM_ERR_RD : (buf_wr_en ? STREAM_RD : DATA_RD); // assuming that the master accpets the slave response right away.
buf_state_en = (ahb_hready_q | ahb_hresp_q);
buf_data_wr_en = buf_state_en;
slvbuf_error_in = ahb_hresp_q;
slvbuf_error_en = buf_state_en;
slave_valid_pre = buf_state_en & ~ahb_hresp_q; // send a response right away if we are not going through an error response.
cmd_done = buf_state_en & ~master_valid; // last one of the stream should not send a htrans
bypass_en = master_ready & master_valid & (buf_nxtstate == STREAM_RD) & buf_state_en;
slave_valid_pre = buf_state_en & ~ahb_hresp_q; // send a response right away if we are not going through an error response.
cmd_done = buf_state_en & ~master_valid; // last one of the stream should not send a htrans
bypass_en = master_ready & master_valid & (buf_nxtstate == STREAM_RD) & buf_state_en;
buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];
ahb_htrans[1:0] = 2'b10 & {2{~((buf_nxtstate != STREAM_RD) & buf_state_en)}};
slvbuf_wr_en = buf_wr_en; // shifting the contents from the buf to slv_buf for streaming cases
slvbuf_wr_en = buf_wr_en; // shifting the contents from the buf to slv_buf for streaming cases
end // case: STREAM_RD
STREAM_ERR_RD: begin
buf_nxtstate = DATA_RD;
@ -319,7 +319,7 @@ module axi4_to_ahb #(parameter TAG = 1) (
slave_valid_pre = buf_state_en;
slvbuf_wr_en = buf_state_en; // Overwrite slvbuf with buffer
buf_cmd_byte_ptr[2:0] = buf_addr[2:0];
ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}};
ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}};
end
DATA_RD: begin
buf_nxtstate = DONE;
@ -327,14 +327,14 @@ module axi4_to_ahb #(parameter TAG = 1) (
buf_data_wr_en = buf_state_en;
slvbuf_error_in= ahb_hresp_q;
slvbuf_error_en= buf_state_en;
slvbuf_wr_en = buf_state_en;
slvbuf_wr_en = buf_state_en;
end
CMD_WR: begin
buf_nxtstate = DATA_WR;
trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
buf_state_en = trxn_done;
buf_cmd_byte_ptr_en = buf_state_en;
slvbuf_wr_en = buf_state_en;
slvbuf_wr_en = buf_state_en;
buf_cmd_byte_ptr = trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
cmd_done = trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ == 3'b111) |
(buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0));
@ -362,12 +362,12 @@ module axi4_to_ahb #(parameter TAG = 1) (
buf_cmd_byte_ptr_en = trxn_done | bypass_en;
buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :
trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
end
end
DONE: begin
buf_nxtstate = IDLE;
buf_state_en = slave_ready;
slvbuf_error_en = 1'b1;
slave_valid_pre = 1'b1;
slave_valid_pre = 1'b1;
end
endcase
end

154
design/lib/beh_lib.sv
View File

@ -19,8 +19,8 @@
module rvdff #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
@ -33,9 +33,9 @@ module rvdff #( parameter WIDTH=1 )
always_ff @(posedge clk or negedge rst_l) begin
if (rst_l == 0)
dout[WIDTH-1:0] <= 0;
dout[WIDTH-1:0] <= 0;
else
dout[WIDTH-1:0] <= din[WIDTH-1:0];
dout[WIDTH-1:0] <= din[WIDTH-1:0];
end
@ -46,8 +46,8 @@ module rvdffs #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
@ -61,12 +61,12 @@ module rvdffsc #( parameter WIDTH=1 )
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
logic [WIDTH-1:0] din_new;
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
@ -105,7 +105,7 @@ module rvclkhdr
output logic l1clk
);
logic TE;
logic TE;
assign TE = scan_mode;
`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
@ -120,7 +120,7 @@ module rvoclkhdr
output logic l1clk
);
logic TE;
logic TE;
assign TE = scan_mode;
`ifdef RV_FPGA_OPTIMIZE
@ -134,14 +134,14 @@ endmodule
module rvdffe #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
input logic en,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
logic l1clk;
logic l1clk;
`ifdef RV_FPGA_OPTIMIZE
@ -178,7 +178,7 @@ module rvsyncss #(parameter WIDTH = 251)
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
logic [WIDTH-1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
@ -193,11 +193,11 @@ module rvlsadder
output logic [31:0] dout
);
logic cout;
logic sign;
logic cout;
logic sign;
logic [31:12] rs1_inc;
logic [31:12] rs1_dec;
logic [31:12] rs1_inc;
logic [31:12] rs1_dec;
assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
@ -208,8 +208,8 @@ module rvlsadder
assign sign = offset[11];
assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |
({20{ ~sign & cout}} & rs1_inc[31:12]) |
({20{ sign & ~cout}} & rs1_dec[31:12]);
({20{ ~sign & cout}} & rs1_inc[31:12]) |
({20{ sign & ~cout}} & rs1_dec[31:12]);
endmodule // rvlsadder
@ -223,8 +223,8 @@ module rvbradder
output [31:1] dout
);
logic cout;
logic sign;
logic cout;
logic sign;
logic [31:13] pc_inc;
logic [31:13] pc_dec;
@ -239,8 +239,8 @@ module rvbradder
assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |
({19{ ~sign & cout}} & pc_inc[31:13]) |
({19{ sign & ~cout}} & pc_dec[31:13]);
({19{ ~sign & cout}} & pc_inc[31:13]) |
({19{ sign & ~cout}} & pc_dec[31:13]);
endmodule // rvbradder
@ -254,9 +254,9 @@ module rvtwoscomp #( parameter WIDTH=32 )
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
genvar i;
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
@ -273,15 +273,15 @@ module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
output logic [SHIFT-1:0] dout
);
logic done;
logic done;
always_comb begin
dout[SHIFT-1:0] = {SHIFT{1'b0}};
done = 1'b0;
for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
done |= din[i];
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
done |= din[i];
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
end : find_first_one
end
endmodule // rvfindfirst1
@ -292,14 +292,14 @@ module rvfindfirst1hot #( parameter WIDTH=32 )
output logic [WIDTH-1:0] dout
);
logic done;
logic done;
always_comb begin
dout[WIDTH-1:0] = {WIDTH{1'b0}};
done = 1'b0;
for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
dout[i] = ~done & din[i];
done |= din[i];
dout[i] = ~done & din[i];
done |= din[i];
end : find_first_one
end
endmodule // rvfindfirst1hot
@ -314,13 +314,13 @@ module rvmaskandmatch #( parameter WIDTH=32 )
output logic match
);
logic [WIDTH-1:0] matchvec;
logic masken_or_fullmask;
logic [WIDTH-1:0] matchvec;
logic masken_or_fullmask;
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
genvar i;
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
@ -331,45 +331,45 @@ module rvmaskandmatch #( parameter WIDTH=32 )
endmodule // rvmaskandmatch
module rvbtb_tag_hash (
input logic [31:1] pc,
output logic [`RV_BTB_BTAG_SIZE-1:0] hash
);
input logic [31:1] pc,
output logic [`RV_BTB_BTAG_SIZE-1:0] hash
);
`ifndef RV_BTB_BTAG_FOLD
assign hash = {(pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+1] ^
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
`else
assign hash = {(
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
`endif
// assign hash = {pc[`RV_BTB_ADDR_HI+1],(pc[`RV_BTB_ADDR_HI+13:`RV_BTB_ADDR_HI+10] ^
// pc[`RV_BTB_ADDR_HI+9:`RV_BTB_ADDR_HI+6] ^
// pc[`RV_BTB_ADDR_HI+5:`RV_BTB_ADDR_HI+2])};
// pc[`RV_BTB_ADDR_HI+9:`RV_BTB_ADDR_HI+6] ^
// pc[`RV_BTB_ADDR_HI+5:`RV_BTB_ADDR_HI+2])};
endmodule
module rvbtb_addr_hash (
input logic [31:1] pc,
output logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hash
);
input logic [31:1] pc,
output logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hash
);
assign hash[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = pc[`RV_BTB_INDEX1_HI:`RV_BTB_INDEX1_LO] ^
`ifndef RV_BTB_FOLD2_INDEX_HASH
pc[`RV_BTB_INDEX2_HI:`RV_BTB_INDEX2_LO] ^
`ifndef RV_BTB_FOLD2_INDEX_HASH
pc[`RV_BTB_INDEX2_HI:`RV_BTB_INDEX2_LO] ^
`endif
pc[`RV_BTB_INDEX3_HI:`RV_BTB_INDEX3_LO];
pc[`RV_BTB_INDEX3_HI:`RV_BTB_INDEX3_LO];
endmodule
module rvbtb_ghr_hash (
input logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hashin,
input logic [`RV_BHT_GHR_RANGE] ghr,
output logic [`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] hash
);
input logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hashin,
input logic [`RV_BHT_GHR_RANGE] ghr,
output logic [`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] hash
);
// The hash function is too complex to write in verilog for all cases.
// The config script generates the logic string based on the bp config.
@ -405,28 +405,28 @@ endmodule // rvrangechecker
// 16 bit even parity generator
module rveven_paritygen #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
output logic parity_out // generated even parity
);
input logic [WIDTH-1:0] data_in, // Data
output logic parity_out // generated even parity
);
assign parity_out = ^(data_in[WIDTH-1:0]) ;
endmodule // rveven_paritygen
module rveven_paritycheck #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
input logic parity_in,
output logic parity_err // Parity error
);
input logic [WIDTH-1:0] data_in, // Data
input logic parity_in,
output logic parity_err // Parity error
);
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
endmodule // rveven_paritycheck
module rvecc_encode (
input [31:0] din,
output [6:0] ecc_out
);
input [31:0] din,
output [6:0] ecc_out
);
logic [5:0] ecc_out_temp;
assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
@ -441,20 +441,20 @@ logic [5:0] ecc_out_temp;
endmodule // rvecc_encode
module rvecc_decode (
input en,
input [31:0] din,
input [6:0] ecc_in,
input en,
input [31:0] din,
input [6:0] ecc_in,
input sed_ded, // only do detection and no correction. Used for the I$
output [31:0] dout,
output [31:0] dout,
output [6:0] ecc_out,
output single_ecc_error,
output double_ecc_error
output single_ecc_error,
output double_ecc_error
);
);
logic [6:0] ecc_check;
logic [38:0] error_mask;
logic [38:0] din_plus_parity, dout_plus_parity;
logic [6:0] ecc_check;
logic [38:0] error_mask;
logic [38:0] din_plus_parity, dout_plus_parity;
// Generate the ecc bits
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];

246
design/lib/mem_lib.sv
View File

@ -27,12 +27,12 @@ module ram_32768x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [32767:0];
reg [38:0] ram_core [32767:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -51,12 +51,12 @@ module ram_16384x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [16383:0];
reg [38:0] ram_core [16383:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -74,12 +74,12 @@ module ram_8192x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [8191:0];
reg [38:0] ram_core [8191:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -97,12 +97,12 @@ module ram_4096x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [4095:0];
reg [38:0] ram_core [4095:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -120,12 +120,12 @@ module ram_3072x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [3071:0];
reg [38:0] ram_core [3071:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -145,12 +145,12 @@ module ram_2048x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [2047:0];
reg [38:0] ram_core [2047:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -168,12 +168,12 @@ module ram_1536x39 // need this for the 48KB DCCM option
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [1535:0];
reg [38:0] ram_core [1535:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -192,12 +192,12 @@ module ram_1024x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [1023:0];
reg [38:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -215,12 +215,12 @@ module ram_768x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [767:0];
reg [38:0] ram_core [767:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -239,12 +239,12 @@ module ram_512x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [511:0];
reg [38:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -263,12 +263,12 @@ module ram_256x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [255:0];
reg [38:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -287,12 +287,12 @@ module ram_128x39
// behavior to be replaced by actual SRAM in VLE
reg [38:0] ram_core [127:0];
reg [38:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -314,12 +314,12 @@ module ram_1024x20
// behavior to be replaced by actual SRAM in VLE
reg [19:0] ram_core [1023:0];
reg [19:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -336,12 +336,12 @@ module ram_512x20
// behavior to be replaced by actual SRAM in VLE
reg [19:0] ram_core [511:0];
reg [19:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -359,12 +359,12 @@ module ram_256x20
// behavior to be replaced by actual SRAM in VLE
reg [19:0] ram_core [255:0];
reg [19:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -381,12 +381,12 @@ module ram_128x20
// behavior to be replaced by actual SRAM in VLE
reg [19:0] ram_core [127:0];
reg [19:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -404,12 +404,12 @@ module ram_64x20
// behavior to be replaced by actual SRAM in VLE
reg [19:0] ram_core [63:0];
reg [19:0] ram_core [63:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -431,12 +431,12 @@ module ram_4096x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [4095:0];
reg [33:0] ram_core [4095:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -456,12 +456,12 @@ module ram_2048x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [2047:0];
reg [33:0] ram_core [2047:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -481,12 +481,12 @@ module ram_1024x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [1023:0];
reg [33:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -506,12 +506,12 @@ module ram_512x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [511:0];
reg [33:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -531,12 +531,12 @@ module ram_256x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [255:0];
reg [33:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -556,12 +556,12 @@ module ram_128x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [127:0];
reg [33:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -580,12 +580,12 @@ module ram_64x34
// behavior to be replaced by actual SRAM in VLE
reg [33:0] ram_core [63:0];
reg [33:0] ram_core [63:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -607,12 +607,12 @@ module ram_4096x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [4095:0];
reg [41:0] ram_core [4095:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -632,12 +632,12 @@ module ram_2048x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [2047:0];
reg [41:0] ram_core [2047:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -656,12 +656,12 @@ module ram_1024x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [1023:0];
reg [41:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -680,12 +680,12 @@ module ram_512x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [511:0];
reg [41:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -706,12 +706,12 @@ module ram_256x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [255:0];
reg [41:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -731,12 +731,12 @@ module ram_128x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [127:0];
reg [41:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -756,12 +756,12 @@ module ram_64x42
// behavior to be replaced by actual SRAM in VLE
reg [41:0] ram_core [63:0];
reg [41:0] ram_core [63:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -784,12 +784,12 @@ module ram_1024x21
// behavior to be replaced by actual SRAM in VLE
reg [20:0] ram_core [1023:0];
reg [20:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -807,12 +807,12 @@ module ram_512x21
// behavior to be replaced by actual SRAM in VLE
reg [20:0] ram_core [511:0];
reg [20:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -832,12 +832,12 @@ module ram_256x21
// behavior to be replaced by actual SRAM in VLE
reg [20:0] ram_core [255:0];
reg [20:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -857,12 +857,12 @@ module ram_128x21
// behavior to be replaced by actual SRAM in VLE
reg [20:0] ram_core [127:0];
reg [20:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -882,12 +882,12 @@ module ram_64x21
// behavior to be replaced by actual SRAM in VLE
reg [20:0] ram_core [63:0];
reg [20:0] ram_core [63:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -906,12 +906,12 @@ module ram_1024x25
// behavior to be replaced by actual SRAM in VLE
reg [24:0] ram_core [1023:0];
reg [24:0] ram_core [1023:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -932,12 +932,12 @@ module ram_512x25
// behavior to be replaced by actual SRAM in VLE
reg [24:0] ram_core [511:0];
reg [24:0] ram_core [511:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -958,12 +958,12 @@ module ram_256x25
// behavior to be replaced by actual SRAM in VLE
reg [24:0] ram_core [255:0];
reg [24:0] ram_core [255:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -984,12 +984,12 @@ module ram_128x25
// behavior to be replaced by actual SRAM in VLE
reg [24:0] ram_core [127:0];
reg [24:0] ram_core [127:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end
@ -1010,12 +1010,12 @@ module ram_64x25
// behavior to be replaced by actual SRAM in VLE
reg [24:0] ram_core [63:0];
reg [24:0] ram_core [63:0];
always_ff @(posedge CLK) begin
if (WE) begin// for active high WE - must be specified by user
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
ram_core[ADR] <= D; Q <= 'x; end else
Q <= ram_core[ADR];
end

2
design/lsu/lsu.sv
View File

@ -70,7 +70,7 @@ module lsu
output logic [31:0] lsu_imprecise_error_addr_any, // bus store imprecise error address
// Non-blocking loads
input logic dec_nonblock_load_freeze_dc2, //
input logic dec_nonblock_load_freeze_dc2, //
output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam
output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load
output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads

20
design/lsu/lsu_addrcheck.sv
View File

@ -27,7 +27,7 @@ module lsu_addrcheck
(
input logic lsu_freeze_c2_dc2_clk, // clock
input logic lsu_freeze_c2_dc3_clk,
input logic rst_l, // reset
input logic rst_l, // reset
input logic [31:0] start_addr_dc1, // start address for lsu
input logic [31:0] end_addr_dc1, // end address for lsu
@ -44,7 +44,7 @@ module lsu_addrcheck
output logic access_fault_dc1, // access fault
output logic misaligned_fault_dc1, // misaligned
input logic scan_mode
input logic scan_mode
);
`include "global.h"
@ -66,11 +66,11 @@ module lsu_addrcheck
`endif
logic is_sideeffects_dc1, is_aligned_dc1;
logic start_addr_in_dccm_dc1, end_addr_in_dccm_dc1;
logic start_addr_in_dccm_dc1, end_addr_in_dccm_dc1;
logic start_addr_in_dccm_region_dc1, end_addr_in_dccm_region_dc1;
logic start_addr_in_pic_dc1, end_addr_in_pic_dc1;
logic start_addr_in_pic_dc1, end_addr_in_pic_dc1;
logic start_addr_in_pic_region_dc1, end_addr_in_pic_region_dc1;
logic [4:0] csr_idx;
logic [4:0] csr_idx;
logic addr_in_iccm;
logic non_dccm_access_ok;
@ -119,10 +119,10 @@ module lsu_addrcheck
.in_region(end_addr_in_pic_region_dc1)
);
assign addr_in_dccm_dc1 = (start_addr_in_dccm_dc1 & end_addr_in_dccm_dc1);
assign addr_in_pic_dc1 = (start_addr_in_pic_dc1 & end_addr_in_pic_dc1);
assign addr_in_dccm_dc1 = (start_addr_in_dccm_dc1 & end_addr_in_dccm_dc1);
assign addr_in_pic_dc1 = (start_addr_in_pic_dc1 & end_addr_in_pic_dc1);
assign addr_external_dc1 = ~(addr_in_dccm_dc1 | addr_in_pic_dc1); //~addr_in_dccm_region_dc1;
assign addr_external_dc1 = ~(addr_in_dccm_dc1 | addr_in_pic_dc1); //~addr_in_dccm_region_dc1;
assign csr_idx[4:0] = {start_addr_dc1[31:28], 1'b1};
assign is_sideeffects_dc1 = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_dc1 | start_addr_in_pic_region_dc1 | addr_in_iccm); //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
assign is_aligned_dc1 = (lsu_pkt_dc1.word & (start_addr_dc1[1:0] == 2'b0)) |
@ -134,7 +134,7 @@ module lsu_addrcheck
(((`RV_DATA_ACCESS_ENABLE0 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK0)) == (`RV_DATA_ACCESS_ADDR0 | `RV_DATA_ACCESS_MASK0)) |
(`RV_DATA_ACCESS_ENABLE1 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK1)) == (`RV_DATA_ACCESS_ADDR1 | `RV_DATA_ACCESS_MASK1)) |
(`RV_DATA_ACCESS_ENABLE2 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK2)) == (`RV_DATA_ACCESS_ADDR2 | `RV_DATA_ACCESS_MASK2)) |
(`RV_DATA_ACCESS_ENABLE3 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) |
(`RV_DATA_ACCESS_ENABLE3 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) |
(`RV_DATA_ACCESS_ENABLE4 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK4)) == (`RV_DATA_ACCESS_ADDR4 | `RV_DATA_ACCESS_MASK4)) |
(`RV_DATA_ACCESS_ENABLE5 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK5)) == (`RV_DATA_ACCESS_ADDR5 | `RV_DATA_ACCESS_MASK5)) |
(`RV_DATA_ACCESS_ENABLE6 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK6)) == (`RV_DATA_ACCESS_ADDR6 | `RV_DATA_ACCESS_MASK6)) |
@ -178,6 +178,6 @@ module lsu_addrcheck
rvdff #(.WIDTH(1)) is_sideeffects_dc2ff (.din(is_sideeffects_dc1), .dout(is_sideeffects_dc2), .clk(lsu_freeze_c2_dc2_clk), .*);
rvdff #(.WIDTH(1)) is_sideeffects_dc3ff (.din(is_sideeffects_dc2), .dout(is_sideeffects_dc3), .clk(lsu_freeze_c2_dc3_clk), .*);
endmodule // lsu_addrcheck

10
design/lsu/lsu_bus_buffer.sv
View File

@ -118,7 +118,7 @@ module lsu_bus_buffer
output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
// Non-blocking loads
input logic dec_nonblock_load_freeze_dc2,
input logic dec_nonblock_load_freeze_dc2,
output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam
output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load
output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads
@ -126,7 +126,7 @@ module lsu_bus_buffer
output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
output logic lsu_nonblock_load_data_error, // non block load has an error
output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
// PMU events
output logic lsu_pmu_bus_trxn,
@ -246,7 +246,7 @@ module lsu_bus_buffer
// Bus buffer signals
state_t [DEPTH-1:0] buf_state;
logic [DEPTH-1:0][2:0] buf_state_out;
logic [DEPTH-1:0][2:0] buf_state_out;
logic [DEPTH-1:0][1:0] buf_sz;
logic [DEPTH-1:0][31:0] buf_addr;
logic [DEPTH-1:0][3:0] buf_byteen;
@ -666,12 +666,12 @@ module lsu_bus_buffer
buf_error_en[i] = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag == LSU_BUS_TAG'(i))) |
(bus_rsp_write_error & (bus_rsp_write_tag == LSU_BUS_TAG'(i))));
buf_data_in[i][31:0] = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
end
end
DONE: begin
buf_nxtstate[i] = IDLE;
buf_rst[i] = lsu_bus_clk_en_q & (buf_write[i] | ~buf_dual[i] | (buf_state[buf_dualtag[i]] == DONE));
buf_state_en[i] = buf_rst[i];
end
end
default : begin
buf_nxtstate[i] = IDLE;
buf_state_en[i] = '0;

22
design/lsu/lsu_bus_intf.sv
View File

@ -105,7 +105,7 @@ module lsu_bus_intf
output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
// Non-blocking loads
input logic dec_nonblock_load_freeze_dc2,
input logic dec_nonblock_load_freeze_dc2,
output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam
output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load
output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads
@ -113,7 +113,7 @@ module lsu_bus_intf
output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
output logic lsu_nonblock_load_data_error, // non block load has an error
output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
// PMU events
output logic lsu_pmu_bus_trxn,
@ -173,7 +173,7 @@ module lsu_bus_intf
`include "global.h"
logic ld_freeze_dc3;
logic ld_freeze_dc3;
logic lsu_bus_clk_en_q;
logic ldst_dual_dc1, ldst_dual_dc2, ldst_dual_dc3, ldst_dual_dc4, ldst_dual_dc5;
@ -181,8 +181,8 @@ module lsu_bus_intf
logic [3:0] ldst_byteen_dc2, ldst_byteen_dc3, ldst_byteen_dc4, ldst_byteen_dc5;
logic [7:0] ldst_byteen_ext_dc2, ldst_byteen_ext_dc3, ldst_byteen_ext_dc4, ldst_byteen_ext_dc5;
logic [3:0] ldst_byteen_hi_dc2, ldst_byteen_hi_dc3, ldst_byteen_hi_dc4, ldst_byteen_hi_dc5;
logic [3:0] ldst_byteen_lo_dc2, ldst_byteen_lo_dc3, ldst_byteen_lo_dc4, ldst_byteen_lo_dc5;
logic [3:0] ldst_byteen_hi_dc2, ldst_byteen_hi_dc3, ldst_byteen_hi_dc4, ldst_byteen_hi_dc5;
logic [3:0] ldst_byteen_lo_dc2, ldst_byteen_lo_dc3, ldst_byteen_lo_dc4, ldst_byteen_lo_dc5;
logic is_sideeffects_dc4, is_sideeffects_dc5;
@ -198,12 +198,12 @@ module lsu_bus_intf
logic ld_addr_dc4hit_lo_lo, ld_addr_dc4hit_hi_lo, ld_addr_dc4hit_lo_hi, ld_addr_dc4hit_hi_hi;
logic ld_addr_dc5hit_lo_lo, ld_addr_dc5hit_hi_lo, ld_addr_dc5hit_lo_hi, ld_addr_dc5hit_hi_hi;
logic [3:0] ld_byte_dc3hit_lo_lo, ld_byte_dc3hit_hi_lo, ld_byte_dc3hit_lo_hi, ld_byte_dc3hit_hi_hi;
logic [3:0] ld_byte_dc4hit_lo_lo, ld_byte_dc4hit_hi_lo, ld_byte_dc4hit_lo_hi, ld_byte_dc4hit_hi_hi;
logic [3:0] ld_byte_dc5hit_lo_lo, ld_byte_dc5hit_hi_lo, ld_byte_dc5hit_lo_hi, ld_byte_dc5hit_hi_hi;
logic [3:0] ld_byte_dc3hit_lo_lo, ld_byte_dc3hit_hi_lo, ld_byte_dc3hit_lo_hi, ld_byte_dc3hit_hi_hi;
logic [3:0] ld_byte_dc4hit_lo_lo, ld_byte_dc4hit_hi_lo, ld_byte_dc4hit_lo_hi, ld_byte_dc4hit_hi_hi;
logic [3:0] ld_byte_dc5hit_lo_lo, ld_byte_dc5hit_hi_lo, ld_byte_dc5hit_lo_hi, ld_byte_dc5hit_hi_hi;
logic [3:0] ld_byte_hit_lo, ld_byte_dc3hit_lo, ld_byte_dc4hit_lo, ld_byte_dc5hit_lo;
logic [3:0] ld_byte_hit_hi, ld_byte_dc3hit_hi, ld_byte_dc4hit_hi, ld_byte_dc5hit_hi;
logic [3:0] ld_byte_hit_lo, ld_byte_dc3hit_lo, ld_byte_dc4hit_lo, ld_byte_dc5hit_lo;
logic [3:0] ld_byte_hit_hi, ld_byte_dc3hit_hi, ld_byte_dc4hit_hi, ld_byte_dc5hit_hi;
logic [31:0] ld_fwddata_dc3pipe_lo, ld_fwddata_dc4pipe_lo, ld_fwddata_dc5pipe_lo;
logic [31:0] ld_fwddata_dc3pipe_hi, ld_fwddata_dc4pipe_hi, ld_fwddata_dc5pipe_hi;
@ -381,7 +381,7 @@ module lsu_bus_intf
assign {ld_fwddata_dc2_nc[63:32], ld_fwddata_dc2[31:0]} = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_dc2[1:0]);
assign bus_read_data_dc3[31:0] = ld_full_hit_dc3 ? ld_fwddata_dc3[31:0] : ld_bus_data_dc3[31:0];
// Fifo flops
rvdff #(.WIDTH(1)) lsu_full_hit_dc3ff (.din(ld_full_hit_dc2), .dout(ld_full_hit_dc3), .clk(lsu_freeze_c2_dc3_clk), .*);
rvdff #(.WIDTH(32)) lsu_fwddata_dc3ff (.din(ld_fwddata_dc2[31:0]), .dout(ld_fwddata_dc3[31:0]), .clk(lsu_c1_dc3_clk), .*);

8
design/lsu/lsu_dccm_ctl.sv
View File

@ -37,7 +37,7 @@ module lsu_dccm_ctl
input logic rst_l,
input logic clk,
input logic lsu_freeze_dc3, // freze
input lsu_pkt_t lsu_pkt_dc3, // lsu packets
input lsu_pkt_t lsu_pkt_dc1,
input logic addr_in_dccm_dc1, // address maps to dccm
@ -75,7 +75,7 @@ module lsu_dccm_ctl
output logic dccm_dma_rvalid, // dccm serviving the dma load
output logic dccm_dma_ecc_error, // DMA load had ecc error
output logic [63:0] dccm_dma_rdata, // dccm data to dma request
// DCCM ports
output logic dccm_wren, // dccm interface -- write
output logic dccm_rden, // dccm interface -- write
@ -83,7 +83,7 @@ module lsu_dccm_ctl
output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo, // dccm interface -- read address for lo bank
output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi, // dccm interface -- read address for hi bank
output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, // dccm write data
input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // dccm read data back from the dccm
input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // dccm read data back from the dccm
@ -95,7 +95,7 @@ module lsu_dccm_ctl
output logic [31:0] picm_wr_data, // write data
input logic [31:0] picm_rd_data, // read data
input logic scan_mode // scan mode
input logic scan_mode // scan mode
);
`include "global.h"

14
design/lsu/lsu_dccm_mem.sv
View File

@ -29,8 +29,8 @@
module lsu_dccm_mem
import swerv_types::*;
(
input logic clk, // clock
input logic rst_l,
input logic clk, // clock
input logic rst_l,
input logic lsu_freeze_dc3, // freeze
input logic clk_override, // clock override
@ -40,7 +40,7 @@ module lsu_dccm_mem
input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, // write data
output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
@ -52,16 +52,16 @@ module lsu_dccm_mem
localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic rd_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0] wren_bank_q;
logic [DCCM_NUM_BANKS-1:0] rden_bank_q;
logic [DCCM_NUM_BANKS-1:0] wren_bank_q;
logic [DCCM_NUM_BANKS-1:0] rden_bank_q;
logic [DCCM_NUM_BANKS-1:0][DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank_q;
logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_q;

28
design/lsu/lsu_ecc.sv
View File

@ -47,7 +47,7 @@ module lsu_ecc
input logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3, // data forward from the store buffer
input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc3,// which bytes from the store buffer are on
input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3,// which bytes from the store buffer are on
input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_hi_dc3, // raw data from mem
input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_lo_dc3, // raw data from mem
input logic [`RV_DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_dc3, // ecc read out from mem
@ -64,7 +64,7 @@ module lsu_ecc
output logic lsu_single_ecc_error_dc3, // or of the 2
output logic lsu_double_ecc_error_dc3, // double error detected
input logic scan_mode
input logic scan_mode
);
`include "global.h"
@ -84,14 +84,14 @@ module lsu_ecc
logic ldst_dual_dc3;
logic is_ldst_dc3;
logic is_ldst_hi_dc3, is_ldst_lo_dc3;
logic [7:0] ldst_byteen_dc3;
logic [7:0] store_byteen_dc3;
logic [7:0] ldst_byteen_dc3;
logic [7:0] store_byteen_dc3;
logic [7:0] store_byteen_ext_dc3;
logic [DCCM_BYTE_WIDTH-1:0] store_byteen_hi_dc3, store_byteen_lo_dc3;
logic [DCCM_BYTE_WIDTH-1:0] store_byteen_hi_dc3, store_byteen_lo_dc3;
logic [163:0] store_data_ext_dc3;
logic [DCCM_DATA_WIDTH-1:0] store_data_hi_dc3, store_data_lo_dc3;
logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
assign ldst_dual_dc3 = (lsu_addr_dc3[2] != end_addr_dc3[2]);
@ -128,28 +128,28 @@ module lsu_ecc
rvecc_decode lsu_ecc_decode_hi (
// Inputs
.en(is_ldst_hi_dc3),
.sed_ded (1'b0), // 1 : means only detection
.sed_ded (1'b0), // 1 : means only detection
.din(dccm_data_hi_dc3[DCCM_DATA_WIDTH-1:0]),
.ecc_in(dccm_data_ecc_hi_dc3[DCCM_ECC_WIDTH-1:0]),
// Outputs
.dout(sec_data_hi_dc3[DCCM_DATA_WIDTH-1:0]),
.ecc_out (ecc_out_hi_nc[6:0]),
.single_ecc_error(single_ecc_error_hi_dc3),
.double_ecc_error(double_ecc_error_hi_dc3),
.ecc_out (ecc_out_hi_nc[6:0]),
.single_ecc_error(single_ecc_error_hi_dc3),
.double_ecc_error(double_ecc_error_hi_dc3),
.*
);
rvecc_decode lsu_ecc_decode_lo (
// Inputs
// Inputs
.en(is_ldst_lo_dc3),
.sed_ded (1'b0), // 1 : means only detection
.sed_ded (1'b0), // 1 : means only detection
.din(dccm_data_lo_dc3[DCCM_DATA_WIDTH-1:0] ),
.ecc_in(dccm_data_ecc_lo_dc3[DCCM_ECC_WIDTH-1:0]),
// Outputs
.dout(sec_data_lo_dc3[DCCM_DATA_WIDTH-1:0]),
.ecc_out (ecc_out_lo_nc[6:0]),
.single_ecc_error(single_ecc_error_lo_dc3),
.double_ecc_error(double_ecc_error_lo_dc3),
.single_ecc_error(single_ecc_error_lo_dc3),
.double_ecc_error(double_ecc_error_lo_dc3),
.*
);

70
design/lsu/lsu_stbuf.sv
View File

@ -47,7 +47,7 @@ module lsu_stbuf
input logic lsu_stbuf_c1_clk, // stbuf clock
input logic lsu_free_c2_clk, // free clk
// Store Buffer input
// Store Buffer input
input logic load_stbuf_reqvld_dc3, // core instruction goes to stbuf
input logic store_stbuf_reqvld_dc3, // core instruction goes to stbuf
//input logic ldst_stbuf_reqvld_dc3,
@ -61,14 +61,14 @@ module lsu_stbuf
input logic isldst_dc1, // instruction in dc1 is lsu
input logic dccm_ldst_dc2, // instruction in dc2 is lsu
input logic dccm_ldst_dc3, // instruction in dc3 is lsu
input logic single_ecc_error_hi_dc3, // single ecc error in hi bank
input logic single_ecc_error_lo_dc3, // single ecc error in lo bank
input logic single_ecc_error_hi_dc3, // single ecc error in hi bank
input logic single_ecc_error_lo_dc3, // single ecc error in lo bank
input logic lsu_single_ecc_error_dc5, // single_ecc_error in either bank staged to the dc5 - needed for the load repairs
input logic lsu_commit_dc5, // lsu commits
input logic lsu_freeze_dc3, // lsu freeze
input logic flush_prior_dc5, // Flush is due to i0 and ld/st is in i1
// Store Buffer output
output logic stbuf_reqvld_any, // stbuf is draining
output logic stbuf_reqvld_flushed_any, // Top entry is flushed
@ -85,16 +85,16 @@ module lsu_stbuf
input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc1, // lsu address
input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc2,
input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc3,
input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc1, // lsu end addrress - needed to check unaligned
input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc2,
input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc3,
// Forwarding signals
input logic lsu_cmpen_dc2, // needed for forwarding stbuf - load
input lsu_pkt_t lsu_pkt_dc2,
input lsu_pkt_t lsu_pkt_dc3,
input lsu_pkt_t lsu_pkt_dc5,
input lsu_pkt_t lsu_pkt_dc3,
input lsu_pkt_t lsu_pkt_dc5,
output logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_dc3, // stbuf data
output logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3,
@ -102,7 +102,7 @@ module lsu_stbuf
output logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3,
input logic scan_mode
);
`include "global.h"
@ -121,19 +121,19 @@ module lsu_stbuf
logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteen;
logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_data;
logic [DEPTH-1:0] sel_lo;
logic [DEPTH-1:0] stbuf_wr_en;
logic [DEPTH-1:0] stbuf_data_en;
logic [DEPTH-1:0] stbuf_drain_or_flush_en;
logic [DEPTH-1:0] stbuf_flush_en;
logic [DEPTH-1:0] stbuf_drain_en;
logic [DEPTH-1:0] stbuf_reset;
logic [DEPTH-1:0] sel_lo;
logic [DEPTH-1:0] stbuf_wr_en;
logic [DEPTH-1:0] stbuf_data_en;
logic [DEPTH-1:0] stbuf_drain_or_flush_en;
logic [DEPTH-1:0] stbuf_flush_en;
logic [DEPTH-1:0] stbuf_drain_en;
logic [DEPTH-1:0] stbuf_reset;
logic [DEPTH-1:0][LSU_SB_BITS-1:0] stbuf_addrin;
logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_datain;
logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteenin;
logic [7:0] ldst_byteen_dc3;
logic [7:0] store_byteen_ext_dc3;
logic [7:0] store_byteen_ext_dc3;
logic [BYTE_WIDTH-1:0] store_byteen_hi_dc3;
logic [BYTE_WIDTH-1:0] store_byteen_lo_dc3;
@ -150,8 +150,8 @@ module lsu_stbuf
logic ldst_stbuf_reqvld_dc4, ldst_stbuf_reqvld_dc5;
logic dual_stbuf_write_dc4, dual_stbuf_write_dc5;
logic [3:0] stbuf_numvld_any, stbuf_specvld_any;
logic [1:0] stbuf_specvld_dc1, stbuf_specvld_dc2, stbuf_specvld_dc3;
logic [3:0] stbuf_numvld_any, stbuf_specvld_any;
logic [1:0] stbuf_specvld_dc1, stbuf_specvld_dc2, stbuf_specvld_dc3;
logic stbuf_oneavl_any, stbuf_twoavl_any;
logic cmpen_hi_dc2, cmpen_lo_dc2, jit_in_same_region;
@ -169,7 +169,7 @@ module lsu_stbuf
logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_fwdbyteenvec_hi, stbuf_fwdbyteenvec_lo;
logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_fwddatavec_hi, stbuf_fwddatavec_lo;
logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_dc2, stbuf_fwddata_lo_dc2;
logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_fn_dc2, stbuf_fwddata_lo_fn_dc2;
logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_fn_dc2, stbuf_fwddata_lo_fn_dc2;
logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc2, stbuf_fwdbyteen_lo_dc2;
logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_fn_dc2, stbuf_fwdbyteen_lo_fn_dc2;
logic stbuf_load_repair_dc5;
@ -204,7 +204,7 @@ module lsu_stbuf
(i == WrPtrPlus1[DEPTH_LOG2-1:0] & dual_stbuf_write_dc3));
assign stbuf_data_en[i] = stbuf_wr_en[i];
assign stbuf_drain_or_flush_en[i] = ldst_stbuf_reqvld_dc5 & ~lsu_pkt_dc5.dma & ((i == WrPtr_dc5[DEPTH_LOG2-1:0]) |
(i == WrPtrPlus1_dc5[DEPTH_LOG2-1:0] & dual_stbuf_write_dc5));
(i == WrPtrPlus1_dc5[DEPTH_LOG2-1:0] & dual_stbuf_write_dc5));
assign stbuf_drain_en[i] = (stbuf_drain_or_flush_en[i] & (lsu_commit_dc5 | stbuf_load_repair_dc5)) | (stbuf_wr_en[i] & lsu_pkt_dc3.dma);
assign stbuf_flush_en[i] = stbuf_drain_or_flush_en[i] & ~(lsu_commit_dc5 | stbuf_load_repair_dc5);
assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2-1:0]);
@ -303,7 +303,7 @@ module lsu_stbuf
assign stbuf_fwddata_lo_hi[(8*i)+7:(8*i)] = {8{stbuf_fwdbyteen_lo_hi[i]}} & store_ecc_datafn_hi_dc3[(8*i)+7:(8*i)];
assign stbuf_fwddata_lo_lo[(8*i)+7:(8*i)] = {8{stbuf_fwdbyteen_lo_lo[i]}} & store_ecc_datafn_lo_dc3[(8*i)+7:(8*i)];
end
always_comb begin: GenLdFwd
stbuf_fwdbyteen_hi_dc2[BYTE_WIDTH-1:0] = '0;
@ -314,13 +314,13 @@ module lsu_stbuf
stbuf_ldmatch_lo[i] = (stbuf_addr[i][LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == cmpaddr_lo_dc2[LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) &
(stbuf_drain_vld[i] | ~lsu_pkt_dc2.dma) & ~stbuf_flush_vld[i] & ((stbuf_addr_in_pic[i] & addr_in_pic_dc2) | (~stbuf_addr_in_pic[i] & addr_in_dccm_dc2));
for (int j=0; j<BYTE_WIDTH; j++) begin
for (int j=0; j<BYTE_WIDTH; j++) begin
stbuf_fwdbyteenvec_hi[i][j] = stbuf_ldmatch_hi[i] & stbuf_byteen[i][j] & stbuf_data_vld[i];
stbuf_fwdbyteen_hi_dc2[j] |= stbuf_fwdbyteenvec_hi[i][j];
stbuf_fwdbyteenvec_lo[i][j] = stbuf_ldmatch_lo[i] & stbuf_byteen[i][j] & stbuf_data_vld[i];
stbuf_fwdbyteen_lo_dc2[j] |= stbuf_fwdbyteenvec_lo[i][j];
end
end
end
end // block: GenLdFwd
@ -338,34 +338,34 @@ module lsu_stbuf
// Byte0
if (stbuf_fwdbyteenvec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][0]) begin
stbuf_fwddata_hi_dc2[7:0] = stbuf_fwddatavec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][7:0];
end
end
if (stbuf_fwdbyteenvec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][0]) begin
stbuf_fwddata_lo_dc2[7:0] = stbuf_fwddatavec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][7:0];
end
end
// Byte1
if (stbuf_fwdbyteenvec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][1]) begin
stbuf_fwddata_hi_dc2[15:8] = stbuf_fwddatavec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][15:8];
end
end
if (stbuf_fwdbyteenvec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][1]) begin
stbuf_fwddata_lo_dc2[15:8] = stbuf_fwddatavec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][15:8];
end
end
// Byte2
if (stbuf_fwdbyteenvec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][2]) begin
stbuf_fwddata_hi_dc2[23:16] = stbuf_fwddatavec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][23:16];
end
end
if (stbuf_fwdbyteenvec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][2]) begin
stbuf_fwddata_lo_dc2[23:16] = stbuf_fwddatavec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][23:16];
end
end
// Byte3
if (stbuf_fwdbyteenvec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][3]) begin
stbuf_fwddata_hi_dc2[31:24] = stbuf_fwddatavec_hi[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][31:24];
end
end
if (stbuf_fwdbyteenvec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][3]) begin
stbuf_fwddata_lo_dc2[31:24] = stbuf_fwddatavec_lo[DEPTH_LOG2'(WrPtr[DEPTH_LOG2-1:0] + DEPTH_LOG2'(i))][31:24];
end
end
end
end
@ -399,4 +399,4 @@ module lsu_stbuf
`endif
endmodule

6
design/lsu/lsu_trigger.sv
View File

@ -25,9 +25,9 @@
module lsu_trigger
import swerv_types::*;
(
input logic clk, // clock
input logic lsu_free_c2_clk, // clock
input logic rst_l, // reset
input logic clk, // clock
input logic lsu_free_c2_clk, // clock
input logic rst_l, // reset
input trigger_pkt_t [3:0] trigger_pkt_any, // trigger packet from dec
input lsu_pkt_t lsu_pkt_dc3, // lsu packet

8
design/mem.sv
View File

@ -18,13 +18,13 @@
module mem
import swerv_types::*;
(
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
input logic lsu_freeze_dc3,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
@ -45,7 +45,7 @@ module mem
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [155:0] iccm_rd_data,
`endif
// Icache and Itag Ports

14
design/pic_ctrl.sv
View File

@ -24,10 +24,10 @@ module pic_ctrl
(
input logic clk, // Core clock
input logic free_clk, // free clock
input logic active_clk, // active clock
input logic free_clk, // free clock
input logic active_clk, // active clock
input logic rst_l, // Reset for all flops
input logic clk_override, // Clock over-ride for gating
input logic clk_override, // Clock over-ride for gating
input logic [`RV_PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req, // Interrupt requests
input logic [31:0] picm_addr, // Address of the register
input logic [31:0] picm_wr_data, // Data to be written to the register
@ -42,7 +42,7 @@ module pic_ctrl
output logic [3:0] pl, // Priority level of the requested interrupt
output logic [31:0] picm_rd_data, // Read data of the register
output logic mhwakeup, // Wake-up interrupt request
input logic scan_mode // scan mode
input logic scan_mode // scan mode
);
`include "global.h"
@ -125,14 +125,14 @@ logic [TOTAL_INT-1:0] extintsrc_req_sync;
logic [TOTAL_INT-1:0] extintsrc_req_gw;
// clkens
logic pic_addr_c1_clken;
logic pic_addr_c1_clken;
logic pic_data_c1_clken;
logic pic_pri_c1_clken;
logic pic_int_c1_clken;
logic gw_config_c1_clken;
// clocks
logic pic_addr_c1_clk;
logic pic_addr_c1_clk;
logic pic_data_c1_clk;
logic pic_pri_c1_clk;
logic pic_int_c1_clk;
@ -174,7 +174,7 @@ rvsyncss #(TOTAL_INT-1) sync_inst
(
.clk (free_clk),
.dout(extintsrc_req_sync[TOTAL_INT-1:1]),
.din (extintsrc_req[TOTAL_INT-1:1]),
.din (extintsrc_req[TOTAL_INT-1:1]),
.*) ;
assign extintsrc_req_sync[0] = extintsrc_req[0];

190
design/swerv.sv
View File

@ -23,11 +23,11 @@
module swerv
import swerv_types::*;
(
input logic clk,
input logic rst_l,
input logic clk,
input logic rst_l,
input logic [31:1] rst_vec,
input logic nmi_int,
input logic [31:1] nmi_vec,
input logic [31:1] nmi_vec,
input logic [31:1] jtag_id,
output logic core_rst_l, // This is "rst_l | dbg_rst_l"
@ -39,7 +39,7 @@ module swerv
output logic [2:0] trace_rv_i_interrupt_ip,
output logic [31:0] trace_rv_i_tval_ip,
output logic lsu_freeze_dc3,
output logic dccm_clk_override,
output logic icm_clk_override,
@ -65,15 +65,15 @@ module swerv
output logic [1:0] dec_tlu_perfcnt1,
output logic [1:0] dec_tlu_perfcnt2,
output logic [1:0] dec_tlu_perfcnt3,
// DCCM ports
// DCCM ports
output logic dccm_wren,
output logic dccm_rden,
output logic [`RV_DCCM_BITS-1:0] dccm_wr_addr,
output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo,
output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi,
output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data,
input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
@ -315,7 +315,7 @@ module swerv
output logic [1:0] htrans,
output logic hwrite,
input logic [63:0] hrdata,
input logic [63:0] hrdata,
input logic hready,
input logic hresp,
@ -328,12 +328,12 @@ module swerv
output logic [1:0] lsu_htrans,
output logic lsu_hwrite,
output logic [63:0] lsu_hwdata,
input logic [63:0] lsu_hrdata,
input logic lsu_hready,
input logic lsu_hresp,
//System Bus Debug Master
//System Bus Debug Master
output logic [31:0] sb_haddr,
output logic [2:0] sb_hburst,
output logic sb_hmastlock,
@ -342,7 +342,7 @@ module swerv
output logic [1:0] sb_htrans,
output logic sb_hwrite,
output logic [63:0] sb_hwdata,
input logic [63:0] sb_hrdata,
input logic sb_hready,
input logic sb_hresp,
@ -370,14 +370,14 @@ module swerv
input logic dbg_bus_clk_en,
input logic dma_bus_clk_en,
// JTAG ports
input logic jtag_tck, // JTAG clk
input logic jtag_tms, // JTAG TMS
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
// JTAG ports
input logic jtag_tck, // JTAG clk
input logic jtag_tms, // JTAG TMS
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
output logic jtag_tdo, // JTAG TDO
input logic [`RV_PIC_TOTAL_INT:1] extintsrc_req,
input logic timer_int,
input logic scan_mode
@ -584,8 +584,8 @@ module swerv
//
//----------------------------------------------------------------------
logic [1:0] ifu_pmu_instr_aligned;
logic ifu_pmu_align_stall;
logic [1:0] ifu_pmu_instr_aligned;
logic ifu_pmu_align_stall;
logic dma_slv_algn_err;
// Icache debug
`ifdef RV_ICACHE_ECC
@ -618,9 +618,9 @@ module swerv
// Trigger signals
trigger_pkt_t [3:0] trigger_pkt_any;
logic [3:0] lsu_trigger_match_dc3;
logic dec_ib3_valid_d, dec_ib2_valid_d;
logic dec_ib1_valid_eff_d;
logic dec_ib0_valid_eff_d;
logic dec_ib3_valid_d, dec_ib2_valid_d;
logic dec_ib1_valid_eff_d;
logic dec_ib0_valid_eff_d;
logic [31:0] dec_i0_immed_d;
@ -629,28 +629,28 @@ module swerv
logic [12:1] dec_i0_br_immed_d;
logic [12:1] dec_i1_br_immed_d;
logic dec_i0_select_pc_d;
logic dec_i1_select_pc_d;
logic dec_i0_select_pc_d;
logic dec_i1_select_pc_d;
logic [31:1] dec_i0_pc_d, dec_i1_pc_d;
logic dec_i0_rs1_bypass_en_d;
logic dec_i0_rs2_bypass_en_d;
logic dec_i1_rs1_bypass_en_d;
logic dec_i1_rs2_bypass_en_d;
logic dec_i0_rs1_bypass_en_d;
logic dec_i0_rs2_bypass_en_d;
logic dec_i1_rs1_bypass_en_d;
logic dec_i1_rs2_bypass_en_d;
logic dec_i0_alu_decode_d;
logic dec_i1_alu_decode_d;
logic dec_i0_alu_decode_d;
logic dec_i1_alu_decode_d;
rets_pkt_t exu_rets_e1_pkt;
rets_pkt_t exu_rets_e4_pkt;
logic dec_tlu_cancel_e4;
logic ifu_miss_state_idle;
logic dec_tlu_flush_noredir_wb;
logic ifu_miss_state_idle;
logic dec_tlu_flush_noredir_wb;
logic dec_tlu_flush_leak_one_wb;
logic dec_tlu_flush_err_wb;
logic ifu_i0_valid, ifu_i1_valid;
logic ifu_i0_valid, ifu_i1_valid;
logic [31:0] ifu_i0_instr, ifu_i1_instr;
logic [31:1] ifu_i0_pc, ifu_i1_pc;
@ -696,14 +696,14 @@ module swerv
logic flush_final_e3;
logic i0_flush_final_e3;
logic dec_csr_ren_d;
logic dec_csr_ren_d;
logic [31:0] exu_csr_rs1_e1;
logic dec_tlu_flush_lower_wb;
logic dec_tlu_flush_lower_wb;
logic dec_tlu_i0_kill_writeb_wb; // I0 is flushed, don't writeback any results to arch state
logic dec_tlu_i1_kill_writeb_wb; // I1 is flushed, don't writeback any results to arch state
logic dec_tlu_fence_i_wb; // flush is a fence_i rfnpc, flush icache
logic dec_tlu_fence_i_wb; // flush is a fence_i rfnpc, flush icache
logic dec_tlu_i0_valid_e4;
logic dec_tlu_i1_valid_e4;
@ -763,8 +763,8 @@ module swerv
logic [31:0] i1_rs1_bypass_data_e2;
logic [31:0] i1_rs2_bypass_data_e2;
logic exu_i0_flush_lower_e4; // to tlu for lower branch flushes
logic exu_i1_flush_lower_e4;
logic exu_i0_flush_lower_e4; // to tlu for lower branch flushes
logic exu_i1_flush_lower_e4;
logic [31:1] exu_i0_flush_path_e4;
logic [31:1] exu_i1_flush_path_e4;
@ -773,7 +773,7 @@ module swerv
predict_pkt_t exu_mp_pkt;
logic [`RV_BHT_GHR_RANGE] exu_mp_eghr;
logic [`RV_BHT_GHR_RANGE] exu_mp_eghr;
logic [`RV_BHT_GHR_RANGE] exu_i0_br_fghr_e4;
logic [1:0] exu_i0_br_hist_e4;
@ -781,9 +781,9 @@ module swerv
logic exu_i0_br_error_e4;
logic exu_i0_br_start_error_e4;
logic exu_i0_br_valid_e4;
logic exu_i0_br_mp_e4;
logic exu_i0_br_mp_e4;
logic exu_i0_br_ret_e4;
logic exu_i0_br_call_e4;
logic exu_i0_br_call_e4;
logic exu_i0_br_middle_e4;
logic [`RV_BHT_GHR_RANGE] exu_i1_br_fghr_e4;
@ -792,9 +792,9 @@ module swerv
logic exu_i1_br_error_e4;
logic exu_i1_br_start_error_e4;
logic exu_i1_br_valid_e4;
logic exu_i1_br_mp_e4;
logic exu_i1_br_mp_e4;
logic exu_i1_br_ret_e4;
logic exu_i1_br_call_e4;
logic exu_i1_br_call_e4;
logic exu_i1_br_middle_e4;
`ifdef RV_BTB_48
@ -804,7 +804,7 @@ module swerv
logic exu_i0_br_way_e4;
logic exu_i1_br_way_e4;
`endif
logic dec_i0_lsu_decode_d;
logic dec_i0_lsu_decode_d;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] exu_i0_br_index_e4;
logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] exu_i1_br_index_e4;
@ -819,7 +819,7 @@ module swerv
logic dccm_dma_rvalid;
logic dccm_dma_ecc_error;
logic [63:0] dccm_dma_rdata;
logic iccm_dma_rvalid;
logic iccm_dma_rvalid;
logic iccm_dma_ecc_error;
logic [63:0] iccm_dma_rdata;
@ -833,16 +833,16 @@ module swerv
logic [31:0] i0_result_e2;
logic ifu_i0_icaf;
logic ifu_i1_icaf;
logic ifu_i0_icaf_f1;
logic ifu_i1_icaf_f1;
logic ifu_i0_perr;
logic ifu_i1_perr;
logic ifu_i0_sbecc;
logic ifu_i1_sbecc;
logic ifu_i0_dbecc;
logic ifu_i1_dbecc;
logic ifu_i0_icaf;
logic ifu_i1_icaf;
logic ifu_i0_icaf_f1;
logic ifu_i1_icaf_f1;
logic ifu_i0_perr;
logic ifu_i1_perr;
logic ifu_i0_sbecc;
logic ifu_i1_sbecc;
logic ifu_i0_dbecc;
logic ifu_i1_dbecc;
logic iccm_dma_sb_error;
br_pkt_t i0_brp;
@ -890,7 +890,7 @@ module swerv
logic dbg_cmd_valid; // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen
logic dbg_cmd_write; // 1: write command; 0: read_command
logic [1:0] dbg_cmd_type; // 0:gpr 1:csr 2: memory
logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command
logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command
logic dbg_halt_req; // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )
logic dbg_resume_req; // Sticky signal indicating that the debug module wants to resume from debug mode
logic dbg_core_rst_l; // Core reset from DM
@ -909,28 +909,28 @@ module swerv
logic [31:0] dec_dbg_rddata; // The core drives this data ( intercepts the pipe and sends it here )
logic dec_dbg_cmd_done; // This will be treated like a valid signal
logic dec_dbg_cmd_fail; // Abstract command failed
logic dec_tlu_mpc_halted_only; // Only halted due to MPC
logic dec_tlu_mpc_halted_only; // Only halted due to MPC
logic dec_tlu_dbg_halted; // The core has finished the queiscing sequence. Sticks this signal high
logic dec_tlu_pmu_fw_halted; // The core has finished the queiscing sequence. Sticks this signal high
logic dec_tlu_resume_ack;
logic dec_tlu_debug_mode; // Core is in debug mode
logic dec_debug_wdata_rs1_d;
logic dec_tlu_stall_dma; // stall dma accesses, tlu is attempting to enter halt/debug mode
logic dec_debug_wdata_rs1_d;
logic dec_tlu_stall_dma; // stall dma accesses, tlu is attempting to enter halt/debug mode
logic [4:2] dec_i0_data_en;
logic [4:1] dec_i0_ctl_en;
logic [4:2] dec_i1_data_en;
logic [4:1] dec_i1_ctl_en;
logic [4:2] dec_i0_data_en;
logic [4:1] dec_i0_ctl_en;
logic [4:2] dec_i1_data_en;
logic [4:1] dec_i1_ctl_en;
logic dec_nonblock_load_freeze_dc2;
logic dec_nonblock_load_freeze_dc2;
// PMU Signals
logic exu_pmu_i0_br_misp;
logic exu_pmu_i0_br_ataken;
logic exu_pmu_i0_pc4;
logic exu_pmu_i1_br_misp;
logic exu_pmu_i1_br_ataken;
logic exu_pmu_i1_pc4;
logic exu_pmu_i0_br_misp;
logic exu_pmu_i0_br_ataken;
logic exu_pmu_i0_pc4;
logic exu_pmu_i1_br_misp;
logic exu_pmu_i1_br_ataken;
logic exu_pmu_i1_pc4;
logic lsu_pmu_misaligned_dc3;
logic lsu_pmu_bus_trxn;
@ -938,21 +938,21 @@ module swerv
logic lsu_pmu_bus_error;
logic lsu_pmu_bus_busy;
logic ifu_pmu_fetch_stall;
logic ifu_pmu_fetch_stall;
logic ifu_pmu_ic_miss;
logic ifu_pmu_ic_hit;
logic ifu_pmu_bus_error;
logic ifu_pmu_bus_busy;
logic ifu_pmu_bus_trxn;
logic active_state;
logic free_clk, active_clk;
logic active_state;
logic free_clk, active_clk;
logic dec_pause_state_cg;
logic lsu_nonblock_load_data_error;
logic lsu_nonblock_load_data_error;
logic [15:0] ifu_i0_cinst;
logic [15:0] ifu_i1_cinst;
logic [15:0] ifu_i0_cinst;
logic [15:0] ifu_i1_cinst;
trace_pkt_t trace_rv_trace_pkt;
@ -976,15 +976,15 @@ module swerv
logic dmi_reg_en; // read or write
logic [6:0] dmi_reg_addr; // address of DM register
logic dmi_reg_wr_en; // write instruction
logic [31:0] dmi_reg_wdata; // write data
logic [31:0] dmi_reg_wdata; // write data
// outputs from the dbg back to jtag
logic [31:0] dmi_reg_rdata;
logic [31:0] dmi_reg_rdata;
logic dmi_hard_reset;
logic jtag_tdoEn;
// Instantiat the JTAG/DMI
dmi_wrapper dmi_wrapper (
// Instantiat the JTAG/DMI
dmi_wrapper dmi_wrapper (
.scan_mode(scan_mode), // scan mode
// JTAG signals
@ -1021,10 +1021,10 @@ module swerv
dec dec (
.dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
.rst_l(core_rst_l),
.*
);
.dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
.rst_l(core_rst_l),
.*
);
exu exu (
.clk_override(dec_tlu_exu_clk_override),
@ -1039,21 +1039,21 @@ module swerv
);
logic [7:0] pic_claimid;
logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
logic mexintpend;
logic mhwakeup;
logic dec_tlu_claim_ack_wb;
logic dec_tlu_claim_ack_wb;
pic_ctrl pic_ctrl_inst (
.clk_override(dec_tlu_pic_clk_override),
.picm_mken (picm_mken),
.extintsrc_req({extintsrc_req[`RV_PIC_TOTAL_INT:1],1'b0}),
.pl(pic_pl[3:0]),
.claimid(pic_claimid[7:0]),
.meicurpl(dec_tlu_meicurpl[3:0]),
.meipt(dec_tlu_meipt[3:0]),
.pl(pic_pl[3:0]),
.claimid(pic_claimid[7:0]),
.meicurpl(dec_tlu_meicurpl[3:0]),
.meipt(dec_tlu_meipt[3:0]),
.rst_l(core_rst_l),
.*);
@ -1244,7 +1244,7 @@ module swerv
.axi_awprot(dma_axi_awprot[2:0]),
.axi_awlen(dma_axi_awlen[7:0]),
.axi_awburst(dma_axi_awburst[1:0]),
.axi_wvalid(dma_axi_wvalid),
.axi_wready(dma_axi_wready),
.axi_wdata(dma_axi_wdata[63:0]),
@ -1255,7 +1255,7 @@ module swerv
.axi_bready(dma_axi_bready),
.axi_bresp(dma_axi_bresp[1:0]),
.axi_bid(dma_axi_bid[DMA_BUS_TAG-1:0]),
// AXI Read Channels
.axi_arvalid(dma_axi_arvalid),
.axi_arready(dma_axi_arready),
@ -1265,12 +1265,12 @@ module swerv
.axi_arprot(dma_axi_arprot[2:0]),
.axi_arlen(dma_axi_arlen[7:0]),
.axi_arburst(dma_axi_arburst[1:0]),
.axi_rvalid(dma_axi_rvalid),
.axi_rready(dma_axi_rready),
.axi_rid(dma_axi_rid[DMA_BUS_TAG-1:0]),
.axi_rdata(dma_axi_rdata[63:0]),
.axi_rresp(dma_axi_rresp[1:0]),
.axi_rresp(dma_axi_rresp[1:0]),
// AHB signals
.ahb_haddr(dma_haddr[31:0]),

124
design/swerv_wrapper.sv
View File

@ -25,11 +25,11 @@
module swerv_wrapper
import swerv_types::*;
(
input logic clk,
input logic rst_l,
input logic [31:1] rst_vec,
input logic clk,
input logic rst_l,
input logic [31:1] rst_vec,
input logic nmi_int,
input logic [31:1] nmi_vec,
input logic [31:1] nmi_vec,
input logic [31:1] jtag_id,
@ -223,37 +223,37 @@ module swerv_wrapper
output logic [`RV_DMA_BUS_TAG-1:0] dma_axi_rid,
output logic [63:0] dma_axi_rdata,
output logic [1:0] dma_axi_rresp,
output logic dma_axi_rlast,
output logic dma_axi_rlast,
`endif
`ifdef RV_BUILD_AHB_LITE
//// AHB LITE BUS
output logic [31:0] haddr,
output logic [2:0] hburst,
output logic hmastlock,
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
output logic hwrite,
output logic [31:0] haddr,
output logic [2:0] hburst,
output logic hmastlock,
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
output logic hwrite,
input logic [63:0] hrdata,
input logic hready,
input logic hresp,
input logic [63:0] hrdata,
input logic hready,
input logic hresp,
// LSU AHB Master
output logic [31:0] lsu_haddr,
output logic [2:0] lsu_hburst,
output logic lsu_hmastlock,
output logic [3:0] lsu_hprot,
output logic [2:0] lsu_hsize,
output logic [1:0] lsu_htrans,
output logic lsu_hwrite,
output logic [63:0] lsu_hwdata,
output logic [31:0] lsu_haddr,
output logic [2:0] lsu_hburst,
output logic lsu_hmastlock,
output logic [3:0] lsu_hprot,
output logic [2:0] lsu_hsize,
output logic [1:0] lsu_htrans,
output logic lsu_hwrite,
output logic [63:0] lsu_hwdata,
input logic [63:0] lsu_hrdata,
input logic lsu_hready,
input logic lsu_hresp,
input logic [63:0] lsu_hrdata,
input logic lsu_hready,
input logic lsu_hresp,
// Debug Syster Bus AHB
output logic [31:0] sb_haddr,
output logic [2:0] sb_hburst,
@ -263,39 +263,39 @@ module swerv_wrapper
output logic [1:0] sb_htrans,
output logic sb_hwrite,
output logic [63:0] sb_hwdata,
input logic [63:0] sb_hrdata,
input logic sb_hready,
input logic sb_hresp,
// DMA Slave
input logic [31:0] dma_haddr,
input logic [2:0] dma_hburst,
input logic dma_hmastlock,
input logic [3:0] dma_hprot,
input logic [2:0] dma_hsize,
input logic [1:0] dma_htrans,
input logic dma_hwrite,
input logic [63:0] dma_hwdata,
input logic [31:0] dma_haddr,
input logic [2:0] dma_hburst,
input logic dma_hmastlock,
input logic [3:0] dma_hprot,
input logic [2:0] dma_hsize,
input logic [1:0] dma_htrans,
input logic dma_hwrite,
input logic [63:0] dma_hwdata,
input logic dma_hsel,
input logic dma_hreadyin,
input logic dma_hreadyin,
output logic [63:0] dma_hrdata,
output logic dma_hreadyout,
output logic dma_hresp,
output logic [63:0] dma_hrdata,
output logic dma_hreadyout,
output logic dma_hresp,
`endif
// clk ratio signals
input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
// input logic ext_int,
input logic timer_int,
input logic timer_int,
input logic [`RV_PIC_TOTAL_INT:1] extintsrc_req,
output logic [1:0] dec_tlu_perfcnt0, // toggles when perf counter 0 has an event inc
@ -303,12 +303,12 @@ module swerv_wrapper
output logic [1:0] dec_tlu_perfcnt2,
output logic [1:0] dec_tlu_perfcnt3,
// ports added by the soc team
input logic jtag_tck, // JTAG clk
input logic jtag_tms, // JTAG TMS
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
output logic jtag_tdo, // JTAG TDO
// ports added by the soc team
input logic jtag_tck, // JTAG clk
input logic jtag_tms, // JTAG TMS
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
output logic jtag_tdo, // JTAG TDO
// external MPC halt/run interface
input logic mpc_debug_halt_req, // Async halt request
input logic mpc_debug_run_req, // Async run request
@ -317,14 +317,14 @@ module swerv_wrapper
output logic mpc_debug_run_ack, // Run ack
output logic debug_brkpt_status, // debug breakpoint
input logic i_cpu_halt_req, // Async halt req to CPU
output logic o_cpu_halt_ack, // core response to halt
output logic o_cpu_halt_status, // 1'b1 indicates core is halted
input logic i_cpu_halt_req, // Async halt req to CPU
output logic o_cpu_halt_ack, // core response to halt
output logic o_cpu_halt_status, // 1'b1 indicates core is halted
output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
input logic i_cpu_run_req, // Async restart req to CPU
output logic o_cpu_run_ack, // Core response to run req
input logic scan_mode, // To enable scan mode
input logic mbist_mode // to enable mbist
input logic i_cpu_run_req, // Async restart req to CPU
output logic o_cpu_run_ack, // Core response to run req
input logic scan_mode, // To enable scan mode
input logic mbist_mode // to enable mbist
);
`include "global.h"
@ -336,7 +336,7 @@ module swerv_wrapper
logic [DCCM_BITS-1:0] dccm_rd_addr_lo;
logic [DCCM_BITS-1:0] dccm_rd_addr_hi;
logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data;
logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
@ -396,14 +396,14 @@ module swerv_wrapper
// Instantiate the swerv core
swerv swerv (
.*
);
);
// Instantiate the mem
mem mem (
.rst_l(core_rst_l),
.*
);
.rst_l(core_rst_l),
.*
);
endmodule

10
testbench/tb_top.sv
View File

@ -310,11 +310,11 @@ end
.jtag_trst_n ( 1'b0 ), // JTAG Reset
.jtag_tdo ( jtag_tdo ), // JTAG TDO
.mpc_debug_halt_ack ( mpc_debug_halt_ack),
.mpc_debug_halt_req ( 1'b0),
.mpc_debug_run_ack ( mpc_debug_run_ack),
.mpc_debug_run_req ( 1'b1),
.mpc_reset_run_req ( 1'b1), // Start running after reset
.mpc_debug_halt_ack ( mpc_debug_halt_ack),
.mpc_debug_halt_req ( 1'b0),
.mpc_debug_run_ack ( mpc_debug_run_ack),
.mpc_debug_run_req ( 1'b1),
.mpc_reset_run_req ( 1'b1), // Start running after reset
.debug_brkpt_status (debug_brkpt_status),
.i_cpu_halt_req ( 1'b0 ), // Async halt req to CPU