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# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital # SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
This repository contains the SweRV Core<sup>TM</sup> 1.1.1 design RTL. The previous version can be found in [branch 1.0,](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) This repository contains the SweRV Core<sup>TM</sup> 1.2 design RTL. The previous version can be found in [branch 1.1.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.1)
The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M). The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
## License ## License