colin
/
abstractaccelerator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Updated release notes.

This commit is contained in:
Joseph Rahmeh 2019-08-13 12:43:09 -07:00
parent ac92841999
commit 85a510db19
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
release-notes.md
View File

@ -1,4 +1,4 @@
# SweRV RISC-V Core<sup>TM</sup> 1.1.1 from Western Digital # SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
## Release Notes ## Release Notes
1. SWERV core RISCV compatibility improvements 1. SWERV core RISCV compatibility improvements
* The ebreak and ecall instructions are no longer counted in the MINSRET * The ebreak and ecall instructions are no longer counted in the MINSRET
@ -10,6 +10,8 @@
eliminates over 90% of clock-gating enabling faster FPGA eliminates over 90% of clock-gating enabling faster FPGA
simulation. simulation.
1. Usability: Untabified all the verilog files.
# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital # SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
## Release Notes ## Release Notes
1. SWERV core RISCV compatibility improvements 1. SWERV core RISCV compatibility improvements