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Updated release notes.

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Joseph Rahmeh 2019-08-13 12:43:09 -07:00
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release-notes.md
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# SweRV RISC-V Core<sup>TM</sup> 1.1.1 from Western Digital
# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements
* The ebreak and ecall instructions are no longer counted in the MINSRET
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eliminates over 90% of clock-gating enabling faster FPGA
simulation.
1. Usability: Untabified all the verilog files.
# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements