Split from soc.mk to soc_sim.mk and soc_top.mk
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1f222dd1e3
commit
8e190efed0
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@ -39,7 +39,8 @@ verilator-build: swerv_define
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$(BUILD_DIR)/common_defines.vh \
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-I${BUILD_DIR} \
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-Wno-UNOPTFLAT \
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-F ${RV_SOC}/soc.mk \
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-F ${RV_SOC}/soc_top.mk \
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-F ${RV_SOC}/soc_sim.mk \
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$(RV_SOC)/soc_sim.sv \
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--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_sim.cpp obj_dir
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@ -42,7 +42,8 @@ verilator-build: swerv_define
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$(BUILD_DIR)/common_defines.vh \
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-I${BUILD_DIR} \
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-Wno-UNOPTFLAT \
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-F ${RV_SOC}/soc.mk \
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-F ${RV_SOC}/soc_top.mk \
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-F ${RV_SOC}/soc_sim.mk \
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$(RV_SOC)/soc_sim.sv \
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--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_sim.cpp obj_dir
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@ -0,0 +1,9 @@
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-I../design/include
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-I./
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-CFLAGS -lpthread
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-LDFLAGS -lpthread
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./dpi/common/tcp_server.c
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./dpi/jtagdpi/jtagdpi.sv
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./dpi/jtagdpi/jtagdpi.c
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@ -38,20 +38,10 @@
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../design/dmi/dmi_wrapper.v
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../design/dmi/dmi_jtag_to_core_sync.v
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../design/dmi/rvjtag_tap.sv
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-v ../design/lib/beh_lib.sv
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-v ../design/lib/mem_lib.sv
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-v ../design/lib/ahb_to_axi4.sv
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-v ../design/lib/axi4_to_ahb.sv
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../design/lib/beh_lib.sv
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../design/lib/mem_lib.sv
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../design/lib/ahb_to_axi4.sv
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../design/lib/axi4_to_ahb.sv
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./ahb_sif.sv
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./soc_top.sv
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-I../design/include
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-I./
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-CFLAGS -lpthread
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-LDFLAGS -lpthread
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./dpi/common/tcp_server.c
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./dpi/jtagdpi/jtagdpi.sv
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./dpi/jtagdpi/jtagdpi.c
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./soc_top.sv
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