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colin
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abstractaccelerator
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Verilog
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colin
8e190efed0
Split from soc.mk to soc_sim.mk and soc_top.mk
2022-02-15 08:31:00 +00:00
.vscode
Set DCCM and ICCM size to 32KB
2022-02-11 12:17:21 +00:00
Cores-SweRV
Split from soc.mk to soc_sim.mk and soc_top.mk
2022-02-15 08:31:00 +00:00
fpga
Add ram test and verilator in fpga DEMO.
2022-02-09 12:47:35 +00:00
jtag
add jtag to ESP32
2022-02-02 03:40:41 +00:00