Version 1.5
This commit is contained in:
Joseph Rahmeh
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LICENSE
206
LICENSE
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@ -1,201 +1,69 @@
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Apache License
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Version 2.0, January 2004
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http://www.apache.org/licenses/
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Apache License
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153
README.md
153
README.md
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@ -1,7 +1,6 @@
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# SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
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# EH1 SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
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This repository contains the SweRV Core<sup>TM</sup> 1.5 design RTL. The previous version can be found in [branch 1.4.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.4)
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The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
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This repository contains the SweRV EH1.5 Core<sup>TM</sup> design RTL
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## License
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@ -24,13 +23,15 @@ Files under the [tools](tools/) directory may be available under a different lic
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├── docs
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├── tools # Scripts/Makefiles
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└── testbench # (Very) simple testbench
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├── asm # Example assembly files
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├── asm # Example test files
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└── hex # Canned demo hex files
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## Dependencies
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- Verilator **(3.926 or later)** must be installed on the system
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- If adding/removing instructions, espresso must be installed. Espresso is a logic minimization tool used in *tools/coredecode*.
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- Verilator **(4.020 or later)** must be installed on the system if running with verilator
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- If adding/removing instructions, espresso must be installed (used by *tools/coredecode*)
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- RISCV tool chain (based on gcc version 7.3 or higher) must be
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installed so that it can be used to prepare RISCV binaries to run.
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## Quickstart guide
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1. Clone the repository
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@ -47,14 +48,17 @@ SweRV can be configured by running the `$RV_ROOT/configs/swerv.config` script:
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`% $RV_ROOT/configs/swerv.config -h` for detailed help options
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For example to build with a DCCM of size 64 :
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For example to build with a DCCM of size 64 Kb:
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`% $RV_ROOT/configs/swerv.config -dccm_size=64`
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This will update the **default** snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM.
|
||||
This will update the **default** snapshot in $PWD/snapshots/default/ with parameters for a 64K DCCM. To **unset** a parameter, use `-unset=PARAM` option to swerv.config.
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Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
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||||
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There are four predefined target configurations: `default`, `default_ahb`, `default_pd`, `high_perf` that can be selected via
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the `-target=name` option to swerv.config.
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||||
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||||
This script derives the following consistent set of include files :
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||||
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$RV_ROOT/configs/snapshots/default
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@ -62,75 +66,134 @@ This script derives the following consistent set of include files :
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|||
├── defines.h # #defines for C/assembly headers
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├── pd_defines.vh # `defines for physical design
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├── perl_configs.pl # Perl %configs hash for scripting
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├── pic_ctrl_verilator_unroll.sv # Unrolled verilog based on PIC size
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├── pic_map_auto.h # PIC memory map based on configure size
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└── whisper.json # JSON file for swerv-iss
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||||
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||||
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||||
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### Building a model
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1. Set the RV_ROOT environment variable to the root of the SweRV directory structure
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`RV_ROOT = /path/to/swerv`
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`export RV_ROOT`
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while in a work directory:
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||||
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||||
1. Create your configuration
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||||
1. Set the RV_ROOT environment variable to the root of the SweRV directory structure.
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||||
Example for bash shell:
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||||
`export RV_ROOT=/path/to/swerv`
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||||
Example for csh or its derivatives:
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||||
`setenv RV_ROOT /path/to/swerv`
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||||
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||||
1. Create your specific configuration
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||||
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||||
*(Skip if default is sufficient)*
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||||
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the **default** snapshot)*
|
||||
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*
|
||||
For example if `mybuild` is the name for the snapshot:
|
||||
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||||
set BUILD_PATH environment variable:
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||||
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||||
`setenv BUILD_PATH snapshots/mybuild`
|
||||
|
||||
`$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild`
|
||||
|
||||
Snapshots are placed in `$RV_ROOT/configs/snapshots/<snapshot name>/` directory
|
||||
Snapshots are placed in `$BUILD_PATH` directory
|
||||
|
||||
1. Build with **verilator**:
|
||||
|
||||
`make -f $RV_ROOT/tools/Makefile verilator [snapshot=name]`
|
||||
1. Running a simple Hello World program (verilator)
|
||||
|
||||
This will create and populate the verilator *obj_dir/* in the current work dir.
|
||||
`make -f $RV_ROOT/tools/Makefile`
|
||||
|
||||
**Other targets supported**:
|
||||
This command will build a verilator model of SweRV EH1 with AXI bus, and
|
||||
execute a short sequence of instructions that writes out "HELLO WORLD"
|
||||
to the bus.
|
||||
|
||||
vcs (Synopsys)
|
||||
irun (Cadence)
|
||||
|
||||
### Running a simple Hello World program (verilator)
|
||||
The simulation produces output on the screen like:
|
||||
|
||||
RV_ROOT = /path/to/swerv
|
||||
export RV_ROOT
|
||||
````
|
||||
VerilatorTB: Start of sim
|
||||
|
||||
make -f $RV_ROOT/tools/Makefile verilator-run
|
||||
----------------------------------
|
||||
Hello World from SweRV EH1 @WDC !!
|
||||
----------------------------------
|
||||
|
||||
This will build a verilator model of SweRV with AHB-lite bus, and execute a short sequence of instructions that writes out "HELLO
|
||||
WORLD" to the bus.
|
||||
Finished : minstret = 443, mcycle = 1372
|
||||
See "exec.log" for execution trace with register updates..
|
||||
|
||||
You can re-execute using
|
||||
TEST_PASSED
|
||||
````
|
||||
|
||||
./obj_dir/Vtb_top
|
||||
The simulation generates following files:
|
||||
|
||||
Start of sim
|
||||
`console.log` contains what the cpu writes to the console address of 0xd0580000.
|
||||
`exec.log` shows instruction trace with GPR updates.
|
||||
`trace_port.csv` contains a log of the trace port.
|
||||
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by
|
||||
gtkwave or similar waveform viewers.
|
||||
|
||||
------------------------------
|
||||
Hello World from SweRV @WDC !!
|
||||
------------------------------
|
||||
You can re-execute simulation using:
|
||||
` ./obj_dir/Vtb_top `
|
||||
or
|
||||
`make -f $RV_ROOT/tools/Makefile verilator`
|
||||
|
||||
Finished : minstret = 389, mcycle = 1658
|
||||
|
||||
End of sim
|
||||
|
||||
A vcd file `sim.vcd` is created which can be browsed by gtkwave or similar waveform viewers. `trace_port.csv` contains a log of
|
||||
the trace port. `exec.log` contains a basic execution trace showing PC, opcode and GPR writes.
|
||||
The simulation run/build command has following generic form:
|
||||
|
||||
The Makefile allows you to specify different assembly files from command line
|
||||
```
|
||||
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=<snapshot>] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>] [CONF_PARAMS=<swerv.config option>]
|
||||
|
||||
make -f $RV_ROOT/tools/Makefile verilator-run ASM_TEST=my_hellow_world.s ASM_TEST_DIR=/path/to/dir
|
||||
where:
|
||||
|
||||
<simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa
|
||||
if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
|
||||
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
|
||||
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'default_pd', 'high_perf'
|
||||
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default
|
||||
TEST_DIR - alternative to test source directory testbench/asm
|
||||
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument
|
||||
for runs on custom configurations.
|
||||
CONF_PARAMS - configuration parameter for swerv.config : ex: 'CONF_PARAMS=-unset=dccm_enable' to build with no DCCM
|
||||
```
|
||||
|
||||
Example:
|
||||
|
||||
make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
|
||||
|
||||
will simulate testbench/asm/cmark.c program with verilator on default target
|
||||
|
||||
|
||||
If you want to compile a test only, you can run:
|
||||
|
||||
make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
|
||||
|
||||
|
||||
The Makefile uses `$RV_ROOT/testbench/link.ld` file by default to build test executable.
|
||||
User can provide test specific linker file in form `<test_name>.ld` to build the test executable,
|
||||
in the same directory with the test source.
|
||||
|
||||
User also can create a test specific makefile in form `<test_name>.makefile`, contaning building instructions
|
||||
how to create `program.hex`, `data.hex` files used by simulation. The private makefile should be in the same directory
|
||||
as the test source.
|
||||
*(`program.hex` file is loaded to instruction bus memory slave and `data.hex` file is loaded to LSU bus memory slave and
|
||||
optionally to DCCM at the beginning of simulation)*.
|
||||
|
||||
Note: You may need to delete `program.hex` file from work directory, when run a new test.
|
||||
|
||||
The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
|
||||
|
||||
```
|
||||
hello_world - default test to run, prints Hello World message to screen and console.log
|
||||
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
|
||||
cmark - coremark benchmark running with code and data in external memories
|
||||
cmark_dccm - the same as above, running data and stack from DCCM (faster)
|
||||
cmark_iccm - the same as above, but with code preloaded to iccm - runs only on CPU with ICCM
|
||||
use CONF_PARAMS=-set=iccm_enable argument to `make` to build CPU with ICCM
|
||||
```
|
||||
|
||||
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
|
||||
|
||||
If you change only the assembly files, you do not need to rebuild verilator, just specify the target as `program.hex` :
|
||||
|
||||
make -f $RV_ROOT/tools/Makefile program.hex ASM_TEST=my_hello_world.s ASM_TEST_DIR=/path/to/dir
|
||||
./obj_dir/Vtb_top
|
||||
|
||||
### SweRV CoreMark Benchmarking
|
||||
We ran [CoreMark](https://www.eembc.org/coremark/) benchmark on Nexys4 board and achieved CoreMark score of **4.94**. Please see the [document](https://github.com/chipsalliance/Cores-SweRV/blob/master/docs/SweRV_CoreMark_Benchmarking.pdf) for details.
|
||||
|
||||
----
|
||||
Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS, and OmniXtend are registered trademarks or trademarks of Western Digital Corporation or its affiliates in the US and/or other countries. All other marks are the property of their respective owners.
|
||||
Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS,
|
||||
and OmniXtend are registered trademarks or trademarks of Western Digital Corporation or its affiliates in the US
|
||||
and/or other countries. All other marks are the property of their respective owners.
|
||||
|
|
|
|||
|
|
@ -8,7 +8,9 @@ Name | Description
|
|||
swerv.config | Configuration script for SweRV
|
||||
|
||||
|
||||
This script will generate a consistent st of `defines/#defines needed for the design and testbench.
|
||||
This script will generate a consistent set of `defines/#defines needed for the design and testbench.
|
||||
A perl hash (*perl_configs.pl*) and a JSON format for SweRV-iss are also generated.
|
||||
|
||||
While the defines fines may be modified by hand, it is recommended that this script be used to generate a consistent set.
|
||||
`$RV_ROOT/configs/swerv.config -h` will provide options for the script.
|
||||
|
||||
While the defines files may be modified by hand, it is recommended that this script be used to generate a consistent set.
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ my @unsets = ();
|
|||
# : multiple -set/-unset options accepted\n\n";
|
||||
#
|
||||
|
||||
$helpusage = "
|
||||
my $helpusage = "
|
||||
|
||||
Main configuration database for SWERV
|
||||
|
||||
|
|
@ -91,7 +91,7 @@ This script documents, and generates the {`#} define/include files for verilog/a
|
|||
|
||||
User options:
|
||||
|
||||
-target = { default, generic }
|
||||
-target = { default, default_ahb, default_pd, high_perf}
|
||||
use default settings for one of the targets
|
||||
|
||||
-set=var=value
|
||||
|
|
@ -246,32 +246,7 @@ my $perlfile = "$build_path/perl_configs.pl";
|
|||
|
||||
my $no_secondary_alu=0;
|
||||
|
||||
if ($target eq "generic") {
|
||||
print "$self: Using target \"generic\"\n";
|
||||
if (!defined($ret_stack_size)) { $ret_stack_size=4; }
|
||||
if (!defined($btb_size)) { $btb_size=32; }
|
||||
if (!defined($bht_size)) { $bht_size=128; }
|
||||
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
||||
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
||||
if (!defined($dccm_offset)) { $dccm_offset="0x80000"; } #1*256*1024
|
||||
if (!defined($dccm_size)) { $dccm_size=512; }
|
||||
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
||||
if (!defined($iccm_enable)) { $iccm_enable=1; }
|
||||
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
||||
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
||||
if (!defined($iccm_size)) { $iccm_size=512; }
|
||||
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
||||
if (!defined($icache_enable)) { $icache_enable=0; }
|
||||
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
||||
if (!defined($icache_size)) { $icache_size=16; }
|
||||
if (!defined($pic_2cycle)) { $pic_2cycle=0; }
|
||||
if (!defined($pic_region)) { $pic_region="0xf"; }
|
||||
if (!defined($pic_offset)) { $pic_offset="0x100000"; } # 3*256*1024
|
||||
if (!defined($pic_size)) { $pic_size=32; }
|
||||
if (!defined($pic_total_int)) { $pic_total_int=8; }
|
||||
if (!defined($dec_instbuf_depth)) { $dec_instbuf_depth=2; }
|
||||
}
|
||||
elsif ($target eq "default") {
|
||||
if ($target eq "default") {
|
||||
if (!defined($ret_stack_size)) { $ret_stack_size=4; }
|
||||
if (!defined($btb_size)) { $btb_size=32; }
|
||||
if (!defined($bht_size)) { $bht_size=128; }
|
||||
|
|
@ -296,8 +271,78 @@ elsif ($target eq "default") {
|
|||
|
||||
# default is AXI bus
|
||||
}
|
||||
else {
|
||||
die "$self: ERROR! Unsupported target \"$target\". Supported targets are: \"default,generic\"!\n";
|
||||
elsif ($target eq "default_ahb") {
|
||||
if (!defined($ret_stack_size)) { $ret_stack_size=4; }
|
||||
if (!defined($btb_size)) { $btb_size=32; }
|
||||
if (!defined($bht_size)) { $bht_size=128; }
|
||||
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
||||
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
||||
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
|
||||
if (!defined($dccm_size)) { $dccm_size=64; }
|
||||
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
||||
if (!defined($iccm_enable)) { $iccm_enable=0; }
|
||||
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
||||
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
||||
if (!defined($iccm_size)) { $iccm_size=512; }
|
||||
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
||||
if (!defined($icache_enable)) { $icache_enable=1; }
|
||||
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
||||
if (!defined($icache_size)) { $icache_size=16; }
|
||||
if (!defined($pic_2cycle)) { $pic_2cycle=0; }
|
||||
if (!defined($pic_region)) { $pic_region="0xf"; }
|
||||
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
|
||||
if (!defined($pic_size)) { $pic_size=32; }
|
||||
if (!defined($pic_total_int)) { $pic_total_int=8; }
|
||||
$ahb_lite = 1;
|
||||
|
||||
} elsif ($target eq "default_pd") {
|
||||
if (!defined($ret_stack_size)) { $ret_stack_size=4; }
|
||||
if (!defined($btb_size)) { $btb_size=32; }
|
||||
if (!defined($bht_size)) { $bht_size=128; }
|
||||
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
||||
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
||||
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
|
||||
if (!defined($dccm_size)) { $dccm_size=32; }
|
||||
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
||||
if (!defined($iccm_enable)) { $iccm_enable=0; }
|
||||
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
||||
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
||||
if (!defined($iccm_size)) { $iccm_size=512; }
|
||||
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
||||
if (!defined($icache_enable)) { $icache_enable=1; }
|
||||
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
||||
if (!defined($icache_size)) { $icache_size=16; }
|
||||
if (!defined($pic_2cycle)) { $pic_2cycle=0; }
|
||||
if (!defined($pic_region)) { $pic_region="0xf"; }
|
||||
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
|
||||
if (!defined($pic_size)) { $pic_size=32; }
|
||||
if (!defined($pic_total_int)) { $pic_total_int=8; }
|
||||
|
||||
} elsif ($target eq "high_perf") {
|
||||
if (!defined($ret_stack_size)) { $ret_stack_size=4; }
|
||||
if (!defined($btb_size)) { $btb_size=512; }
|
||||
if (!defined($bht_size)) { $bht_size=2048; }
|
||||
if (!defined($dccm_enable)) { $dccm_enable=1; }
|
||||
if (!defined($dccm_region)) { $dccm_region="0xf"; }
|
||||
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
|
||||
if (!defined($dccm_size)) { $dccm_size=64; }
|
||||
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
|
||||
if (!defined($iccm_enable)) { $iccm_enable=0; }
|
||||
if (!defined($iccm_region)) { $iccm_region="0xe"; }
|
||||
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
|
||||
if (!defined($iccm_size)) { $iccm_size=512; }
|
||||
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
|
||||
if (!defined($icache_enable)) { $icache_enable=1; }
|
||||
if (!defined($icache_ecc)) { $icache_ecc=0; }
|
||||
if (!defined($icache_size)) { $icache_size=32; }
|
||||
if (!defined($pic_2cycle)) { $pic_2cycle=0; }
|
||||
if (!defined($pic_region)) { $pic_region="0xf"; }
|
||||
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
|
||||
if (!defined($pic_size)) { $pic_size=32; }
|
||||
if (!defined($pic_total_int)) { $pic_total_int=8; }
|
||||
|
||||
} else {
|
||||
die "$self: ERROR! Unsupported target \"$target\". Supported targets are: \"default, default_ahb, default_pd, high_perf\"!\n";
|
||||
}
|
||||
|
||||
# general stuff - can't set from command line other than -set
|
||||
|
|
@ -366,7 +411,7 @@ our %csr = (#{{{
|
|||
"exists" => "true",
|
||||
},
|
||||
"mimpid" => {
|
||||
"reset" => "0x1",
|
||||
"reset" => "0x2",
|
||||
"mask" => "0x0",
|
||||
"exists" => "true",
|
||||
},
|
||||
|
|
@ -742,7 +787,7 @@ our %config = (#{{{
|
|||
"CPU_TOP" => "`RV_TOP.swerv",
|
||||
"clock_period" => "100",
|
||||
"build_ahb_lite" => "$ahb_lite", # one and only one bus build arg will ever be defined
|
||||
"build_axi4" => "",
|
||||
"build_axi4" => "1",
|
||||
"assert_on" => "",
|
||||
"datawidth" => "64", # deprecate this !! FIXME
|
||||
"ext_datawidth" => "64",
|
||||
|
|
@ -905,6 +950,12 @@ else { # default is AXI bus
|
|||
}
|
||||
|
||||
|
||||
# Over-ride MFDC reset value for AXI.
|
||||
if (exists($config{"testbench"}{"build_axi_native"}) and
|
||||
$config{"testbench"}{"build_axi_native"} ne "") {
|
||||
$config{csr}{mfdc}{reset} = "0x00070040" if exists $config{csr}{mfdc};
|
||||
}
|
||||
|
||||
# Over-ride MFDC reset value for AXI.
|
||||
if (exists($config{"testbench"}{"build_axi_native"}) and
|
||||
$config{"testbench"}{"build_axi_native"} ne "") {
|
||||
|
|
@ -1254,14 +1305,6 @@ for ($rgn = 15;$rgn >= 0; $rgn--) {
|
|||
}
|
||||
$config{memmap}{debug_sb_mem} = sprintf("0x%08x", $config{memmap}{debug_sb_mem});
|
||||
|
||||
# Boot generic from ICCM
|
||||
if ($target eq "generic") {
|
||||
$config{reset_vec} = $config{iccm}{iccm_sadr};
|
||||
$config{testbench}{generic} = 1;
|
||||
print "$self: Setting reset_vec = ICCM start address for Generic\n";
|
||||
}
|
||||
|
||||
|
||||
|
||||
# Output bit-width specifiers for these variables
|
||||
our %widths = (
|
||||
|
|
@ -1296,6 +1339,31 @@ our %widths = (
|
|||
);
|
||||
#}}}
|
||||
|
||||
|
||||
#-----------------------Reset Vector MPU check-----------------------#
|
||||
$flag_pass=0;
|
||||
if(!(hex($config{reset_vec}) >= ((hex($config{iccm}{iccm_region})<<28) + (hex($config{iccm}{iccm_offset}))) && (hex($config{reset_vec}) < ((hex($config{iccm}{iccm_region})<<28) + (hex($config{iccm}{iccm_offset})) + size($config{iccm}{iccm_size})-1))))
|
||||
{
|
||||
for(my $i=0; $i<8; $i++)
|
||||
{
|
||||
$inst_access_enable = "inst_access_enable$i";
|
||||
$inst_access_addr = "inst_access_addr$i";
|
||||
$inst_access_mask = "inst_access_mask$i";
|
||||
if(hex($config{protection}{$inst_access_enable}))
|
||||
{
|
||||
if((hex($config{reset_vec})>= hex($config{protection}{$inst_access_addr})) && (hex($config{reset_vec})< (hex($config{protection}{$inst_access_addr}) | hex($config{protection}{$inst_access_mask}))))
|
||||
{
|
||||
$flag_pass++;
|
||||
last;
|
||||
}
|
||||
}
|
||||
else {$enable_check++;}
|
||||
}
|
||||
|
||||
if($flag_pass == 0 & $enable_check < 8) { die("$helpusage\n\nFAIL: RESET_VECTOR not in any of MPU enabled instruction access windows or ICCM !!!\n\n");}
|
||||
}
|
||||
#-----------------------Reset Vector MPU check-----------------------#
|
||||
|
||||
#print Dumper(\%config);
|
||||
#print Dumper(\%width);
|
||||
|
||||
|
|
@ -1612,6 +1680,73 @@ sub collect_mem_protection {
|
|||
}
|
||||
}
|
||||
|
||||
# Collect memory protection specs (array of address pairs) in the given
|
||||
# resutls array. Tag is either "data" or "inst".
|
||||
sub collect_mem_protection {
|
||||
my ($tag, $config, $results) = @_;
|
||||
return unless exists $config{protection};
|
||||
|
||||
my $prot = $config{protection};
|
||||
|
||||
my $enable_tag = $tag . "_access_enable";
|
||||
my $addr_tag = $tag . "_access_addr";
|
||||
my $mask_tag = $tag . "_access_mask";
|
||||
|
||||
foreach my $key (keys %{$prot}) {
|
||||
next unless $key =~ /^$enable_tag(\d+)$/;
|
||||
my $ix = $1;
|
||||
|
||||
my $enable = $prot->{$key};
|
||||
if ($enable !~ /[01]$/) {
|
||||
warn("Invalid value for protection entry $key: $enable\n");
|
||||
next;
|
||||
}
|
||||
|
||||
next unless ($enable eq "1" or $enable eq "1'b1");
|
||||
|
||||
if (! exists $prot->{"$addr_tag$ix"}) {
|
||||
warn("Missing $addr_tag$ix\n");
|
||||
next;
|
||||
}
|
||||
|
||||
if (! exists $prot->{"$mask_tag$ix"}) {
|
||||
warn("Missing $mask_tag$ix\n");
|
||||
next;
|
||||
}
|
||||
|
||||
my $addr = $prot->{"$addr_tag$ix"};
|
||||
my $mask = $prot->{"$mask_tag$ix"};
|
||||
|
||||
if ($addr !~ /^0x[0-9a-fA-F]+$/) {
|
||||
warn("Invalid $addr_tag$ix: $addr\n");
|
||||
next;
|
||||
}
|
||||
|
||||
if ($mask !~ /^0x[0-9a-fA-F]+$/) {
|
||||
warn("Invalid $mask_tag$ix: $mask\n");
|
||||
next;
|
||||
}
|
||||
|
||||
if ((hex($addr) & hex($mask)) != 0) {
|
||||
warn("Protection mask bits overlap address bits in mask $mask and addr $addr\n");
|
||||
}
|
||||
|
||||
if ($mask !~ /^0x0*[137]?f*$/) {
|
||||
warn("Protection mask ($mask) must have all its one bits to the right of its zero bits\n");
|
||||
next;
|
||||
}
|
||||
|
||||
my $start = hex($addr) & ~hex($mask) & 0xffffffff;
|
||||
my $end = (hex($addr) | hex($mask)) & 0xffffffff;
|
||||
|
||||
$start = sprintf("0x%08x", $start);
|
||||
$end = sprintf("0x%08x", $end);
|
||||
|
||||
push(@{$results}, [ $start, $end ]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
sub dump_whisper_config{#{{{
|
||||
my ($config, $path) = @_;
|
||||
|
||||
|
|
|
|||
|
|
@ -110,6 +110,7 @@ module dbg (
|
|||
input logic clk,
|
||||
input logic free_clk,
|
||||
input logic rst_l,
|
||||
input logic dbg_rst_l,
|
||||
input logic clk_override,
|
||||
input logic scan_mode
|
||||
);
|
||||
|
|
@ -151,6 +152,8 @@ module dbg (
|
|||
logic dmstatus_havereset_wren;
|
||||
logic dmstatus_havereset_rst;
|
||||
logic dmstatus_resumeack;
|
||||
logic dmstatus_unavail;
|
||||
logic dmstatus_running;
|
||||
logic dmstatus_halted;
|
||||
logic dmstatus_havereset;
|
||||
|
||||
|
|
@ -240,7 +243,7 @@ module dbg (
|
|||
// end clocking section
|
||||
|
||||
// Reset logic
|
||||
assign dbg_dm_rst_l = rst_l & (dmcontrol_reg[0] | scan_mode);
|
||||
assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode);
|
||||
assign dbg_core_rst_l = ~dmcontrol_reg[1];
|
||||
|
||||
// system bus register
|
||||
|
|
@ -266,10 +269,10 @@ module dbg (
|
|||
|
||||
assign sbcs_illegal_size = sbcs_reg[19]; // Anything bigger than 64 bits is illegal
|
||||
|
||||
assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'b000)}} & 4'b0001) |
|
||||
({4{(sbcs_reg[19:17] == 3'b001)}} & 4'b0010) |
|
||||
({4{(sbcs_reg[19:17] == 3'b010)}} & 4'b0100) |
|
||||
({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000);
|
||||
assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'h0)}} & 4'b0001) |
|
||||
({4{(sbcs_reg[19:17] == 3'h1)}} & 4'b0010) |
|
||||
({4{(sbcs_reg[19:17] == 3'h2)}} & 4'b0100) |
|
||||
({4{(sbcs_reg[19:17] == 3'h3)}} & 4'b1000);
|
||||
|
||||
// sbdata
|
||||
//assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 32'h3c);
|
||||
|
|
@ -301,13 +304,14 @@ module dbg (
|
|||
assign sbdata0wr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write to sbdata0 will start write command to system bus
|
||||
|
||||
// memory mapped registers
|
||||
// dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive.
|
||||
// dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 28: ackhavereset, 1: ndmreset, 0: dmactive.
|
||||
// rest all the bits are zeroed out
|
||||
// dmactive flop is reset based on core rst_l, all other flops use dm_rst_l
|
||||
assign dmcontrol_wren = (dmi_reg_addr == 7'h10) & dmi_reg_en & dmi_reg_wr_en;
|
||||
assign dmcontrol_reg[29] = '0;
|
||||
assign dmcontrol_reg[27:2] = '0;
|
||||
rvdffs #(5) dmcontrolff (.din({dmi_reg_wdata[31:28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(rst_l), .clk(dbg_free_clk));
|
||||
rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk));
|
||||
rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
||||
// dmstatus register bits that are implemented
|
||||
|
|
@ -316,10 +320,12 @@ module dbg (
|
|||
//assign dmstatus_wren = (dmi_reg_addr == 32'h11) & dmi_reg_en;
|
||||
assign dmstatus_reg[31:20] = '0;
|
||||
assign dmstatus_reg[19:18] = {2{dmstatus_havereset}};
|
||||
assign dmstatus_reg[15:10] = '0;
|
||||
assign dmstatus_reg[15:14] = '0;
|
||||
assign dmstatus_reg[7] = '1;
|
||||
assign dmstatus_reg[6:4] = '0;
|
||||
assign dmstatus_reg[17:16] = {2{dmstatus_resumeack}};
|
||||
assign dmstatus_reg[13:12] = {2{dmstatus_unavail}};
|
||||
assign dmstatus_reg[11:10] = {2{dmstatus_running}};
|
||||
assign dmstatus_reg[9:8] = {2{dmstatus_halted}};
|
||||
assign dmstatus_reg[3:0] = 4'h2;
|
||||
|
||||
|
|
@ -329,6 +335,9 @@ module dbg (
|
|||
assign dmstatus_havereset_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[1] & dmi_reg_en & dmi_reg_wr_en;
|
||||
assign dmstatus_havereset_rst = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en;
|
||||
|
||||
assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l;
|
||||
assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);
|
||||
|
||||
rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdff #(1) dmstatus_halted_reg (.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), .dout(dmstatus_halted), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdffsc #(1) dmstatus_havereset_reg (.din(1'b1), .dout(dmstatus_havereset), .en(dmstatus_havereset_wren), .clear(dmstatus_havereset_rst), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
|
@ -401,19 +410,19 @@ module dbg (
|
|||
dbg_state_en = 1'b0;
|
||||
abstractcs_busy_wren = 1'b0;
|
||||
abstractcs_busy_din = 1'b0;
|
||||
dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31]; // single pulse output to the core
|
||||
dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31] & ~dmcontrol_reg[1]; // single pulse output to the core. Need to drive every time this register is written since core might be halted due to MPC
|
||||
dbg_resume_req = 1'b0; // single pulse output to the core
|
||||
|
||||
case (dbg_state)
|
||||
IDLE: begin
|
||||
dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core
|
||||
dbg_state_en = ((dmcontrol_reg[31] & ~dec_tlu_debug_mode) | dmstatus_reg[9] | dec_tlu_mpc_halted_only) & ~dmcontrol_reg[1]; // when the jtag writes the halt bit in the DM register, OR when the status indicates Halted
|
||||
dbg_halt_req = dmcontrol_reg[31]; // Removed debug mode qualification during MPC changes
|
||||
dbg_halt_req = dmcontrol_reg[31] & ~dmcontrol_reg[1]; // Removed debug mode qualification during MPC changes
|
||||
//dbg_halt_req = dmcontrol_reg[31] & ~dec_tlu_debug_mode; // only when jtag has written the halt_req bit in the control
|
||||
end
|
||||
HALTING : begin
|
||||
dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK
|
||||
dbg_state_en = dmstatus_reg[9]; // core indicates halted
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : HALTED; // Goto HALTED once the core sends an ACK
|
||||
dbg_state_en = dmstatus_reg[9] | dmcontrol_reg[1]; // core indicates halted
|
||||
end
|
||||
HALTED: begin
|
||||
// wait for halted to go away before send to resume. Else start of new command
|
||||
|
|
@ -426,22 +435,22 @@ module dbg (
|
|||
dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming
|
||||
end
|
||||
CMD_START: begin
|
||||
dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : CMD_WAIT; // new command sent to the core
|
||||
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]);
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (|abstractcs_reg[10:8]) ? CMD_DONE : CMD_WAIT; // new command sent to the core
|
||||
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | dmcontrol_reg[1];
|
||||
end
|
||||
CMD_WAIT: begin
|
||||
dbg_nxtstate = CMD_DONE;
|
||||
dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : CMD_DONE;
|
||||
dbg_state_en = core_dbg_cmd_done | dmcontrol_reg[1]; // go to done state for one cycle after completing current command
|
||||
end
|
||||
CMD_DONE: begin
|
||||
dbg_nxtstate = HALTED;
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : HALTED;
|
||||
dbg_state_en = 1'b1;
|
||||
abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
|
||||
abstractcs_busy_din = 1'b0;
|
||||
end
|
||||
RESUMING : begin
|
||||
dbg_nxtstate = IDLE;
|
||||
dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register
|
||||
dbg_state_en = dmstatus_reg[17] | dmcontrol_reg[1]; // resume ack has been updated in the dmstatus register
|
||||
end
|
||||
default : begin
|
||||
dbg_nxtstate = IDLE;
|
||||
|
|
@ -467,7 +476,7 @@ module dbg (
|
|||
({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);
|
||||
|
||||
|
||||
rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l & rst_l), .clk(dbg_free_clk)); // Reset for both core/dbg reset
|
||||
// Ack will use the power on reset only otherwise there won't be any ack until dmactive is 1
|
||||
// rvdff #(1) dmi_ack_reg (.din(dmi_reg_en), .dout(dmi_reg_ack), .rst_l(rst_l), .clk(free_clk));
|
||||
rvdffs #(32) dmi_rddata_reg(.din(dmi_reg_rdata_din), .dout(dmi_reg_rdata), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
|
@ -604,9 +613,9 @@ module dbg (
|
|||
assign sb_axi_wlast = '1;
|
||||
|
||||
assign sb_axi_arvalid = (sb_state == CMD_RD) & ~(sb_axi_arvalid_q & sb_axi_arready_q);
|
||||
assign sb_axi_araddr[31:0] = {sbaddress0_reg[31:3],3'b0};
|
||||
assign sb_axi_araddr[31:0] = sbaddress0_reg[31:0];
|
||||
assign sb_axi_arid[SB_BUS_TAG-1:0] = '0;
|
||||
assign sb_axi_arsize[2:0] = 3'b011;
|
||||
assign sb_axi_arsize[2:0] = sbcs_reg[19:17];
|
||||
assign sb_axi_arprot[2:0] = '0;
|
||||
assign sb_axi_arcache[3:0] = 4'b0;
|
||||
assign sb_axi_arregion[3:0] = sbaddress0_reg[31:28];
|
||||
|
|
|
|||
|
|
@ -123,6 +123,9 @@ module dec
|
|||
input br_pkt_t i1_brp,
|
||||
|
||||
input lsu_error_pkt_t lsu_error_pkt_dc3, // LSU exception/error packet
|
||||
input logic lsu_single_ecc_error_incr, // Increment the counter for Single ECC error
|
||||
|
||||
input logic lsu_load_ecc_stbuf_full_dc3, // STBUF full, ecc errors should be rfpc'd
|
||||
|
||||
input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error
|
||||
input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error
|
||||
|
|
|
|||
|
|
@ -779,6 +779,7 @@ module dec_decode_ctl
|
|||
end
|
||||
end
|
||||
|
||||
|
||||
assign cam_reset_same_dest_wb = wbd.i0v & wbd.i1v & (wbd.i0rd[4:0] == wbd.i1rd[4:0]) &
|
||||
wbd.i0load & nonblock_load_valid_wb & ~dec_tlu_i0_kill_writeb_wb & ~dec_tlu_i1_kill_writeb_wb;
|
||||
|
||||
|
|
@ -794,6 +795,7 @@ module dec_decode_ctl
|
|||
|
||||
assign nonblock_load_rd[4:0] = (e3d.i0load) ? e3d.i0rd[4:0] : e3d.i1rd[4:0]; // rd data
|
||||
|
||||
|
||||
// checks
|
||||
|
||||
`ifdef ASSERT_ON
|
||||
|
|
@ -937,6 +939,7 @@ end : cam_array
|
|||
// pmu start
|
||||
|
||||
|
||||
|
||||
assign csr_read = dec_csr_ren_d;
|
||||
assign csr_write = dec_csr_wen_unq_d;
|
||||
|
||||
|
|
@ -1339,7 +1342,6 @@ end : cam_array
|
|||
|
||||
assign i1_block_d = leak1_i1_stall |
|
||||
(i0_jal) | // no i1 after a jal, will flush
|
||||
( (i0_br_error_all | (|dec_i0_trigger_match_d[3:0]) | ((i0_dp.condbr | i0_dp.jal) & i0_secondary_d)) & i1_dp.load ) | // if branch or branch error then don't allow i1 load
|
||||
i0_presync | i0_postsync |
|
||||
i1_dp.presync | i1_dp.postsync |
|
||||
i1_icaf_d | // instruction access fault is i0 only
|
||||
|
|
@ -1934,6 +1936,7 @@ end : cam_array
|
|||
assign dec_tlu_i1_valid_e4 = e4d.i1valid & ~flush_lower_wb;
|
||||
|
||||
|
||||
|
||||
assign dt.legal = i0_legal_decode_d ;
|
||||
assign dt.icaf = i0_icaf_d & i0_legal_decode_d; // dbecc is icaf exception
|
||||
assign dt.icaf_f1 = dec_i0_icaf_f1_d & i0_legal_decode_d; // this includes icaf and dbecc
|
||||
|
|
@ -1988,6 +1991,7 @@ end : cam_array
|
|||
rvdffe #( $bits(trap_pkt_t) ) trap_e4ff (.*, .en(i0_e4_ctl_en), .din(e3t_in), .dout(e4t));
|
||||
|
||||
|
||||
|
||||
assign freeze_e3 = freeze & ~freeze_before;
|
||||
|
||||
rvdff #(1) freeze_before_ff (.*, .clk(active_clk), .din(freeze), .dout(freeze_before));
|
||||
|
|
@ -2025,6 +2029,8 @@ end : cam_array
|
|||
|
||||
// end tlu stuff
|
||||
|
||||
|
||||
|
||||
assign i0_dc.mul = i0_dp.mul & i0_legal_decode_d;
|
||||
assign i0_dc.load = i0_dp.load & i0_legal_decode_d;
|
||||
assign i0_dc.sec = i0_dp.alu & i0_secondary_d & i0_legal_decode_d;
|
||||
|
|
@ -2179,6 +2185,7 @@ end : cam_array
|
|||
assign dec_i1_sec_decode_e3 = e3d.i1secondary & ~i0_flush_final_e3 & ~flush_lower_wb & ~freeze;
|
||||
|
||||
|
||||
|
||||
rvdffe #( $bits(dest_pkt_t) ) e4ff (.*, .en(i0_e4_ctl_en), .din(e3d_in), .dout(e4d));
|
||||
|
||||
always_comb begin
|
||||
|
|
@ -2281,6 +2288,7 @@ end : cam_array
|
|||
rvdffe #(12) e2brpcff (.*, .en(i0_e2_data_en), .din(last_br_immed_e1[12:1]), .dout(last_br_immed_e2[12:1]));
|
||||
|
||||
|
||||
|
||||
// trace stuff
|
||||
|
||||
rvdffe #(32) divinstff (.*, .en(i0_div_decode_d), .din(i0_inst_d[31:0]), .dout(div_inst[31:0]));
|
||||
|
|
|
|||
|
|
@ -74,6 +74,9 @@ module dec_tlu_ctl
|
|||
input logic iccm_dma_sb_error, // I side dma single bit error
|
||||
|
||||
input lsu_error_pkt_t lsu_error_pkt_dc3, // lsu precise exception/error packet
|
||||
input logic lsu_single_ecc_error_incr, // Increment the counter for Single ECC error
|
||||
|
||||
input logic lsu_load_ecc_stbuf_full_dc3, // STBUF full, ecc errors should be rfpc'd
|
||||
|
||||
input logic dec_pause_state, // Pause counter not zero
|
||||
input logic lsu_imprecise_error_store_any, // store bus error
|
||||
|
|
@ -336,11 +339,12 @@ module dec_tlu_ctl
|
|||
logic [1:0] dec_tlu_br0_bank_e4, dec_tlu_br1_bank_e4;
|
||||
logic rfpc_i0_e4, rfpc_i1_e4;
|
||||
logic lsu_i0_rfnpc_dc4, lsu_i1_rfnpc_dc4;
|
||||
logic lsu_i0_rfpc_dc4, lsu_i1_rfpc_dc4;
|
||||
logic dec_tlu_br0_error_e4, dec_tlu_br0_start_error_e4, dec_tlu_br0_v_e4;
|
||||
logic dec_tlu_br1_error_e4, dec_tlu_br1_start_error_e4, dec_tlu_br1_v_e4;
|
||||
logic lsu_i0_exc_dc4, lsu_i1_exc_dc4, lsu_i0_exc_dc4_raw, lsu_i1_exc_dc4_raw, lsu_exc_ma_dc4, lsu_exc_acc_dc4, lsu_exc_st_dc4,
|
||||
lsu_exc_valid_e4, lsu_exc_valid_e4_raw, lsu_exc_valid_wb, lsu_i0_exc_wb,
|
||||
block_interrupts, lsu_block_interrupts_dc3, lsu_block_interrupts_e4;
|
||||
block_interrupts, lsu_block_interrupts_dc3, lsu_block_interrupts_e4, lsu_load_ecc_stbuf_full_dc4;
|
||||
logic tlu_i0_commit_cmt, tlu_i1_commit_cmt;
|
||||
logic i0_trigger_eval_e4, i1_trigger_eval_e4, lsu_freeze_e4, lsu_freeze_pulse_e3, lsu_freeze_pulse_e4;
|
||||
|
||||
|
|
@ -459,7 +463,7 @@ module dec_tlu_ctl
|
|||
assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f;
|
||||
|
||||
// states
|
||||
assign mpc_halt_state_ns = (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse) & ~mpc_debug_run_req_sync;
|
||||
assign mpc_halt_state_ns = (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync;
|
||||
assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);
|
||||
|
||||
// note, MPC halt can allow the jtag debugger to just start sending commands. When that happens, set the interal debugger halt state to prevent
|
||||
|
|
@ -722,10 +726,10 @@ module dec_tlu_ctl
|
|||
// LSU exceptions (LSU responsible for prioritizing simultaneous cases)
|
||||
lsu_error_pkt_t lsu_error_pkt_dc4;
|
||||
|
||||
rvdff #( $bits(lsu_error_pkt_t) ) lsu_error_dc4ff (.*, .clk(lsu_e3_e4_clk), .din(lsu_error_pkt_dc3), .dout(lsu_error_pkt_dc4));
|
||||
rvdff #( $bits(lsu_error_pkt_t)+1 ) lsu_error_dc4ff (.*, .clk(lsu_e3_e4_clk), .din({lsu_error_pkt_dc3, lsu_load_ecc_stbuf_full_dc3}), .dout({lsu_error_pkt_dc4, lsu_load_ecc_stbuf_full_dc4}));
|
||||
|
||||
logic lsu_single_ecc_error_wb_ns;
|
||||
assign lsu_single_ecc_error_wb_ns = lsu_error_pkt_dc4.single_ecc_error;// & ((~lsu_error_pkt_dc4.inst_pipe & tlu_i0_commit_cmt) | (lsu_error_pkt_dc4.inst_pipe & tlu_i1_commit_cmt));
|
||||
assign lsu_single_ecc_error_wb_ns = lsu_single_ecc_error_incr;
|
||||
rvdff #(2) lsu_dccm_errorff (.*, .clk(free_clk), .din({mdseac_locked_ns, lsu_single_ecc_error_wb_ns}), .dout({mdseac_locked_f, lsu_single_ecc_error_wb}));
|
||||
|
||||
logic [31:0] lsu_error_pkt_addr_dc4, lsu_error_pkt_addr_wb;
|
||||
|
|
@ -746,12 +750,18 @@ module dec_tlu_ctl
|
|||
assign lsu_exc_acc_dc4 = (lsu_i0_exc_dc4 | lsu_i1_exc_dc4) & lsu_error_pkt_dc4.exc_type;
|
||||
assign lsu_exc_st_dc4 = (lsu_i0_exc_dc4 | lsu_i1_exc_dc4) & lsu_error_pkt_dc4.inst_type;
|
||||
|
||||
// If the stbuf is not full, then
|
||||
// Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR.
|
||||
// LSU turns the load into a store and patches the data in the DCCM
|
||||
assign lsu_i0_rfnpc_dc4 = dec_tlu_i0_valid_e4 & ~lsu_error_pkt_dc4.inst_pipe & ~lsu_error_pkt_dc4.inst_type &
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & ~i0_trigger_hit_e4;
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & ~i0_trigger_hit_e4 & ~lsu_load_ecc_stbuf_full_dc4;
|
||||
assign lsu_i1_rfnpc_dc4 = dec_tlu_i1_valid_e4 & lsu_error_pkt_dc4.inst_pipe & ~lsu_error_pkt_dc4.inst_type &
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & ~i0_trigger_hit_e4 & ~i1_trigger_hit_e4;
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & ~i0_trigger_hit_e4 & ~i1_trigger_hit_e4 & ~lsu_load_ecc_stbuf_full_dc4;
|
||||
// otherwise, they are rfpcs
|
||||
assign lsu_i0_rfpc_dc4 = dec_tlu_i0_valid_e4 & ~lsu_error_pkt_dc4.inst_pipe & ~lsu_error_pkt_dc4.inst_type &
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & lsu_load_ecc_stbuf_full_dc4;
|
||||
assign lsu_i1_rfpc_dc4 = dec_tlu_i1_valid_e4 & lsu_error_pkt_dc4.inst_pipe & ~lsu_error_pkt_dc4.inst_type &
|
||||
lsu_error_pkt_dc4.single_ecc_error & ~lsu_error_pkt_dc4.dma_valid & lsu_load_ecc_stbuf_full_dc4;
|
||||
|
||||
// Branch prediction updating
|
||||
assign dec_tlu_br0_addr_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = exu_i0_br_index_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO];
|
||||
|
|
@ -784,10 +794,10 @@ module dec_tlu_ctl
|
|||
|
||||
// refetch PC, microarch flush
|
||||
// ic errors only in pipe0
|
||||
assign rfpc_i0_e4 = dec_tlu_i0_valid_e4 & ~tlu_flush_lower_wb & (exu_i0_br_error_e4 | exu_i0_br_start_error_e4 | ic_perr_e4 | iccm_sbecc_e4) & ~i0_trigger_hit_e4;
|
||||
assign rfpc_i0_e4 = dec_tlu_i0_valid_e4 & ~tlu_flush_lower_wb & (exu_i0_br_error_e4 | exu_i0_br_start_error_e4 | ic_perr_e4 | iccm_sbecc_e4 | lsu_i0_rfpc_dc4) & ~i0_trigger_hit_e4;
|
||||
assign rfpc_i1_e4 = dec_tlu_i1_valid_e4 & ~tlu_flush_lower_wb & ~i0_exception_valid_e4 & ~exu_i0_br_mp_e4 & ~lsu_i0_exc_dc4 & ~lsu_i0_rfnpc_dc4 &
|
||||
~(exu_i0_br_error_e4 | exu_i0_br_start_error_e4 | ic_perr_e4 | iccm_sbecc_e4) &
|
||||
(exu_i1_br_error_e4 | exu_i1_br_start_error_e4) &
|
||||
~(exu_i0_br_error_e4 | exu_i0_br_start_error_e4 | ic_perr_e4 | iccm_sbecc_e4 | lsu_i0_rfpc_dc4) &
|
||||
(exu_i1_br_error_e4 | exu_i1_br_start_error_e4 | lsu_i1_rfpc_dc4) &
|
||||
~trigger_hit_e4;
|
||||
|
||||
// go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush
|
||||
|
|
@ -1050,7 +1060,8 @@ module dec_tlu_ctl
|
|||
assign dec_csr_wen_wb_mod = dec_csr_wen_wb & ~trigger_hit_wb;
|
||||
assign wr_mstatus_wb = dec_csr_wen_wb_mod & (dec_csr_wraddr_wb[11:0] == `MSTATUS);
|
||||
|
||||
assign mstatus_ns[1:0] = ( ({2{exc_or_int_valid_wb}} & {mstatus[`MSTATUS_MIE], 1'b0}) |
|
||||
assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_wb & exc_or_int_valid_wb}} & {mstatus[`MSTATUS_MIE], 1'b0}) |
|
||||
({2{ wr_mstatus_wb & exc_or_int_valid_wb}} & {dec_csr_wrdata_wb[3], 1'b0}) |
|
||||
({2{mret_wb & ~exc_or_int_valid_wb}} & {1'b1, mstatus[1]}) |
|
||||
({2{wr_mstatus_wb & ~exc_or_int_valid_wb}} & {dec_csr_wrdata_wb[7], dec_csr_wrdata_wb[3]}) |
|
||||
({2{~wr_mstatus_wb & ~exc_or_int_valid_wb & ~mret_wb}} & mstatus[1:0]) );
|
||||
|
|
@ -1148,10 +1159,10 @@ module dec_tlu_ctl
|
|||
|
||||
assign {minstretl_cout, minstretl_inc[31:0]} = minstretl[31:0] + {31'b0,i0_valid_no_ebreak_ecall_wb} + {31'b0,i1_valid_wb};
|
||||
|
||||
assign minstret_enable = i0_valid_no_ebreak_ecall_wb | i1_valid_wb | wr_minstretl_wb;
|
||||
assign minstret_enable = i0_valid_no_ebreak_ecall_wb | i1_valid_wb;
|
||||
|
||||
assign minstretl_ns[31:0] = wr_minstretl_wb ? dec_csr_wrdata_wb[31:0] : minstretl_inc[31:0];
|
||||
rvdffe #(32) minstretl_ff (.*, .en(minstret_enable), .din(minstretl_ns[31:0]), .dout(minstretl[31:0]));
|
||||
rvdffe #(32) minstretl_ff (.*, .en(minstret_enable | wr_minstretl_wb), .din(minstretl_ns[31:0]), .dout(minstretl[31:0]));
|
||||
logic minstret_enable_f;
|
||||
rvdff #(2) minstretf_cout_ff (.*, .clk(free_clk), .din({minstret_enable, minstretl_cout & ~wr_minstreth_wb}), .dout({minstret_enable_f, minstretl_cout_f}));
|
||||
|
||||
|
|
@ -1405,7 +1416,7 @@ module dec_tlu_ctl
|
|||
`define MPMC 12'h7c6
|
||||
logic wr_mpmc_wb;
|
||||
assign wr_mpmc_wb = dec_csr_wrdata_wb[0] & dec_csr_wen_wb_mod & (dec_csr_wraddr_wb[11:0] == `MPMC);
|
||||
assign fw_halt_req = wr_mpmc_wb & ~internal_dbg_halt_mode_f;
|
||||
assign fw_halt_req = wr_mpmc_wb & ~internal_dbg_halt_mode_f & ~interrupt_valid_wb;
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// MICECT (I-Cache error counter/threshold)
|
||||
|
|
@ -2484,7 +2495,7 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
|
|||
assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) |
|
||||
({32{csr_mvendorid}} & 32'h00000045) |
|
||||
({32{csr_marchid}} & 32'h0000000b) |
|
||||
({32{csr_mimpid}} & 32'h1) |
|
||||
({32{csr_mimpid}} & 32'h2) |
|
||||
({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) |
|
||||
({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |
|
||||
({32{csr_mip}} & {1'b0, mip[3], 18'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |
|
||||
|
|
|
|||
|
|
@ -48,8 +48,8 @@ module dmi_jtag_to_core_sync (
|
|||
// synchronizers
|
||||
always @ ( posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
rden <= 3'b0;
|
||||
wren <= 3'b0;
|
||||
rden <= '0;
|
||||
wren <= '0;
|
||||
end
|
||||
else begin
|
||||
rden <= {rden[1:0], rd_en};
|
||||
|
|
|
|||
|
|
@ -390,15 +390,21 @@ module ifu_mem_ctl
|
|||
logic iccm_rd_ecc_single_err_ff ;
|
||||
logic perr_state_en;
|
||||
logic [7:0] fetch_mask, ic_fetch_mem_val, bp_mask, ic_bp_mem_mask, ic_fetch_val_mem_f2;
|
||||
logic dma_iccm_rd_req_f1;
|
||||
logic dma_iccm_rd_req_f2;
|
||||
logic [3:0] iccm_single_ecc_error;
|
||||
|
||||
assign iccm_dma_sb_error = iccm_rd_ecc_single_err & ic_dma_active;
|
||||
assign dma_iccm_rd_req_f1 = (dma_iccm_req & ~dma_mem_write) ;
|
||||
rvdff #(1) dma_iccm_req_ff (.*, .clk(free_clk), .din (dma_iccm_rd_req_f1), .dout(dma_iccm_rd_req_f2));
|
||||
|
||||
assign iccm_dma_sb_error = (|iccm_single_ecc_error ) & dma_iccm_rd_req_f2;
|
||||
|
||||
|
||||
typedef enum logic [2:0] {ERR_IDLE=3'b000, PERR_WFF=3'b001 , ECC_WFF=3'b010 , ECC_CORR=3'b011, DMA_SB_ERR=3'b100} perr_state_t;
|
||||
perr_state_t perr_state, perr_nxtstate;
|
||||
|
||||
|
||||
assign ic_dma_active = iccm_correct_ecc | (perr_state == DMA_SB_ERR);
|
||||
assign ic_dma_active = iccm_correct_ecc | (perr_state == DMA_SB_ERR) | (dec_tlu_flush_err_wb & (perr_state == ECC_WFF));
|
||||
//////////////////////////////////// Create Miss State Machine ///////////////////////
|
||||
// Create Miss State Machine //
|
||||
// Create Miss State Machine //
|
||||
|
|
@ -474,7 +480,7 @@ module ifu_mem_ctl
|
|||
assign ic_act_hit_f2 = (|ic_rd_hit[3:0]) & fetch_req_icache_f2 & ~reset_all_tags & (~miss_pending | (miss_state==HIT_U_MISS)) & ~sel_mb_addr_ff;
|
||||
assign ic_act_miss_f2 = (~(|ic_rd_hit[3:0]) | reset_all_tags) & fetch_req_icache_f2 & ~miss_pending & ~ifc_region_acc_fault_f2;
|
||||
assign ic_miss_under_miss_f2 = (~(|ic_rd_hit[3:0]) | reset_all_tags) & fetch_req_icache_f2 & (miss_state == HIT_U_MISS) ;
|
||||
assign ic_hit_f2 = ic_act_hit_f2 | ic_byp_hit_f2 | ic_iccm_hit_f2 | (ifc_region_acc_fault_f2 & ifc_fetch_req_f2);
|
||||
assign ic_hit_f2 = ic_act_hit_f2 | ic_byp_hit_f2 | ic_iccm_hit_f2 | (ifc_region_acc_fault_f2 & ifc_fetch_req_f2 & ~((miss_state == CRIT_BYP_OK) | (miss_state == SCND_MISS)));
|
||||
|
||||
assign uncacheable_miss_in = sel_hold_imb ? uncacheable_miss_ff : ifc_fetch_uncacheable_f1 ;
|
||||
assign imb_in[31:1] = sel_hold_imb ? imb_ff[31:1] : {fetch_addr_f1[31:1]} ;
|
||||
|
|
@ -866,7 +872,6 @@ logic ifu_icache_sb_error_val_ff ;
|
|||
|
||||
logic [3:0] [31:0] iccm_corrected_data;
|
||||
logic [3:0] [06:0] iccm_corrected_ecc;
|
||||
logic [3:0] iccm_single_ecc_error;
|
||||
logic [3:0] iccm_double_ecc_error;
|
||||
logic [3:0] iccm_ecc_word_enable;
|
||||
|
||||
|
|
@ -931,6 +936,8 @@ assign iccm_rd_ecc_single_err_ff = 1'b0 ;
|
|||
assign iccm_ecc_corr_index_ff[ICCM_BITS-1:2] = '0;
|
||||
assign iccm_ecc_corr_data_ff[38:0] = '0;
|
||||
assign iccm_ecc_write_status = '0;
|
||||
assign iccm_single_ecc_error = '0;
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
|
|
@ -1028,7 +1035,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
|
|||
// assign ifu_axi_arvalid = ifc_axi_ic_req_ff2 & ~axi_cmd_rsp_pend;
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
assign ifu_axi_arvalid = ifc_axi_ic_req_ff2 ;
|
||||
assign ifu_axi_arid[IFU_BUS_TAG-1:0] = IFU_BUS_TAG'(axi_new_rd_addr_count[2:0]);
|
||||
assign ifu_axi_arid[IFU_BUS_TAG-1:0] = IFU_BUS_TAG'(axi_rd_addr_count[2:0]);
|
||||
assign ifu_axi_araddr[31:0] = {ifu_ic_req_addr_f2[31:3],3'b0} ;
|
||||
assign ifu_axi_rready = 1'b1;
|
||||
assign ifu_axi_arsize[2:0] = 3'b011;
|
||||
|
|
@ -1052,7 +1059,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
|
|||
|
||||
assign ifu_axi_arready_ff = ifu_axi_arready_unq_ff & axi_ifu_bus_clk_en_ff ;
|
||||
assign ifu_axi_rvalid_ff = ifu_axi_rvalid_unq_ff & axi_ifu_bus_clk_en_ff ;
|
||||
assign axi_cmd_sent = ifu_axi_arvalid_ff & ifu_axi_arready_ff & miss_pending;
|
||||
assign axi_cmd_sent = ifu_axi_arvalid & ifu_axi_arready & miss_pending & axi_ifu_bus_clk_en;
|
||||
assign axi_inc_data_beat_cnt = (axi_ifu_wr_en_new & ~axi_last_data_beat) ;
|
||||
assign axi_reset_data_beat_cnt = ic_act_miss_f2 | (axi_ifu_wr_en_new & axi_last_data_beat) ;
|
||||
assign axi_hold_data_beat_cnt = ~axi_inc_data_beat_cnt & ~axi_reset_data_beat_cnt ;
|
||||
|
|
@ -1070,7 +1077,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
|
|||
|
||||
assign axi_new_rd_addr_count[2:0] = ~miss_pending ? {imb_ff[5:4],1'b0} : axi_inc_rd_addr_cnt ? (axi_rd_addr_count[2:0] + 3'b001) : axi_rd_addr_count[2:0];
|
||||
|
||||
rvdffs #(3) axi_rd_addr_ff (.*, .en(~axi_hold_rd_addr_cnt), .clk(free_clk), .din ({axi_new_rd_addr_count[2:0]}), .dout({axi_rd_addr_count[2:0]}));
|
||||
rvdffs #(3) axi_rd_addr_ff (.*, .en(1'b1), .clk(axiclk_reset), .din ({axi_new_rd_addr_count[2:0]}), .dout({axi_rd_addr_count[2:0]}));
|
||||
|
||||
// command beat Count
|
||||
assign axi_inc_cmd_beat_cnt = ifu_axi_arvalid & ifu_axi_arready & miss_pending;
|
||||
|
|
@ -1090,7 +1097,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
|
|||
rvdff #(3) axi_cmd_beat_ff (.*, .clk(axiclk_reset), .din ({axi_new_cmd_beat_count[2:0]}),
|
||||
.dout({axi_cmd_beat_count[2:0]}));
|
||||
|
||||
assign req_addr_count[2:0] = axi_new_rd_addr_count[2:0] ;
|
||||
assign req_addr_count[2:0] = axi_rd_addr_count[2:0] ;
|
||||
|
||||
|
||||
|
||||
|
|
@ -1148,7 +1155,7 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
|
|||
|
||||
// assign ic_dma_active_in = ifc_dma_access_q_ok & dma_iccm_req ;
|
||||
assign iccm_wren = (ifc_dma_access_q_ok & dma_iccm_req & dma_mem_write) | iccm_correct_ecc;
|
||||
assign iccm_rden = (ifc_dma_access_q_ok & dma_iccm_req & ~dma_mem_write) | ifc_iccm_access_f1;
|
||||
assign iccm_rden = (ifc_dma_access_q_ok & dma_iccm_req & ~dma_mem_write) | (ifc_iccm_access_f1 & ifc_fetch_req_f1);
|
||||
assign iccm_dma_rden = (ifc_dma_access_q_ok & dma_iccm_req & ~dma_mem_write) ;
|
||||
assign iccm_wr_size[2:0] = {3{dma_iccm_req & dma_mem_write}} & dma_mem_sz[2:0] ;
|
||||
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ module rvoclkhdr
|
|||
`ifdef RV_FPGA_OPTIMIZE
|
||||
assign l1clk = clk;
|
||||
`else
|
||||
`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
|
||||
`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
@ -143,6 +143,7 @@ module rvdffe #( parameter WIDTH=1 )
|
|||
|
||||
logic l1clk;
|
||||
|
||||
|
||||
`ifndef PHYSICAL
|
||||
if (WIDTH >= 8) begin: genblock
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -56,10 +56,12 @@ module lsu
|
|||
input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
|
||||
|
||||
output logic [31:0] lsu_result_dc3, // lsu load data
|
||||
output logic lsu_single_ecc_error_incr, // Increment the counter for Single ECC error
|
||||
output logic [31:0] lsu_result_corr_dc4, // This is the ECC corrected data going to RF
|
||||
output logic lsu_freeze_dc3, // lsu freeze due to load to external
|
||||
output logic lsu_load_stall_any, // This is for blocking loads in the decode
|
||||
output logic lsu_store_stall_any, // This is for blocking stores in the decode
|
||||
output logic lsu_load_ecc_stbuf_full_dc3, // Load with ecc error can't allocate to stbuf
|
||||
output logic lsu_idle_any, // lsu buffers are empty and no instruction in the pipeline
|
||||
output logic lsu_halt_idle_any, // This is used to enter halt mode. Exclude DMA
|
||||
|
||||
|
|
|
|||
|
|
@ -158,7 +158,8 @@ module lsu_addrcheck
|
|||
if (DCCM_REGION == PIC_REGION) begin
|
||||
assign access_fault_dc1 = ((start_addr_in_dccm_region_dc1 & ~(start_addr_in_dccm_dc1 | start_addr_in_pic_dc1)) |
|
||||
(end_addr_in_dccm_region_dc1 & ~(end_addr_in_dccm_dc1 | end_addr_in_pic_dc1)) |
|
||||
((start_addr_dc1[27:18] != end_addr_dc1[27:18]) & start_addr_in_dccm_dc1) |
|
||||
(start_addr_in_dccm_dc1 & end_addr_in_pic_dc1) |
|
||||
(start_addr_in_pic_dc1 & end_addr_in_dccm_dc1) |
|
||||
((addr_in_pic_dc1 & ((start_addr_dc1[1:0] != 2'b0) | ~lsu_pkt_dc1.word))) |
|
||||
(~start_addr_in_dccm_region_dc1 & ~non_dccm_access_ok)) & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma;
|
||||
end else begin
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ module lsu_dccm_ctl
|
|||
|
||||
assign dccm_dma_rvalid = lsu_pkt_dc3.valid & lsu_pkt_dc3.load & lsu_pkt_dc3.dma;
|
||||
assign dccm_dma_ecc_error = lsu_double_ecc_error_dc3;
|
||||
assign dccm_dma_rdata[63:0] = lsu_rdata_corr_dc3[63:0];
|
||||
assign dccm_dma_rdata[63:0] = lsu_pkt_dc3.dword ? lsu_rdata_corr_dc3[63:0] : {2{lsu_rdata_corr_dc3[31:0]}}; // Need to replicate the data for non-dw access since ecc correction is done only in lower word
|
||||
|
||||
|
||||
assign {lsu_ld_data_dc3_nc[63:32], lsu_ld_data_dc3[31:0]} = lsu_rdata_dc3[63:0] >> 8*lsu_addr_dc3[1:0];
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@ module lsu_lsc_ctl
|
|||
input logic ld_bus_error_dc3,
|
||||
input logic [31:0] ld_bus_error_addr_dc3,
|
||||
input logic lsu_single_ecc_error_dc3,
|
||||
input logic lsu_single_ecc_error_dc5,
|
||||
input logic lsu_double_ecc_error_dc3,
|
||||
input logic lsu_freeze_dc3,
|
||||
|
||||
|
|
@ -102,6 +103,7 @@ module lsu_lsc_ctl
|
|||
input logic [31:0] dec_tlu_mrac_ff,
|
||||
output logic lsu_exc_dc2,
|
||||
output lsu_error_pkt_t lsu_error_pkt_dc3,
|
||||
output logic lsu_single_ecc_error_incr, // Increment the counter for Single ECC error
|
||||
output logic lsu_freeze_external_ints_dc3,
|
||||
output logic is_sideeffects_dc2,
|
||||
output logic is_sideeffects_dc3,
|
||||
|
|
@ -199,9 +201,12 @@ module lsu_lsc_ctl
|
|||
assign lsu_exc_dc2 = access_fault_dc2 | misaligned_fault_dc2;
|
||||
assign lsu_freeze_external_ints_dc3 = lsu_freeze_dc3 & is_sideeffects_dc3;
|
||||
|
||||
// Increment the single bit ecc counter
|
||||
assign lsu_single_ecc_error_incr = lsu_single_ecc_error_dc5 & (lsu_commit_dc5 | lsu_pkt_dc5.dma);
|
||||
|
||||
// Generate exception packet
|
||||
assign lsu_error_pkt_dc3.exc_valid = (access_fault_dc3 | misaligned_fault_dc3 | ld_bus_error_dc3 | lsu_double_ecc_error_dc3) & lsu_pkt_dc3.valid & ~lsu_pkt_dc3.dma & ~flush_dc3;
|
||||
assign lsu_error_pkt_dc3.single_ecc_error = lsu_single_ecc_error_dc3;
|
||||
assign lsu_error_pkt_dc3.single_ecc_error = lsu_single_ecc_error_dc3 & ~(access_fault_dc3 | misaligned_fault_dc3 | lsu_double_ecc_error_dc3);
|
||||
assign lsu_error_pkt_dc3.inst_type = lsu_pkt_dc3.store;
|
||||
assign lsu_error_pkt_dc3.dma_valid = lsu_pkt_dc3.dma;
|
||||
assign lsu_error_pkt_dc3.inst_pipe = ~lsu_i0_valid_dc3;
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@ module lsu_stbuf
|
|||
output logic lsu_stbuf_full_any, // stbuf is full
|
||||
output logic lsu_stbuf_empty_any, // stbuf is empty
|
||||
output logic lsu_stbuf_nodma_empty_any, // stbuf is empty except dma
|
||||
output logic lsu_load_ecc_stbuf_full_dc3, // Load with ecc error can't allocate to stbuf
|
||||
|
||||
input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc1, // lsu address
|
||||
input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc2,
|
||||
|
|
@ -205,8 +206,8 @@ module lsu_stbuf
|
|||
assign stbuf_data_en[i] = stbuf_wr_en[i];
|
||||
assign stbuf_drain_or_flush_en[i] = ldst_stbuf_reqvld_dc5 & ~lsu_pkt_dc5.dma & ((i == WrPtr_dc5[DEPTH_LOG2-1:0]) |
|
||||
(i == WrPtrPlus1_dc5[DEPTH_LOG2-1:0] & dual_stbuf_write_dc5));
|
||||
assign stbuf_drain_en[i] = (stbuf_drain_or_flush_en[i] & (lsu_commit_dc5 | stbuf_load_repair_dc5)) | (stbuf_wr_en[i] & lsu_pkt_dc3.dma);
|
||||
assign stbuf_flush_en[i] = stbuf_drain_or_flush_en[i] & ~(lsu_commit_dc5 | stbuf_load_repair_dc5);
|
||||
assign stbuf_drain_en[i] = (stbuf_drain_or_flush_en[i] & lsu_commit_dc5) | (stbuf_wr_en[i] & lsu_pkt_dc3.dma);
|
||||
assign stbuf_flush_en[i] = stbuf_drain_or_flush_en[i] & ~lsu_commit_dc5;
|
||||
assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2-1:0]);
|
||||
|
||||
// Mux select for start/end address
|
||||
|
|
@ -274,6 +275,7 @@ module lsu_stbuf
|
|||
assign lsu_stbuf_full_any = (stbuf_specvld_any[3:0] > (DEPTH - 2));
|
||||
assign lsu_stbuf_empty_any = (stbuf_numvld_any[3:0] == 4'b0);
|
||||
assign lsu_stbuf_nodma_empty_any = ~(|(stbuf_data_vld[DEPTH-1:0] & ~stbuf_dma[DEPTH-1:0]));
|
||||
assign lsu_load_ecc_stbuf_full_dc3 = load_stbuf_reqvld_dc3 & ~ldst_stbuf_reqvld_dc3;
|
||||
|
||||
assign stbuf_oneavl_any = (stbuf_numvld_any[3:0] < DEPTH);
|
||||
assign stbuf_twoavl_any = (stbuf_numvld_any[3:0] < (DEPTH - 1));
|
||||
|
|
@ -396,6 +398,12 @@ module lsu_stbuf
|
|||
assert_drainorflushvld_notvld: assert #0 (~(|((stbuf_drain_vld[DEPTH-1:0] | stbuf_flush_vld[DEPTH-1:0]) & ~stbuf_data_vld[DEPTH-1:0])));
|
||||
assert_drainAndflushvld: assert #0 (~(|(stbuf_drain_vld[DEPTH-1:0] & stbuf_flush_vld[DEPTH-1:0])));
|
||||
assert_stbufempty: assert #0 (~lsu_stbuf_empty_any | lsu_stbuf_nodma_empty_any);
|
||||
|
||||
property ldecc_stbuffull_commit;
|
||||
@(posedge clk) disable iff(~rst_l) (load_stbuf_reqvld_dc3 & lsu_load_ecc_stbuf_full_dc3) |-> ##2 (lsu_commit_dc5 == 1'b0);
|
||||
endproperty
|
||||
assert_ldecc_stbuffull_commit: assert property (ldecc_stbuffull_commit) else
|
||||
$display("load with ecc error committed with store buffer full");
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ rvsyncss #(TOTAL_INT-1) sync_inst
|
|||
|
||||
assign extintsrc_req_sync[0] = extintsrc_req[0];
|
||||
|
||||
genvar i ;
|
||||
genvar i, l, m , j, k;
|
||||
for (i=0; i<TOTAL_INT ; i++) begin : SETREG
|
||||
|
||||
if (i > 0 ) begin : NON_ZERO_INT
|
||||
|
|
@ -256,6 +256,50 @@ end
|
|||
assign levelx_intpend_w_prior_en[NUM_LEVELS/2][(TOTAL_INT/2**(NUM_LEVELS/2))+1:0] = {{1*INTPRIORITY_BITS{1'b0}},l2_intpend_w_prior_en_ff[(TOTAL_INT/2**(NUM_LEVELS/2)):0]} ;
|
||||
assign levelx_intpend_id[NUM_LEVELS/2][(TOTAL_INT/2**(NUM_LEVELS/2))+1:0] = {{1*ID_BITS{1'b1}},l2_intpend_id_ff[(TOTAL_INT/2**(NUM_LEVELS/2)):0]} ;
|
||||
|
||||
///////// Do the prioritization of the interrupts here ////////////
|
||||
for (l=0; l<NUM_LEVELS/2 ; l++) begin : TOP_LEVEL
|
||||
for (m=0; m<=(TOTAL_INT)/(2**(l+1)) ; m++) begin : COMPARE
|
||||
if ( m == (TOTAL_INT)/(2**(l+1))) begin
|
||||
assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
|
||||
assign level_intpend_id[l+1][m+1] = '0 ;
|
||||
end
|
||||
cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
|
||||
.a_id(level_intpend_id[l][2*m]),
|
||||
.a_priority(level_intpend_w_prior_en[l][2*m]),
|
||||
.b_id(level_intpend_id[l][2*m+1]),
|
||||
.b_priority(level_intpend_w_prior_en[l][2*m+1]),
|
||||
.out_id(level_intpend_id[l+1][m]),
|
||||
.out_priority(level_intpend_w_prior_en[l+1][m])) ;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
for (i=0; i<=TOTAL_INT/2**(NUM_LEVELS/2) ; i++) begin : MIDDLE_FLOPS
|
||||
rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (.*, .din (level_intpend_w_prior_en[NUM_LEVELS/2][i]), .dout(l2_intpend_w_prior_en_ff[i]), .clk(free_clk));
|
||||
rvdff #(ID_BITS) level2_intpend_id_reg (.*, .din (level_intpend_id[NUM_LEVELS/2][i]), .dout(l2_intpend_id_ff[i]), .clk(free_clk));
|
||||
end
|
||||
|
||||
for (j=NUM_LEVELS/2; j<NUM_LEVELS ; j++) begin : BOT_LEVELS
|
||||
for (k=0; k<=(TOTAL_INT)/(2**(j+1)) ; k++) begin : COMPARE
|
||||
if ( k == (TOTAL_INT)/(2**(j+1))) begin
|
||||
assign levelx_intpend_w_prior_en[j+1][k+1] = '0 ;
|
||||
assign levelx_intpend_id[j+1][k+1] = '0 ;
|
||||
end
|
||||
cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
.INTPRIORITY_BITS(INTPRIORITY_BITS))
|
||||
cmp_l1 (
|
||||
.a_id(levelx_intpend_id[j][2*k]),
|
||||
.a_priority(levelx_intpend_w_prior_en[j][2*k]),
|
||||
.b_id(levelx_intpend_id[j][2*k+1]),
|
||||
.b_priority(levelx_intpend_w_prior_en[j][2*k+1]),
|
||||
.out_id(levelx_intpend_id[j+1][k]),
|
||||
.out_priority(levelx_intpend_w_prior_en[j+1][k])) ;
|
||||
end
|
||||
end
|
||||
assign claimid_in[ID_BITS-1:0] = levelx_intpend_id[NUM_LEVELS][0] ; // This is the last level output
|
||||
assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en[NUM_LEVELS][0] ;
|
||||
|
||||
`else
|
||||
logic [NUM_LEVELS:0] [TOTAL_INT+1:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en;
|
||||
logic [NUM_LEVELS:0] [TOTAL_INT+1:0] [ID_BITS-1:0] level_intpend_id;
|
||||
|
|
@ -263,86 +307,30 @@ end
|
|||
assign level_intpend_w_prior_en[0][TOTAL_INT+1:0] = {{2*INTPRIORITY_BITS{1'b0}},intpend_w_prior_en[TOTAL_INT-1:0]} ;
|
||||
assign level_intpend_id[0][TOTAL_INT+1:0] = {{2*ID_BITS{1'b1}},intpend_id[TOTAL_INT-1:0]} ;
|
||||
|
||||
////////// Do the prioritization of the interrupts here ////////////
|
||||
///////// genvar l, m , j, k; already declared outside ifdef
|
||||
for (l=0; l<NUM_LEVELS ; l++) begin : LEVEL
|
||||
for (m=0; m<=(TOTAL_INT)/(2**(l+1)) ; m++) begin : COMPARE
|
||||
if ( m == (TOTAL_INT)/(2**(l+1))) begin
|
||||
assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
|
||||
assign level_intpend_id[l+1][m+1] = '0 ;
|
||||
end
|
||||
cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
|
||||
.a_id(level_intpend_id[l][2*m]),
|
||||
.a_priority(level_intpend_w_prior_en[l][2*m]),
|
||||
.b_id(level_intpend_id[l][2*m+1]),
|
||||
.b_priority(level_intpend_w_prior_en[l][2*m+1]),
|
||||
.out_id(level_intpend_id[l+1][m]),
|
||||
.out_priority(level_intpend_w_prior_en[l+1][m])) ;
|
||||
|
||||
end
|
||||
end
|
||||
assign claimid_in[ID_BITS-1:0] = level_intpend_id[NUM_LEVELS][0] ; // This is the last level output
|
||||
assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en[NUM_LEVELS][0] ;
|
||||
|
||||
`endif
|
||||
|
||||
genvar l, m , j, k;
|
||||
|
||||
// `ifdef VERILATOR
|
||||
`include "pic_ctrl_verilator_unroll.sv"
|
||||
// `else
|
||||
// `ifdef RV_PIC_2CYCLE
|
||||
// /// Do the prioritization of the interrupts here ////////////
|
||||
// for (l=0; l<NUM_LEVELS/2 ; l++) begin : TOP_LEVEL
|
||||
// for (m=0; m<=(TOTAL_INT)/(2**(l+1)) ; m++) begin : COMPARE
|
||||
// if ( m == (TOTAL_INT)/(2**(l+1))) begin
|
||||
// assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
|
||||
// assign level_intpend_id[l+1][m+1] = '0 ;
|
||||
// end
|
||||
// cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
// .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
|
||||
// .a_id(level_intpend_id[l][2*m]),
|
||||
// .a_priority(level_intpend_w_prior_en[l][2*m]),
|
||||
// .b_id(level_intpend_id[l][2*m+1]),
|
||||
// .b_priority(level_intpend_w_prior_en[l][2*m+1]),
|
||||
// .out_id(level_intpend_id[l+1][m]),
|
||||
// .out_priority(level_intpend_w_prior_en[l+1][m])) ;
|
||||
//
|
||||
// end
|
||||
// end
|
||||
//
|
||||
// for (i=0; i<=TOTAL_INT/2**(NUM_LEVELS/2) ; i++) begin : MIDDLE_FLOPS
|
||||
// rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (.*, .din (level_intpend_w_prior_en[NUM_LEVELS/2][i]), .dout(l2_intpend_w_prior_en_ff[i]), .clk(free_clk));
|
||||
// rvdff #(ID_BITS) level2_intpend_id_reg (.*, .din (level_intpend_id[NUM_LEVELS/2][i]), .dout(l2_intpend_id_ff[i]), .clk(free_clk));
|
||||
// end
|
||||
//
|
||||
// for (j=NUM_LEVELS/2; j<NUM_LEVELS ; j++) begin : BOT_LEVELS
|
||||
// for (k=0; k<=(TOTAL_INT)/(2**(j+1)) ; k++) begin : COMPARE
|
||||
// if ( k == (TOTAL_INT)/(2**(j+1))) begin
|
||||
// assign levelx_intpend_w_prior_en[j+1][k+1] = '0 ;
|
||||
// assign levelx_intpend_id[j+1][k+1] = '0 ;
|
||||
// end
|
||||
// cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
// .INTPRIORITY_BITS(INTPRIORITY_BITS))
|
||||
// cmp_l1 (
|
||||
// .a_id(levelx_intpend_id[j][2*k]),
|
||||
// .a_priority(levelx_intpend_w_prior_en[j][2*k]),
|
||||
// .b_id(levelx_intpend_id[j][2*k+1]),
|
||||
// .b_priority(levelx_intpend_w_prior_en[j][2*k+1]),
|
||||
// .out_id(levelx_intpend_id[j+1][k]),
|
||||
// .out_priority(levelx_intpend_w_prior_en[j+1][k])) ;
|
||||
// end
|
||||
// end
|
||||
// assign claimid_in[ID_BITS-1:0] = levelx_intpend_id[NUM_LEVELS][0] ; // This is the last level output
|
||||
// assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en[NUM_LEVELS][0] ;
|
||||
//
|
||||
// `else
|
||||
//
|
||||
// /// Do the prioritization of the interrupts here ////////////
|
||||
// // genvar l, m , j, k; already declared outside ifdef
|
||||
// for (l=0; l<NUM_LEVELS ; l++) begin : LEVEL
|
||||
// for (m=0; m<=(TOTAL_INT)/(2**(l+1)) ; m++) begin : COMPARE
|
||||
// if ( m == (TOTAL_INT)/(2**(l+1))) begin
|
||||
// assign level_intpend_w_prior_en[l+1][m+1] = '0 ;
|
||||
// assign level_intpend_id[l+1][m+1] = '0 ;
|
||||
// end
|
||||
// cmp_and_mux #(.ID_BITS(ID_BITS),
|
||||
// .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
|
||||
// .a_id(level_intpend_id[l][2*m]),
|
||||
// .a_priority(level_intpend_w_prior_en[l][2*m]),
|
||||
// .b_id(level_intpend_id[l][2*m+1]),
|
||||
// .b_priority(level_intpend_w_prior_en[l][2*m+1]),
|
||||
// .out_id(level_intpend_id[l+1][m]),
|
||||
// .out_priority(level_intpend_w_prior_en[l+1][m])) ;
|
||||
//
|
||||
// end
|
||||
// end
|
||||
// assign claimid_in[ID_BITS-1:0] = level_intpend_id[NUM_LEVELS][0] ; // This is the last level output
|
||||
// assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en[NUM_LEVELS][0] ;
|
||||
//
|
||||
// `endif
|
||||
// `endif
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Config Reg`
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ module swerv
|
|||
(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic dbg_rst_l,
|
||||
input logic [31:1] rst_vec,
|
||||
input logic nmi_int,
|
||||
input logic [31:1] nmi_vec,
|
||||
|
|
@ -674,12 +675,14 @@ module swerv
|
|||
logic [31:0] lsu_result_dc3;
|
||||
logic [31:0] lsu_result_corr_dc4; // ECC corrected lsu load data
|
||||
lsu_error_pkt_t lsu_error_pkt_dc3;
|
||||
logic lsu_single_ecc_error_incr; // Increment the counter for Single ECC error
|
||||
logic lsu_freeze_external_ints_dc3;
|
||||
logic lsu_imprecise_error_load_any;
|
||||
logic lsu_imprecise_error_store_any;
|
||||
logic [31:0] lsu_imprecise_error_addr_any;
|
||||
logic lsu_load_stall_any; // This is for blocking stores
|
||||
logic lsu_store_stall_any; // This is for blocking stores
|
||||
logic lsu_load_ecc_stbuf_full_dc3; // Load with ecc error can't allocate to stbuf
|
||||
logic lsu_idle_any;
|
||||
logic lsu_halt_idle_any; // This is used to enter halt mode. Exclude DMA
|
||||
|
||||
|
|
@ -971,7 +974,6 @@ module swerv
|
|||
.*
|
||||
);
|
||||
|
||||
|
||||
// ----------------- DEBUG END -----------------------------
|
||||
|
||||
assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
|
||||
|
|
@ -1313,3 +1315,4 @@ module swerv
|
|||
|
||||
|
||||
endmodule // swerv
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ module swerv_wrapper
|
|||
(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic dbg_rst_l,
|
||||
input logic [31:1] rst_vec,
|
||||
input logic nmi_int,
|
||||
input logic [31:1] nmi_vec,
|
||||
|
|
@ -424,7 +425,7 @@ module swerv_wrapper
|
|||
.tdoEnable (), // Test Data Output enable
|
||||
|
||||
// Processor Signals
|
||||
.core_rst_n (core_rst_l), // Core reset, active low
|
||||
.core_rst_n (dbg_rst_l), // Primary reset, active low
|
||||
.core_clk (clk), // Core clock
|
||||
.jtag_id (jtag_id), // 32 bit JTAG ID
|
||||
.rd_data (dmi_reg_rdata), // 32 bit Read data from Processor
|
||||
|
|
|
|||
|
|
@ -13,154 +13,183 @@
|
|||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
`ifdef RV_BUILD_AHB_LITE
|
||||
|
||||
module ahb_sif (
|
||||
input logic [63:0] HWDATA,
|
||||
input logic HCLK,
|
||||
input logic HSEL,
|
||||
input logic [3:0] HPROT,
|
||||
input logic HWRITE,
|
||||
input logic [1:0] HTRANS,
|
||||
input logic [2:0] HSIZE,
|
||||
input logic HREADY,
|
||||
input logic HRESETn,
|
||||
input logic [31:0] HADDR,
|
||||
input logic [2:0] HBURST,
|
||||
|
||||
output logic HREADYOUT,
|
||||
output logic HRESP,
|
||||
output logic [63:0] HRDATA
|
||||
input logic [63:0] HWDATA,
|
||||
input logic HCLK,
|
||||
input logic HSEL,
|
||||
input logic [3:0] HPROT,
|
||||
input logic HWRITE,
|
||||
input logic [1:0] HTRANS,
|
||||
input logic [2:0] HSIZE,
|
||||
input logic HREADY,
|
||||
input logic HRESETn,
|
||||
input logic [31:0] HADDR,
|
||||
input logic [2:0] HBURST,
|
||||
|
||||
output logic HREADYOUT,
|
||||
output logic HRESP,
|
||||
output logic [63:0] HRDATA
|
||||
);
|
||||
|
||||
localparam MEM_SIZE_DW = 8192;
|
||||
localparam MAILBOX_ADDR = 32'hD0580000;
|
||||
parameter MEM_SIZE_DW = 8192;
|
||||
parameter MAILBOX_ADDR = 32'hD0580000;
|
||||
localparam MEM_SIZE = MEM_SIZE_DW*8;
|
||||
|
||||
logic Last_HSEL;
|
||||
logic NextLast_HSEL;
|
||||
logic Last_HWRITE;
|
||||
logic [1:0] Last_HTRANS;
|
||||
logic [1:0] NextLast_HTRANS;
|
||||
logic Write;
|
||||
logic [31:0] Last_HADDR;
|
||||
logic [63:0] Next_HRDATA;
|
||||
logic [63:0] WriteReadData;
|
||||
logic [63:0] WriteMask;
|
||||
|
||||
bit [7:0] mem [0:MEM_SIZE_DW-1];
|
||||
logic [7:0] strb_lat;
|
||||
|
||||
bit [7:0] mem [0:MEM_SIZE-1];
|
||||
//bit [7:0] mem [int];
|
||||
//int kuku[int];
|
||||
|
||||
// Wires
|
||||
wire [63:0] Next_WriteMask = HSIZE == 3'b000 ? (64'hff << {HADDR[2:0], 3'b000}) : (HSIZE == 3'b001 ? (64'hffff << {HADDR[2], 4'h0}) : (HSIZE == 3'b010 ? (64'hffff_ffff << {HADDR[3],5'h0}) : 64'hffff_ffff_ffff_ffff));
|
||||
wire [63:0] WriteData = HWDATA;
|
||||
wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
|
||||
HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
|
||||
HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
|
||||
|
||||
wire [63:0] MaskedWriteData = HWDATA & WriteMask;
|
||||
wire [63:0] MaskedWriteReadData = WriteReadData & ~WriteMask;
|
||||
wire [63:0] WriteData = (MaskedWriteData | MaskedWriteReadData );
|
||||
wire Write = &{Last_HSEL, Last_HWRITE, Last_HTRANS[1]};
|
||||
wire Read = &{ HSEL, ~HWRITE, HTRANS[1]};
|
||||
wire[31:0] addr = HADDR & (MEM_SIZE-1);
|
||||
wire[31:0] laddr = Last_HADDR & (MEM_SIZE-1);
|
||||
|
||||
wire mailbox_write = &{Write, Last_HADDR==MAILBOX_ADDR, HRESETn==1};
|
||||
wire Next_HWRITE = |{HTRANS} ? HWRITE : Last_HWRITE;
|
||||
wire [63:0] mem_dout = {mem[{Last_HADDR[12:3],3'b0}+7],mem[{Last_HADDR[12:3],3'b0}+6],mem[{Last_HADDR[12:3],3'b0}+5],mem[{Last_HADDR[12:3],3'b0}+4],mem[{Last_HADDR[12:3],3'b0}+3],mem[{Last_HADDR[12:3],3'b0}+2],mem[{Last_HADDR[12:3],3'b0}+1],mem[{Last_HADDR[12:3],3'b0}]};
|
||||
wire mailbox_write = Write && Last_HADDR==MAILBOX_ADDR;
|
||||
|
||||
wire [63:0] mem_dout = {mem[{addr[31:3],3'd7}],
|
||||
mem[{addr[31:3],3'd6}],
|
||||
mem[{addr[31:3],3'd5}],
|
||||
mem[{addr[31:3],3'd4}],
|
||||
mem[{addr[31:3],3'd3}],
|
||||
mem[{addr[31:3],3'd2}],
|
||||
mem[{addr[31:3],3'd1}],
|
||||
mem[{addr[31:3],3'd0}]};
|
||||
|
||||
|
||||
always @ (posedge HCLK or negedge HRESETn) begin
|
||||
if (Write && Last_HADDR == 32'h0) begin
|
||||
mem[{Last_HADDR[12:3],3'b0}+7] <= #1 { WriteData[63:56] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+6] <= #1 { WriteData[55:48] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+5] <= #1 { WriteData[47:40] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+4] <= #1 { WriteData[39:32] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+3] <= #1 { WriteData[31:24] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+2] <= #1 { WriteData[23:16] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+1] <= #1 { WriteData[15:08] };
|
||||
mem[{Last_HADDR[12:3],3'b0}+0] <= #1 { WriteData[07:00] };
|
||||
always @ (negedge HCLK ) begin
|
||||
if (Write) begin
|
||||
if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56];
|
||||
if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48];
|
||||
if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40];
|
||||
if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32];
|
||||
if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24];
|
||||
if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16];
|
||||
if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08];
|
||||
if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign HREADYOUT = 1;
|
||||
assign HRESP = 0;
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
HREADYOUT <= #1 1'b0 ;
|
||||
HRESP <= #1 1'b0;
|
||||
Last_HADDR <= 32'b0;
|
||||
Write <= 1'b0;
|
||||
HRDATA <= '0;
|
||||
end else begin
|
||||
HREADYOUT <= #1 |HTRANS;
|
||||
HRESP <= #1 1'b0;
|
||||
WriteMask <= #1 Next_WriteMask;
|
||||
end
|
||||
end
|
||||
|
||||
`ifdef VERILATOR
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
`else
|
||||
always @(negedge HCLK or negedge HRESETn) begin
|
||||
`endif
|
||||
if(~HRESETn) begin
|
||||
Last_HADDR <= #1 32'b0;
|
||||
end else begin
|
||||
Last_HADDR <= #1 |{HTRANS} ? {HADDR[31:2], 2'b00} : Last_HADDR;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
Last_HWRITE <= #1 1'b0;
|
||||
end else begin
|
||||
Last_HWRITE <= #1 Next_HWRITE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
Last_HTRANS <= #1 2'b0;
|
||||
end else begin
|
||||
Last_HTRANS <= #1 HTRANS;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
Last_HSEL <= #1 1'b0;
|
||||
end else begin
|
||||
Last_HSEL <= #1 HSEL;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
`ifndef VERILATOR
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
HRDATA <= #1 Next_HRDATA ;
|
||||
end else begin
|
||||
HRDATA <= #1 Next_HRDATA ;
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
Next_HRDATA = mem_dout;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
always @(posedge HCLK) begin
|
||||
Next_HRDATA <= mem_dout;
|
||||
end
|
||||
|
||||
assign HRDATA = mem_dout;
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
always @* begin
|
||||
if(Last_HSEL) begin
|
||||
WriteReadData[07:00] = mem[{Last_HADDR[12:3],3'b0}];
|
||||
WriteReadData[15:08] = mem[{Last_HADDR[12:3],3'b0}+1];
|
||||
WriteReadData[23:16] = mem[{Last_HADDR[12:3],3'b0}+2];
|
||||
WriteReadData[31:24] = mem[{Last_HADDR[12:3],3'b0}+3];
|
||||
WriteReadData[39:32] = mem[{Last_HADDR[12:3],3'b0}+4];
|
||||
WriteReadData[47:40] = mem[{Last_HADDR[12:3],3'b0}+5];
|
||||
WriteReadData[55:48] = mem[{Last_HADDR[12:3],3'b0}+6];
|
||||
WriteReadData[63:56] = mem[{Last_HADDR[12:3],3'b0}+7];
|
||||
Last_HADDR <= HADDR;
|
||||
Write <= HWRITE & |HTRANS;
|
||||
if(|HTRANS & ~HWRITE)
|
||||
HRDATA <= mem_dout;
|
||||
strb_lat <= strb;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef RV_BUILD_AXI4
|
||||
module axi_slv #(TAGW=1) (
|
||||
input aclk,
|
||||
input rst_l,
|
||||
input arvalid,
|
||||
output reg arready,
|
||||
input [31:0] araddr,
|
||||
input [TAGW-1:0] arid,
|
||||
input [7:0] arlen,
|
||||
input [1:0] arburst,
|
||||
input [2:0] arsize,
|
||||
|
||||
output reg rvalid,
|
||||
input rready,
|
||||
output reg [63:0] rdata,
|
||||
output reg [1:0] rresp,
|
||||
output reg [TAGW-1:0] rid,
|
||||
output rlast,
|
||||
|
||||
input awvalid,
|
||||
output awready,
|
||||
input [31:0] awaddr,
|
||||
input [TAGW-1:0] awid,
|
||||
input [7:0] awlen,
|
||||
input [1:0] awburst,
|
||||
input [2:0] awsize,
|
||||
|
||||
input [63:0] wdata,
|
||||
input [7:0] wstrb,
|
||||
input wvalid,
|
||||
output wready,
|
||||
|
||||
output reg bvalid,
|
||||
input bready,
|
||||
output reg [1:0] bresp,
|
||||
output reg [TAGW-1:0] bid
|
||||
);
|
||||
|
||||
parameter MAILBOX_ADDR = 32'hD0580000;
|
||||
parameter MEM_SIZE_DW = 8192;
|
||||
|
||||
bit [7:0] mem [0:MEM_SIZE_DW*8-1];
|
||||
bit [63:0] memdata;
|
||||
wire [31:0] waddr, raddr;
|
||||
wire [63:0] WriteData;
|
||||
wire mailbox_write;
|
||||
|
||||
assign raddr = araddr & (MEM_SIZE_DW*8-1);
|
||||
assign waddr = awaddr & (MEM_SIZE_DW*8-1);
|
||||
|
||||
assign mailbox_write = awvalid && awaddr==MAILBOX_ADDR && rst_l;
|
||||
assign WriteData = wdata;
|
||||
|
||||
always @ ( posedge aclk or negedge rst_l) begin
|
||||
if(!rst_l) begin
|
||||
rvalid <= 0;
|
||||
bvalid <= 0;
|
||||
end
|
||||
else begin
|
||||
bid <= awid;
|
||||
rid <= arid;
|
||||
rvalid <= arvalid;
|
||||
bvalid <= awvalid;
|
||||
rdata <= memdata;
|
||||
end
|
||||
end
|
||||
|
||||
always @ ( negedge aclk) begin
|
||||
if(arvalid) memdata <= {mem[raddr+7], mem[raddr+6], mem[raddr+5], mem[raddr+4],
|
||||
mem[raddr+3], mem[raddr+2], mem[raddr+1], mem[raddr]};
|
||||
if(awvalid) begin
|
||||
if(wstrb[7]) mem[waddr+7] = wdata[63:56];
|
||||
if(wstrb[6]) mem[waddr+6] = wdata[55:48];
|
||||
if(wstrb[5]) mem[waddr+5] = wdata[47:40];
|
||||
if(wstrb[4]) mem[waddr+4] = wdata[39:32];
|
||||
if(wstrb[3]) mem[waddr+3] = wdata[31:24];
|
||||
if(wstrb[2]) mem[waddr+2] = wdata[23:16];
|
||||
if(wstrb[1]) mem[waddr+1] = wdata[15:08];
|
||||
if(wstrb[0]) mem[waddr+0] = wdata[07:00];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign arready = 1'b1;
|
||||
assign awready = 1'b1;
|
||||
assign wready = 1'b1;
|
||||
assign rresp = 2'b0;
|
||||
assign bresp = 2'b0;
|
||||
assign rlast = 1'b1;
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -1,67 +1,72 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
|
||||
// Assembly code for Hello World
|
||||
// Not using only ALU ops for creating the string
|
||||
|
||||
|
||||
#include "defines.h"
|
||||
|
||||
#define STDOUT 0xd0580000
|
||||
|
||||
|
||||
// Code to execute
|
||||
.section .text
|
||||
.global _start
|
||||
_start:
|
||||
csrrw x2, 0xb02, x3
|
||||
|
||||
// Clear minstret
|
||||
csrw minstret, zero
|
||||
csrw minstreth, zero
|
||||
|
||||
// Set up MTVEC - not expecting to use it though
|
||||
li x1, RV_ICCM_SADR
|
||||
csrw mtvec, x1
|
||||
|
||||
|
||||
lui x5, 974848
|
||||
ori x5, x5, 0
|
||||
csrrw x2, 0x305, x5
|
||||
// Enable Caches in MRAC
|
||||
li x1, 0x5f555555
|
||||
csrw 0x7c0, x1
|
||||
|
||||
// Load string from hw_data
|
||||
// and write to stdout address
|
||||
|
||||
lui x6, 382293
|
||||
ori x6, x6, 1365
|
||||
csrrw x1, 0x7c0, x6
|
||||
li x3, STDOUT
|
||||
la x4, hw_data
|
||||
|
||||
loop:
|
||||
lb x5, 0(x4)
|
||||
sb x5, 0(x3)
|
||||
addi x4, x4, 1
|
||||
bnez x5, loop
|
||||
|
||||
// Write 0xff to STDOUT for TB to terminate test.
|
||||
_finish:
|
||||
li x3, STDOUT
|
||||
addi x5, x0, 0xff
|
||||
sb x5, 0(x3)
|
||||
beq x0, x0, _finish
|
||||
.rept 100
|
||||
nop
|
||||
.endr
|
||||
|
||||
|
||||
lui x5, 0
|
||||
ori x5, x5, 0
|
||||
csrrw x2, 0x7f8, x5
|
||||
|
||||
|
||||
|
||||
|
||||
lui x5, 0
|
||||
ori x5, x5, 0
|
||||
csrrw x2, 0x7f9, x5
|
||||
|
||||
|
||||
addi x0, x0, 0
|
||||
lui x11, 853376
|
||||
ori x9, x0, 'H'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'E'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'L'
|
||||
sw x9, 0 (x11)
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'O'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, ' '
|
||||
sw x9, 0 (x11)
|
||||
addi x9, x0, 'W'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'O'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'R'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'L'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 'D'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, '!'
|
||||
sw x9, 0 (x11)
|
||||
ori x9, x0, 255
|
||||
sw x9, 0 (x11)
|
||||
addi x1,x0,0
|
||||
|
||||
finish:
|
||||
addi x1,x1,1
|
||||
jal x0, finish;
|
||||
addi x0,x0,0
|
||||
addi x0,x0,0
|
||||
addi x0,x0,0
|
||||
addi x0,x0,0
|
||||
.global hw_data
|
||||
.data
|
||||
hw_data:
|
||||
.ascii "----------------------------------\n"
|
||||
.ascii "Hello World from SweRV EH1 @WDC !!\n"
|
||||
.ascii "----------------------------------\n"
|
||||
.byte 0
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ ENTRY(_start)
|
|||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x1000;
|
||||
.data . : { *(.*data) *(.rodata*) }
|
||||
. = 0x0;
|
||||
.text . : { *(.text) }
|
||||
. = 0;
|
||||
.text : { *(.text*) }
|
||||
_end = .;
|
||||
. = 0x10000;
|
||||
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -22,62 +22,50 @@
|
|||
#include "verilated_vcd_c.h"
|
||||
|
||||
|
||||
// /*
|
||||
vluint64_t main_time = 0;
|
||||
|
||||
double sc_time_stamp () {
|
||||
return main_time;
|
||||
}
|
||||
// */
|
||||
|
||||
//int main(int argc, char* argv[]) {
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
|
||||
|
||||
// Check for +dumpon and remove it from argv
|
||||
bool dumpWaves = false;
|
||||
int newArgc = 0;
|
||||
for (int i = 0; i < argc; ++i)
|
||||
if (strcmp(argv[i], "+dumpon") == 0)
|
||||
dumpWaves = true;
|
||||
else
|
||||
argv[newArgc++] = argv[i];
|
||||
argc = newArgc;
|
||||
|
||||
std::cout << "\nStart of sim\n" << std::endl;
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
Vtb_top* tb = new Vtb_top;
|
||||
uint32_t clkCnt = 0;
|
||||
|
||||
// init trace dump
|
||||
Verilated::traceEverOn(true);
|
||||
VerilatedVcdC* tfp = new VerilatedVcdC;
|
||||
tb->trace (tfp, 24);
|
||||
if (dumpWaves)
|
||||
tfp->open ("sim.vcd");
|
||||
|
||||
|
||||
// Simulate
|
||||
for(auto i=0; i<200000; ++i){
|
||||
clkCnt++;
|
||||
if(i<10) {
|
||||
tb->reset_l = 0;
|
||||
} else {
|
||||
tb->reset_l = 1;
|
||||
}
|
||||
|
||||
for (auto clk=0; clk<2; clk++) {
|
||||
tfp->dump (2*i+clk);
|
||||
while(!Verilated::gotFinish()){
|
||||
if (dumpWaves)
|
||||
tfp->dump (main_time);
|
||||
main_time += 5;
|
||||
tb->core_clk = !tb->core_clk;
|
||||
tb->eval();
|
||||
}
|
||||
|
||||
if (tb->finished) {
|
||||
if (dumpWaves)
|
||||
tfp->close();
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for(auto i=0; i<100; ++i){
|
||||
clkCnt++;
|
||||
for (auto clk=0; clk<2; clk++) {
|
||||
tfp->dump (2*i+clk);
|
||||
tb->core_clk = !tb->core_clk;
|
||||
tb->eval();
|
||||
}
|
||||
}
|
||||
|
||||
std::cout << "\nEnd of sim" << std::endl;
|
||||
std::cout << "\nVerilatorTB: End of sim" << std::endl;
|
||||
exit(EXIT_SUCCESS);
|
||||
|
||||
}
|
||||
|
|
|
|||
176
tools/Makefile
176
tools/Makefile
|
|
@ -1,5 +1,5 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
# Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
# Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
|
|
@ -20,110 +20,140 @@ $(error env var RV_ROOT does not point to a valid dir! Exiting!)
|
|||
endif
|
||||
|
||||
# Allow snapshot override
|
||||
ifeq ($(strip $(snapshot)),)
|
||||
snapshot = default
|
||||
endif
|
||||
target = default
|
||||
snapshot = $(target)
|
||||
|
||||
# Allow tool override
|
||||
SWERV_CONFIG = ${RV_ROOT}/configs/swerv.config
|
||||
IRUN = irun
|
||||
VCS = vcs
|
||||
VERILATOR = verilator
|
||||
VLOG = qverilog
|
||||
GCC_PREFIX = riscv64-unknown-elf
|
||||
BUILD_DIR = snapshots/${snapshot}
|
||||
TBDIR = ${RV_ROOT}/testbench
|
||||
|
||||
# Define test name
|
||||
ifeq ($(strip $(ASM_TEST)),)
|
||||
ASM_TEST = hello_world2
|
||||
# Define default test name
|
||||
TEST = hello_world
|
||||
|
||||
# Define default test directory
|
||||
TEST_DIR = $(TBDIR)/asm
|
||||
HEX_DIR = $(TBDIR)/hex
|
||||
|
||||
ifdef debug
|
||||
DEBUG_PLUS = +dumpon
|
||||
IRUN_DEBUG = -access +rc
|
||||
IRUN_DEBUG_RUN = -input ${RV_ROOT}/testbench/input.tcl
|
||||
VCS_DEBUG = -debug_access
|
||||
endif
|
||||
|
||||
# Define test name
|
||||
ifeq ($(strip $(ASM_TEST_DIR)),)
|
||||
ASM_TEST_DIR = ${RV_ROOT}/testbench/asm
|
||||
# provide specific link file
|
||||
ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
|
||||
LINK = $(TBDIR)/link.ld
|
||||
else
|
||||
LINK = $(TEST_DIR)/$(TEST).ld
|
||||
endif
|
||||
|
||||
defines = ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh ${RV_ROOT}/design/include/build.h ${RV_ROOT}/design/include/global.h ${RV_ROOT}/design/include/swerv_types.sv
|
||||
includes = -I${RV_ROOT}/design/include -I${RV_ROOT}/design/lib -I${RV_ROOT}/design/dmi -I${RV_ROOT}/configs/snapshots/$(snapshot)
|
||||
VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
|
||||
TBFILES = $(TBDIR)/tb_top.sv $(TBDIR)/ahb_sif.sv
|
||||
|
||||
defines = $(BUILD_DIR)/common_defines.vh ${RV_ROOT}/design/include/swerv_types.sv
|
||||
includes = -I${RV_ROOT}/design/include -I${RV_ROOT}/design/lib -I${BUILD_DIR}
|
||||
|
||||
# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
|
||||
CFLAGS += "-std=c++11"
|
||||
# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
|
||||
# -O2 for faster runtime (slower compiles), or -O for balance.
|
||||
VERILATOR_MAKE_FLAGS = OPT_FAST=""
|
||||
VERILATOR_MAKE_FLAGS = OPT_FAST="-O2"
|
||||
|
||||
# Targets
|
||||
all: clean verilator
|
||||
|
||||
clean:
|
||||
rm -rf obj_dir *.hex build ${RV_ROOT}/configs/snapshots/$(snapshot)
|
||||
rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* snapshots swerv* \
|
||||
verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv
|
||||
|
||||
verilator: ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
echo '`undef ASSERT_ON' >> ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
$(VERILATOR) '-UASSERT_ON' --cc -CFLAGS ${CFLAGS} $(defines) $(includes) ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh \
|
||||
-f ${RV_ROOT}/testbench/flist.verilator --top-module swerv_wrapper
|
||||
$(MAKE) -C obj_dir/ -f Vswerv_wrapper.mk $(VERILATOR_MAKE_FLAGS)
|
||||
# If define files do not exist, then run swerv.config.
|
||||
${BUILD_DIR}/defines.h :
|
||||
BUILD_PATH=${BUILD_DIR} ${SWERV_CONFIG} -target=$(target) $(CONF_PARAMS)
|
||||
|
||||
vcs: ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
$(VCS) -full64 -assert svaext -sverilog +define+RV_OPENSOURCE +error+500 +incdir+${RV_ROOT}/design/lib +incdir+${RV_ROOT}/design/include \
|
||||
${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh \
|
||||
+incdir+${RV_ROOT}/design/dmi +incdir+${RV_ROOT}/configs/snapshots/$(snapshot) +libext+.v ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh \
|
||||
$(defines)-f ${RV_ROOT}/testbench/flist.vcs -l vcs.log
|
||||
|
||||
irun: ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
$(IRUN) -64bit -elaborate -ida -access +rw -q -sv -sysv -nowarn CUVIHR -nclibdirpath ${PWD} -nclibdirname swerv.build \
|
||||
-incdir ${RV_ROOT}/design/lib -incdir ${RV_ROOT}/design/include -incdir ${RV_ROOT}/design/dmi -vlog_ext +.vh+.h\
|
||||
$(defines) -incdir ${RV_ROOT}/configs/snapshots/$(snapshot) -f ${RV_ROOT}/testbench/flist.vcs -elaborate -snapshot default
|
||||
|
||||
${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh:
|
||||
$(SWERV_CONFIG) -snapshot=$(snapshot)
|
||||
|
||||
verilator-run: program.hex
|
||||
snapshot=ahb_lite
|
||||
$(SWERV_CONFIG) -snapshot=$(snapshot) -ahb_lite
|
||||
echo '`undef ASSERT_ON' >> ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
$(VERILATOR) '-UASSERT_ON' --cc -CFLAGS ${CFLAGS} $(defines) $(includes) ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh \
|
||||
${RV_ROOT}/testbench/tb_top.sv -I${RV_ROOT}/testbench \
|
||||
-f ${RV_ROOT}/testbench/flist.verilator --top-module tb_top -exe test_tb_top.cpp --trace --autoflush
|
||||
verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h test_tb_top.cpp
|
||||
echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
|
||||
$(VERILATOR) '-UASSERT_ON' --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
|
||||
-Wno-UNOPTFLAT \
|
||||
-I${RV_ROOT}/testbench \
|
||||
-f ${RV_ROOT}/testbench/flist \
|
||||
${TBFILES} \
|
||||
--top-module tb_top -exe test_tb_top.cpp --trace --autoflush
|
||||
cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/
|
||||
$(MAKE) -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
|
||||
./obj_dir/Vtb_top
|
||||
touch verilator-build
|
||||
|
||||
irun-run: program.hex
|
||||
snapshot=ahb_lite
|
||||
$(SWERV_CONFIG) -snapshot=$(snapshot) -ahb_lite
|
||||
$(IRUN) -64bit -ida -access +rw -q -sv -sysv -nowarn CUVIHR -nclibdirpath ${PWD} -nclibdirname swerv.build \
|
||||
-incdir ${RV_ROOT}/design/lib -incdir ${RV_ROOT}/design/include -incdir ${RV_ROOT}/design/dmi -vlog_ext +.vh+.h\
|
||||
$(defines) -top tb_top ${RV_ROOT}/testbench/tb_top.sv -I${RV_ROOT}/testbench ${RV_ROOT}/testbench/ahb_sif.sv\
|
||||
-incdir ${RV_ROOT}/configs/snapshots/$(snapshot) -f ${RV_ROOT}/testbench/flist.vcs -snapshot default
|
||||
vcs-build: ${TBFILES} ${BUILD_DIR}/defines.h
|
||||
$(VCS) -full64 -assert svaext -sverilog +error+500 \
|
||||
+incdir+${RV_ROOT}/design/lib \
|
||||
+incdir+${RV_ROOT}/design/include \
|
||||
+incdir+${BUILD_DIR} +libext+.v\
|
||||
$(defines) -f ${RV_ROOT}/testbench/flist\
|
||||
${TBFILES} \
|
||||
-l vcs_compile.log
|
||||
touch vcs-build
|
||||
|
||||
vcs-run: program.hex
|
||||
snapshot=ahb_lite
|
||||
$(SWERV_CONFIG) -snapshot=$(snapshot) -ahb_lite
|
||||
cp ${RV_ROOT}/testbench/hex/*.hex .
|
||||
$(VCS) -full64 -assert svaext -sverilog +define+RV_OPENSOURCE +error+500 +incdir+${RV_ROOT}/design/lib +incdir+${RV_ROOT}/design/include \
|
||||
${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh \
|
||||
+incdir+${RV_ROOT}/design/dmi +incdir+${RV_ROOT}/configs/snapshots/$(snapshot) +libext+.v \
|
||||
$(defines) -f ${RV_ROOT}/testbench/flist.vcs ${RV_ROOT}/testbench/tb_top.sv -I${RV_ROOT}/testbench ${RV_ROOT}/testbench/ahb_sif.sv -l vcs.log
|
||||
./simv
|
||||
irun-build: ${TBFILES} ${BUILD_DIR}/defines.h
|
||||
$(IRUN) -64bit -elaborate $(IRUN_DEBUG) -q -sv -sysv -nowarn CUVIHR -nclibdirpath . -nclibdirname swerv.build \
|
||||
-incdir ${RV_ROOT}/design/lib -incdir ${RV_ROOT}/design/include -incdir ${BUILD_DIR} -vlog_ext +.vh+.h\
|
||||
$(defines) -f ${RV_ROOT}/testbench/flist\
|
||||
-top tb_top ${TBFILES} -I${RV_ROOT}/testbench \
|
||||
-elaborate -snapshot $(snapshot)
|
||||
touch irun-build
|
||||
|
||||
program.hex: $(ASM_TEST_DIR)/$(ASM_TEST).s ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh
|
||||
@echo Building $(ASM_TEST)
|
||||
ifeq ($(shell which $(GCC_PREFIX)-as),)
|
||||
@echo " !!! No $(GCC_PREFIX)-as in path, using canned hex files !!"
|
||||
cp ${RV_ROOT}/testbench/hex/*.hex .
|
||||
verilator: program.hex verilator-build
|
||||
./obj_dir/Vtb_top ${DEBUG_PLUS}
|
||||
|
||||
irun: program.hex irun-build
|
||||
$(IRUN) -64bit -abvglobalfailurelimit 1 +lic_queue -licqueue -status -nclibdirpath . -nclibdirname swerv.build \
|
||||
-snapshot ${snapshot} -r ${snapshot} $(IRUN_DEBUG_RUN)
|
||||
|
||||
vcs: program.hex vcs-build
|
||||
./simv $(DEBUG_PLUS) +vcs+lic+wait -l vcs.log
|
||||
|
||||
vlog: program.hex ${TBFILES} ${BUILD_DIR}/defines.h
|
||||
$(VLOG) -l vlog.log -sv -mfcu +incdir+${BUILD_DIR}+${RV_ROOT}/design/include+${RV_ROOT}/design/lib\
|
||||
$(defines) -f ${RV_ROOT}/testbench/flist ${TBFILES} -R ${DEBUG_PLUS}
|
||||
|
||||
ifeq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)
|
||||
program.hex: ${BUILD_DIR}/defines.h
|
||||
@echo " !!! No $(GCC_PREFIX)-gcc in path, using canned hex files !!"
|
||||
cp ${HEX_DIR}/$(TEST).program.hex program.hex
|
||||
cp ${HEX_DIR}/$(TEST).data.hex data.hex
|
||||
else
|
||||
cp $(ASM_TEST_DIR)/$(ASM_TEST).s .
|
||||
$(GCC_PREFIX)-cpp -I${RV_ROOT}/configs/snapshots/$(snapshot) $(ASM_TEST).s > $(ASM_TEST).cpp.s
|
||||
$(GCC_PREFIX)-as -march=rv32imc $(ASM_TEST).cpp.s -o $(ASM_TEST).o
|
||||
$(GCC_PREFIX)-ld -m elf32lriscv --discard-none -T${RV_ROOT}/testbench/link.ld -o $(ASM_TEST).exe $(ASM_TEST).o
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".data*" --only-section ".rodata*" $(ASM_TEST).exe data.hex
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".text*" --set-start=0x0 $(ASM_TEST).exe program.hex
|
||||
$(GCC_PREFIX)-objdump -dS $(ASM_TEST).exe > $(ASM_TEST).dis
|
||||
$(GCC_PREFIX)-nm -f posix -C $(ASM_TEST).exe > $(ASM_TEST).tbl
|
||||
@echo Completed building $(ASM_TEST)
|
||||
ifneq (,$(wildcard $(TEST_DIR)/$(TEST).makefile))
|
||||
program.hex:
|
||||
$(MAKE) -f $(TEST_DIR)/$(TEST).makefile
|
||||
else
|
||||
program.hex: $(TEST).o $(LINK)
|
||||
@echo Building $(TEST)
|
||||
$(GCC_PREFIX)-ld -m elf32lriscv --discard-none -T$(LINK) -o $(TEST).exe $(TEST).o
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".data*" --change-section-lma .data=0 $(TEST).exe data.hex
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".text*" $(TEST).exe program.hex
|
||||
$(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis
|
||||
$(GCC_PREFIX)-nm -f posix -C $(TEST).exe > $(TEST).tbl
|
||||
@echo Completed building $(TEST)
|
||||
|
||||
%.o : %.s ${BUILD_DIR}/defines.h
|
||||
$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(TEST).cpp.s
|
||||
$(GCC_PREFIX)-as -march=rv32gc $(TEST).cpp.s -o $(TEST).o
|
||||
|
||||
TEST_CFLAGS = -g -O3 -funroll-all-loops
|
||||
ABI = -mabi=ilp32 -march=rv32imc
|
||||
|
||||
%.o : %.c ${BUILD_DIR}/defines.h
|
||||
$(GCC_PREFIX)-gcc -I${BUILD_DIR} ${TEST_CFLAGS} ${ABI} -nostdlib -c $< -o $@
|
||||
endif
|
||||
endif
|
||||
|
||||
help:
|
||||
@echo Make sure the environment variable RV_ROOT is set.
|
||||
@echo Possible targets: verilator vcs irun help clean all verilator-run irun-run vcs-run program.hex
|
||||
@echo Possible targets: verilator vcs irun vlog help clean all verilator-build irun-build vcs-build program.hex
|
||||
|
||||
.PHONY: help clean verilator vcs irun verilator-run irun-run vcs-run
|
||||
.PHONY: help clean verilator vcs irun vlog
|
||||
|
|
|
|||
Loading…
Reference in New Issue