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Formatting changes.

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Joseph Rahmeh 2020-02-18 13:51:15 -08:00
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release-notes.md
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@ -6,63 +6,63 @@ This is a bug-fix and performance-improvement release. No new functionality
is added to the SweRV core.
## Bug fixes:
1. Bug fixes:
1. Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
* Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
Codasip).
2. Hart never asserted the dmstatus.allrunning signal on reset which
* Hart never asserted the dmstatus.allrunning signal on reset which
caused a timeout in OpenOCD (reported by Codasip).
3. Debug module failed to auto-increment register on system-bus access
* Debug module failed to auto-increment register on system-bus access
of size 64-bit (reported by Codasip).
4. The core_rst_n signal was incorrectly connected (reported by Codasip).
5. Moudule/instance renamed for tool compatibility.
6. The program counter was getting corrupted when the load/store unit
* The core_rst_n signal was incorrectly connected (reported by Codasip).
* Moudule/instance renamed for tool compatibility.
* The program counter was getting corrupted when the load/store unit
indicated both a single-bit and a double-bit error in the same
cycle.
7. The MSTATUS control register was not being updated as expected when
* The MSTATUS control register was not being updated as expected when
both a non-maskable-interrupt and an MSTATUS-write happened in the
same cycle.
8. Write to SBDATA0 was not starting an system-bus write access when
* Write to SBDATA0 was not starting an system-bus write access when
sbreadonaddr/sbreadondata is set.
9. Minstret was incorrectly counting ecall/ebreak instructions
10. The dec_tlu_mpc_halted_only signal was not set for MPC halt after
* Minstret was incorrectly counting ecall/ebreak instructions
* The dec_tlu_mpc_halted_only signal was not set for MPC halt after
reset.
11. The MEPC control register was not being updated when a
* The MEPC control register was not being updated when a
firmware-halt request was followed by a timer interrupt.
12. The MINSTRETH control register was being incremented when
* The MINSTRETH control register was being incremented when
performance counters were disabled.
13. Bus driver contained combinational logic from multiple clock
* Bus driver contained combinational logic from multiple clock
domains that sometimes caused a glitch.
14. System bus reads were always being made with 64-bit size for the
* System bus reads were always being made with 64-bit size for the
AXI bus which is incorrect for IO access.
15. DCCM single bit errors were counted for instruction that did not
* DCCM single bit errors were counted for instruction that did not
commit.
16. ICCM Single Bit Errors were double counted.
17. Load/store unit was not detecting access faults when DCCM and PIC
* ICCM Single Bit Errors were double counted.
* Load/store unit was not detecting access faults when DCCM and PIC
memories are next to each other.
18. Single bit ECC errors on data load were not always corrected in
* Single bit ECC errors on data load were not always corrected in
the DCCM.
19. ECC single bit error were not always corrected in the DCCM for DMA
* ECC single bit error were not always corrected in the DCCM for DMA
access.
20. Single bit Errors detected while reading ICCM through DMA were not
* Single bit Errors detected while reading ICCM through DMA were not
being corrected in memory.
## Improvements:
2. Improvements:
1. Improved performance by removing redundant term in decode stall
* Improved performance by removing redundant term in decode stall
logic.
2. Reduced power used by the ICCM memory arrays.
* Reduced power used by the ICCM memory arrays.
## Testbench Improvements:
3. Testbench Improvements:
1. AXI4 and AHB-Lite support.
2. Updated bus memory to be persistent and handle larger programs.
3. Makefile supports ability to run with source or pre-generated hex
* AXI4 and AHB-Lite support.
* Updated bus memory to be persistent and handle larger programs.
* Makefile supports ability to run with source or pre-generated hex
files.
4. Makefile supports targets for coremarks benchmark (issue #25).
5. Questa support in Makefile (Issue #19).
* Makefile supports targets for coremarks benchmark (issue #25).
* Questa support in Makefile (Issue #19).