colin
/
abstractaccelerator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Changed version to 1.5.

This commit is contained in:
Joseph Rahmeh 2020-02-18 13:41:42 -08:00
parent 9228e01812
commit a44ef01adf
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README.md
View File

@ -1,6 +1,6 @@
# SweRV RISC-V Core<sup>TM</sup> 1.4 from Western Digital
# SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
This repository contains the SweRV Core<sup>TM</sup> 1.3 design RTL. The previous version can be found in [branch 1.3.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.3)
This repository contains the SweRV Core<sup>TM</sup> 1.5 design RTL. The previous version can be found in [branch 1.4.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.4)
The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
## License