Conditioned declaration of finished per issue #13

This commit is contained in:
Ajay Nath 2019-09-03 21:35:43 -04:00
parent 2108e722c8
commit fc331027c2
1 changed files with 2 additions and 0 deletions

View File

@ -100,7 +100,9 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
logic [31:0] cycleCnt ;
logic mailbox_data_val;
`ifndef VERILATOR
logic finished;
`endif
wire dma_hready_out;