colin
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0a00e20cfe
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Update riscv gcc version and usage.
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2022-03-06 04:21:41 +00:00 |
|
colin
|
3da81c5916
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Add install commond in riscv gnu tools.
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2022-03-01 13:22:23 +00:00 |
|
colin
|
3972a891ca
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Add fpga demo in Cores.
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2022-02-21 07:52:52 +00:00 |
|
colin
|
3edc87e0ea
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Switch mem bus from ahb to axi.
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2022-02-17 11:35:01 +00:00 |
|
colin
|
8e190efed0
|
Split from soc.mk to soc_sim.mk and soc_top.mk
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2022-02-15 08:31:00 +00:00 |
|
colin
|
1f222dd1e3
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Split soc and verilator to two part system verilog.
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2022-02-14 12:32:21 +00:00 |
|
colin
|
a6038fde4a
|
Set DCCM and ICCM size to 32KB
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2022-02-11 12:17:21 +00:00 |
|
colin
|
547f0dbdc3
|
remove axi4 in demo soc use ahb as default
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2022-02-10 12:17:10 +00:00 |
|
colin
|
3370d01917
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Add verilator install method in readme.
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2022-02-07 08:13:16 +00:00 |
|
colin
|
853d12f17c
|
Init to abstract accelerator project
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2022-02-02 03:34:37 +00:00 |