Joseph Rahmeh
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ec254f5491
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Version 1.9.
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2021-01-27 09:36:43 -08:00 |
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Joseph Rahmeh
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5e613582c2
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New branch: branch1.8
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2020-09-18 13:34:02 -07:00 |
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Joseph Rahmeh
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b65d4dd8f1
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Version 1.5
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2020-02-19 18:25:04 -08:00 |
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Joseph Rahmeh
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790c48cd0b
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Version 1.5
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2020-02-19 18:24:28 -08:00 |
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Joseph Rahmeh
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3820e84e20
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Move declarations to top of Verilog file to fix fpga compile issues.
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2019-10-15 13:14:36 -07:00 |
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Joseph Rahmeh
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b35d7e9e1b
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Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
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2019-09-04 13:29:39 -07:00 |
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Joseph Rahmeh
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d9bb036633
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Updated hello world message. Updated last compilation time.
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2019-08-13 12:57:04 -07:00 |
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Joseph Rahmeh
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c0f7e509cc
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SweRV 1.1
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2019-06-04 07:57:48 -07:00 |