colin
/
abstractaccelerator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
19 Commits 1 Branch 0 Tags 138 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
Joseph Rahmeh 5990932214 Removed apostrophe from comment. 2019-07-12 06:04:31 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00