colin.liang
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44161e293f
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Reset Readme.
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2023-01-04 22:40:08 +08:00 |
colin
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32fff97ff5
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Update gnu build.
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2022-07-07 12:06:04 +00:00 |
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colin
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bd392cfb7c
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Refine reset vector in Cores-SweRV.
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2022-03-22 23:25:11 +00:00 |
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colin
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388db4a82e
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Delete quasar in Cores-SweRV.
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2022-03-22 23:24:01 +00:00 |
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colin
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beab126fc5
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add quasar fpga.
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2022-03-09 11:16:13 +00:00 |
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colin
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33885bbccb
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Add Bit-Vector install in readme
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2022-03-07 04:08:12 +00:00 |
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colin
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27fade0b6d
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Add EL2 cores implement by Chisel in quaser.
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2022-03-06 04:22:17 +00:00 |
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colin
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0a00e20cfe
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Update riscv gcc version and usage.
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2022-03-06 04:21:41 +00:00 |
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colin
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3da81c5916
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Add install commond in riscv gnu tools.
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2022-03-01 13:22:23 +00:00 |
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colin
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3972a891ca
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Add fpga demo in Cores.
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2022-02-21 07:52:52 +00:00 |
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colin
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3edc87e0ea
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Switch mem bus from ahb to axi.
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2022-02-17 11:35:01 +00:00 |
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colin
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8e190efed0
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Split from soc.mk to soc_sim.mk and soc_top.mk
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2022-02-15 08:31:00 +00:00 |
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colin
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1f222dd1e3
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Split soc and verilator to two part system verilog.
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2022-02-14 12:32:21 +00:00 |
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colin
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a6038fde4a
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Set DCCM and ICCM size to 32KB
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2022-02-11 12:17:21 +00:00 |
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colin
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547f0dbdc3
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remove axi4 in demo soc use ahb as default
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2022-02-10 12:17:10 +00:00 |
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colin
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3370d01917
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Add verilator install method in readme.
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2022-02-07 08:13:16 +00:00 |
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colin
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853d12f17c
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Init to abstract accelerator project
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2022-02-02 03:34:37 +00:00 |