b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
cf4d56c78c
Added basic commit register update trace in exec.log
2019-09-08 11:13:17 -04:00
b35d7e9e1b
Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
2019-09-04 13:29:39 -07:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
412c128fb0
Removed duplicate declaration of finished for Verilator.
2019-06-20 09:50:50 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh
Ajay Nath