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5 Commits

Author SHA1 Message Date
Joseph Rahmeh b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. 2019-09-04 13:29:39 -07:00
Joseph Rahmeh 7ff8d7fb5a Untabified files. 2019-08-13 12:48:48 -07:00
Joseph Rahmeh 1cf98e765d fix synthesis syntax in rvdffe in beh_lib.sv 2019-08-08 07:51:56 -07:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00