74a6bdb50d
Do not use variables before declaration
2021-02-17 17:09:35 +01:00
f3da044f15
Delete testbench/tests/cmark_dccm directory
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This directory is redundant due to the reworking of test flow in release 1.9
2021-02-16 08:56:23 -05:00
5e23462bd0
Update README.md
2021-02-03 13:26:41 -08:00
695883a674
Removed dead code.
2021-02-03 11:08:48 -08:00
0c92ea167b
Version 1.9
2021-02-03 07:07:10 -08:00
ec254f5491
Version 1.9.
2021-01-27 09:36:43 -08:00
bcb5b33726
Merge pull request #82 from chipsalliance/quartus_core_fix
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Only load Vivado TCL files when using Vivado
2021-01-21 17:59:41 -05:00
bb9f9ef37b
Merge pull request #89 from olofk/scan_mode
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Remove unused scan_mode input from dmi_wrapper.
We will be releasing some fixes shortly which will have this change too. Accepting your PR so as not hold up any progress.
2021-01-21 17:58:36 -05:00
bcf505751e
Remove unused scan_mode input from dmi_wrapper
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This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
2021-01-18 10:15:08 +01:00
3918a8d345
Only load Vivado TCL files when using Vivado
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This prevents the vivado-specific TCL file to be loaded when using the synth target with other synthesis tools than vivado
2020-11-24 09:31:52 +01:00
7332edc0ad
Merge pull request #76 from olofk/snapshot_dir2
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Set snapshot dir to a known location in FuseSoC SweRV config generator
2020-09-24 10:26:32 -04:00
0242c9e6d2
Explicitly use python3
2020-09-24 15:24:30 +02:00
801d0f66f6
Set snapshot dir to a known location in FuseSoC SweRV config generator
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The previous fix for the FuseSoC SweRV config generator was not complete
2020-09-24 14:32:08 +02:00
1e8c6e3813
Merge pull request #75 from olofk/snapshot_dir
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Adapt FuseSoC SweRV config generator wrt new snapshot dir
2020-09-22 13:41:35 -04:00
2627ccc82b
Adapt FuseSoC SweRV config generator wrt new snapshot dir
2020-09-22 16:27:04 +02:00
f32b634c16
Updated per issue #70
2020-09-22 09:58:03 -04:00
3c50837a75
Update release-notes.md
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Minor corrections
2020-09-18 18:00:45 -07:00
e63dfe17d8
Updated version in swerv.core
2020-09-18 14:42:34 -07:00
d6024bcc6b
Updated branch number in README file.
2020-09-18 14:08:43 -07:00
d395a96492
Updated branch number in README file.
2020-09-18 14:03:24 -07:00
8caf5f69b0
Added testbench/hex directory.
2020-09-18 13:47:53 -07:00
95e9589446
Updated PRM.
2020-09-18 13:47:21 -07:00
5e613582c2
New branch: branch1.8
2020-09-18 13:34:02 -07:00
499378d0c6
Merge pull request #68 from olofk/fusesoc_v1_7
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Update SweRV version in core description file to 1.7
2020-08-19 12:03:59 -05:00
9e0aeed92e
Update SweRV version in core description file to 1.7
2020-08-19 18:25:32 +02:00
48f01f101e
Update README.md
2020-06-26 15:02:13 -07:00
5f905a0912
Upped version.
2020-06-26 10:24:06 -07:00
ae1b1bccad
Updated PRM.
2020-06-26 09:55:56 -07:00
8065eef677
Branch for version 1.7
2020-06-25 19:59:36 -07:00
0555dd8763
Reverted change related to enum assign as it broke some Verilog tools.
2020-05-27 14:50:39 -07:00
5a004dd2b6
Merge pull request #55 from dawidzim/riviera_fusesoc
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update swerv.core for Riviera-PRO
2020-05-27 10:55:32 -05:00
27507b79a1
Merge pull request #49 from dawidzim/enum_from_diff_type
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fix for assignment to enum variable from expression of different type
2020-05-27 08:38:13 -05:00
23c6ce84dc
update swerv.core for Riviera-PRO
2020-05-26 15:17:59 +02:00
ee7473ee90
SweRV core roadmap white paper
2020-05-20 18:23:44 -07:00
a4cc4368ad
Update RISC-V_SweRV_EH1_PRM.pdf
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Fixed typo in Section 18.3.
2020-05-15 15:22:32 -07:00
977175e264
Add 'V' to to title
2020-05-15 14:21:49 -07:00
0b2ec70608
Update version from 1.5 to 1.6
2020-05-15 14:20:29 -07:00
d2a6fac636
Version 1.6
2020-05-15 13:04:43 -07:00
83d5753bad
Version 1.6
2020-05-15 11:40:52 -07:00
6b1e5ded3a
Version 1.6
2020-05-15 11:28:59 -07:00
21fe37b5e2
Merge pull request #20 from toddstrader/master
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Add Travis CI
2020-04-13 16:03:04 -04:00
cc6285eb3b
remove unnecessary switch from vlog
2020-04-02 16:38:56 +02:00
241ad18e25
fix for assignment to enum variable from expression of different type
2020-04-02 15:48:17 +02:00
26c3bcb78f
Merge pull request #42 from danielmlynek/readme_upd_for_aldec1
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Riviera simulator added to Readme
2020-03-04 11:13:19 -05:00
f2e40ff2c8
Update README.md
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Updated version number to 1.5.1
2020-02-28 14:21:35 -08:00
cbb7080411
Update RISC-V_SweRV_EH1_PRM.pdf
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Minor update
2020-02-28 14:19:14 -08:00
040d2807c9
Fix Riviera -l switch
2020-02-27 09:59:42 +01:00
e1aec7d193
Riviera simulator added to Readme
2020-02-27 09:40:53 +01:00
0dbee1c24c
Merge pull request #30 from danielmlynek/make_for_riviera
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Make for riviera
2020-02-26 19:38:57 -06:00
91ac750284
Update release-notes.md
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Remove from the 1.5 release notes items that were accidentally carried over from a previous release.
2020-02-26 19:27:55 -06:00
Tomasz Gorochowik
Ajay Nath
Thomas Wicki
Joseph Rahmeh
Olof Kindgren
Ajay Nath
jrahmeh
Dawid Zimonczyk
Zvonimir Bandic
Daniel Mlynek