colin
|
3da81c5916
|
Add install commond in riscv gnu tools.
|
2022-03-01 13:22:23 +00:00 |
|
colin
|
e26d5260de
|
start to add ecp5 support,current donet support jlink
Use FT2232H base jtag,and VexRiscv's openocd to support dbg.
|
2022-02-28 03:34:59 +00:00 |
|
colin
|
2c4658ddb9
|
Refine murax sim config file
|
2022-02-28 03:33:41 +00:00 |
|
colin
|
28d08fc3ad
|
Refine Readme of install openocd.
|
2022-02-28 03:33:08 +00:00 |
|
colin
|
e0f77ceead
|
Add configuration to flash by ecpdap.
|
2022-02-27 15:39:45 +00:00 |
|
colin
|
94c99367ba
|
remove gen file in fpga
|
2022-02-27 04:49:27 +00:00 |
|
colin
|
1d1237c223
|
Add VexRiscv fpga generation to ecp5.
|
2022-02-26 15:14:43 +00:00 |
|
colin
|
25a557365b
|
Enable VexRiscv murax jtag simulator by verilator.
|
2022-02-26 14:34:25 +00:00 |
|
colin
|
e3968e6fa7
|
Refine opene906 gdb sample.
|
2022-02-25 12:24:03 +00:00 |
|
colin
|
65545d5e03
|
Add VexRiscv.
|
2022-02-25 11:56:36 +00:00 |
|
colin
|
ccc993e003
|
Refine gdb sample code
|
2022-02-24 06:04:58 +00:00 |
|
colin
|
3258c057e3
|
Enable demo openocd and gdb.
|
2022-02-24 03:18:07 +00:00 |
|
colin
|
1d7ba86749
|
Add dome on opene906
|
2022-02-22 06:44:45 +00:00 |
|
colin
|
0d940ba004
|
Add opene906
|
2022-02-21 10:41:54 +00:00 |
|
colin
|
51730ed20d
|
Add xilinx readme.
|
2022-02-21 07:53:02 +00:00 |
|
colin
|
3972a891ca
|
Add fpga demo in Cores.
|
2022-02-21 07:52:52 +00:00 |
|
colin
|
3edc87e0ea
|
Switch mem bus from ahb to axi.
|
2022-02-17 11:35:01 +00:00 |
|
colin
|
cffec82632
|
Add clean before fpga ram make all
|
2022-02-17 06:21:42 +00:00 |
|
colin
|
8e190efed0
|
Split from soc.mk to soc_sim.mk and soc_top.mk
|
2022-02-15 08:31:00 +00:00 |
|
colin
|
1f222dd1e3
|
Split soc and verilator to two part system verilog.
|
2022-02-14 12:32:21 +00:00 |
|
colin
|
a6038fde4a
|
Set DCCM and ICCM size to 32KB
|
2022-02-11 12:17:21 +00:00 |
|
colin
|
547f0dbdc3
|
remove axi4 in demo soc use ahb as default
|
2022-02-10 12:17:10 +00:00 |
|
colin
|
18c8352c09
|
Add ram test and verilator in fpga DEMO.
|
2022-02-09 12:47:35 +00:00 |
|
colin
|
3c3cfccfd5
|
add ram test.
|
2022-02-08 03:00:40 +00:00 |
|
colin
|
a7ef641f0d
|
Refine io level
|
2022-02-07 13:34:50 +00:00 |
|
colin
|
3405c88c9e
|
Correct blink and use sample blink code
|
2022-02-07 13:23:34 +00:00 |
|
colin
|
3370d01917
|
Add verilator install method in readme.
|
2022-02-07 08:13:16 +00:00 |
|
colin
|
3ba8533996
|
Add fpga
|
2022-02-02 03:43:53 +00:00 |
|
colin
|
a15c797e93
|
add jtag to ESP32
|
2022-02-02 03:40:41 +00:00 |
|
colin
|
853d12f17c
|
Init to abstract accelerator project
|
2022-02-02 03:34:37 +00:00 |
|
colin
|
f299211d91
|
Refine readme for rocket tool build
|
2022-02-01 15:50:30 +00:00 |
|
Colin
|
d8c2a6861b
|
refine Readme for demo
|
2022-01-27 16:42:31 +08:00 |
 Colin
|
3ed8011eaa
|
add jtag demo for GDB which openocd
|
2022-01-22 08:08:47 +00:00 |
|
Colin
|
5f80832b1a
|
add jtag demo and refine Makefile
|
2022-01-20 03:44:59 +00:00 |
|
Colin
|
a8fc3642ad
|
Add dpi of jtag
|
2022-01-19 12:45:38 +00:00 |
|
Colin
|
65f5085afa
|
refine makefile
|
2022-01-19 09:57:37 +00:00 |
|
Colin
|
9174bfe249
|
mv flist to soc folder
|
2022-01-17 12:18:33 +00:00 |
|
Colin
|
1437f0fcf3
|
move swerv config and json to soc
|
2022-01-17 12:14:05 +00:00 |
|
Colin
|
7aff1ae5f1
|
add soc for common test with soc.
|
2022-01-17 11:53:50 +00:00 |
|
Colin
|
3be1146718
|
refine define file build
|
2022-01-17 11:40:11 +00:00 |
|
Colin
|
1d8069026b
|
remove no use file in demo
|
2022-01-17 11:10:22 +00:00 |
|
Colin
|
2b298f0fff
|
rename test to demo
|
2022-01-17 06:43:14 +00:00 |
|
Colin
|
0eb74fdc10
|
refine test use function
|
2022-01-05 03:47:27 +00:00 |
|
Colin
|
6567357739
|
add llvm build flow from .c file
|
2022-01-04 12:39:14 +00:00 |
|
Colin
|
be63e84a1d
|
Add build from llvm
|
2021-12-17 13:29:59 +00:00 |
|
Colin
|
911f65874f
|
add test of verilator in one folder
|
2021-12-16 12:08:59 +00:00 |
Ajay Nath
|
87c23b9952
|
Merge pull request #101 from antmicro/fix-vivado-tcl
Remove not existing file from vivado.tcl
|
2021-10-08 17:45:03 -04:00 |
Kamil Rakoczy
|
f57cce19ff
|
Remove not existing file from vivado.tcl
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
|
2021-08-27 15:27:02 +02:00 |
Ajay Nath
|
81bff1c0d7
|
reverting to 0242c9e for swerv_config_gen.py
|
2021-03-12 08:02:57 -05:00 |
|
Ajay Nath
|
d4e7b25f71
|
Merge pull request #93 from antmicro/variable-order-fix
Declare variables before using them
Thank you for this update.
|
2021-02-19 15:03:43 -05:00 |