8065eef677
Branch for version 1.7
2020-06-25 19:59:36 -07:00
6b1e5ded3a
Version 1.6
2020-05-15 11:28:59 -07:00
b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
4e161e6c3b
Minor cleanup in config script.
2019-08-13 15:47:53 -07:00
ac92841999
Adjust CSR MFDC reset value for the AXI bus.
2019-08-13 12:38:50 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh