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3 Commits

Author SHA1 Message Date
Joseph Rahmeh ac92841999 Adjust CSR MFDC reset value for the AXI bus. 2019-08-13 12:38:50 -07:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00