8065eef677
Branch for version 1.7
2020-06-25 19:59:36 -07:00
0555dd8763
Reverted change related to enum assign as it broke some Verilog tools.
2020-05-27 14:50:39 -07:00
241ad18e25
fix for assignment to enum variable from expression of different type
2020-04-02 15:48:17 +02:00
b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
5990932214
Removed apostrophe from comment.
2019-07-12 06:04:31 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh
Dawid Zimonczyk