Commit Graph

20 Commits

Author SHA1 Message Date
Joseph Rahmeh 5e613582c2 New branch: branch1.8 2020-09-18 13:34:02 -07:00
Joseph Rahmeh 8065eef677 Branch for version 1.7 2020-06-25 19:59:36 -07:00
Joseph Rahmeh 6b1e5ded3a Version 1.6 2020-05-15 11:28:59 -07:00
Daniel Mlynek e1aec7d193 Riviera simulator added to Readme 2020-02-27 09:40:53 +01:00
Joseph Rahmeh b65d4dd8f1 Version 1.5 2020-02-19 18:25:04 -08:00
Joseph Rahmeh a44ef01adf Changed version to 1.5. 2020-02-18 13:41:42 -08:00
Arup De c89f6b7511
Update README.md 2019-11-20 11:02:15 -08:00
Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues. 2019-10-15 13:14:36 -07:00
aprnath 5fce5b0a26
Update README.md 2019-09-08 11:15:25 -04:00
Joseph Rahmeh b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. 2019-09-04 13:29:39 -07:00
jrahmeh 8242950a58
Fixed branch numbers 2019-08-13 15:30:00 -05:00
Joseph Rahmeh e20f012de7 Removed refernce to version 1.1. 2019-08-10 13:42:48 -07:00
Joseph Rahmeh 40db638de6 Mention 1.1.1 release. 2019-08-10 13:23:53 -07:00
jrahmeh bc367eaf3a
Update README.md
Added description of "espresso".
2019-07-20 08:28:44 -05:00
jrahmeh 48dc8668cb
Update README.md 2019-06-09 19:50:35 -05:00
jrahmeh 166274de5e
Update README.md
Added reference to version 1.0.
2019-06-06 11:32:35 -05:00
Joseph Rahmeh de6978de5d SweRV 1.1 2019-06-04 07:58:40 -07:00
Zvonimir Bandic 6ccfce0957
Update README.md 2019-06-01 23:45:59 -07:00
Zvonimir Bandic 1abeb9a380
Update README.md 2019-06-01 23:44:30 -07:00
Zvonimir Bandic 763cd3d38a
Create README.md 2019-06-01 23:43:28 -07:00