Joseph Rahmeh
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5e613582c2
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New branch: branch1.8
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2020-09-18 13:34:02 -07:00 |
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Joseph Rahmeh
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8065eef677
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Branch for version 1.7
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2020-06-25 19:59:36 -07:00 |
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Joseph Rahmeh
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6b1e5ded3a
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Version 1.6
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2020-05-15 11:28:59 -07:00 |
Daniel Mlynek
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e1aec7d193
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Riviera simulator added to Readme
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2020-02-27 09:40:53 +01:00 |
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Joseph Rahmeh
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b65d4dd8f1
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Version 1.5
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2020-02-19 18:25:04 -08:00 |
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Joseph Rahmeh
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a44ef01adf
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Changed version to 1.5.
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2020-02-18 13:41:42 -08:00 |
Arup De
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c89f6b7511
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Update README.md
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2019-11-20 11:02:15 -08:00 |
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Joseph Rahmeh
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3820e84e20
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Move declarations to top of Verilog file to fix fpga compile issues.
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2019-10-15 13:14:36 -07:00 |
aprnath
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5fce5b0a26
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Update README.md
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2019-09-08 11:15:25 -04:00 |
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Joseph Rahmeh
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b35d7e9e1b
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Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
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2019-09-04 13:29:39 -07:00 |
jrahmeh
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8242950a58
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Fixed branch numbers
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2019-08-13 15:30:00 -05:00 |
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Joseph Rahmeh
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e20f012de7
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Removed refernce to version 1.1.
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2019-08-10 13:42:48 -07:00 |
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Joseph Rahmeh
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40db638de6
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Mention 1.1.1 release.
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2019-08-10 13:23:53 -07:00 |
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jrahmeh
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bc367eaf3a
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Update README.md
Added description of "espresso".
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2019-07-20 08:28:44 -05:00 |
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jrahmeh
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48dc8668cb
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Update README.md
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2019-06-09 19:50:35 -05:00 |
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jrahmeh
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166274de5e
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Update README.md
Added reference to version 1.0.
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2019-06-06 11:32:35 -05:00 |
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Joseph Rahmeh
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de6978de5d
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SweRV 1.1
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2019-06-04 07:58:40 -07:00 |
Zvonimir Bandic
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6ccfce0957
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Update README.md
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2019-06-01 23:45:59 -07:00 |
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Zvonimir Bandic
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1abeb9a380
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Update README.md
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2019-06-01 23:44:30 -07:00 |
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Zvonimir Bandic
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763cd3d38a
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Create README.md
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2019-06-01 23:43:28 -07:00 |