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Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 		2019-08-07 17:04:48 -07:00
..
snapshots/default SweRV 1.1 2019-06-04 07:57:48 -07:00
README.md SweRV 1.1 2019-06-04 07:57:48 -07:00
swerv.config Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00

README.md

SweRV RISC-V core from Western Digital

Configuration

Contents

Name Description
swerv.config Configuration script for SweRV

This script will generate a consistent st of `defines/#defines needed for the design and testbench.
A perl hash (perl_configs.pl) and a JSON format for SweRV-iss are also generated.

While the defines fines may be modified by hand, it is recommended that this script be used to generate a consistent set.