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colin 2c4658ddb9 Refine murax sim config file		2022-02-28 03:33:41 +00:00
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common	Enable VexRiscv murax jtag simulator by verilator.	2022-02-26 14:34:25 +00:00
fpga	remove gen file in fpga	2022-02-27 04:49:27 +00:00
sim	Refine murax sim config file	2022-02-28 03:33:41 +00:00
Murax.v	Add VexRiscv fpga generation to ecp5.	2022-02-26 15:14:43 +00:00
Readme.md	Enable VexRiscv murax jtag simulator by verilator.	2022-02-26 14:34:25 +00:00

Readme.md

VexRiscV

install special OpenOCD to support VexRiscV

https://github.com/SpinalHDL/openocd_riscv.git

sudo apt-get install libtool automake libusb-1.0.0-dev texinfo libusb-dev libyaml-dev pkg-config

./bootstrap
./configure --enable-ftdi --enable-dummy --enable-cmsis-dap --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
make -j
sudo make install

install sbt to gen the VexRiscv core

# JAVA JDK 8
sudo add-apt-repository -y ppa:openjdk-r/ppa
sudo apt-get update
sudo apt-get install openjdk-8-jdk -y
sudo update-alternatives --config java
sudo update-alternatives --config javac

# Install SBT - https://www.scala-sbt.org/
echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
sudo apt-get update
sudo apt-get install sbt

VexRiscv

# To generate the SoC without any content in the ram
sbt "runMain vexriscv.demo.Murax"

# To generate the SoC with a demo program already in ram
sbt "runMain vexriscv.demo.MuraxWithRamInit"