67148 lines
1.6 MiB
67148 lines
1.6 MiB
.device LFE5U-25F
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.comment Part: LFE5U-25F-6CABGA381
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.tile CIB_R19C1:CIB_LR
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arc: S3_V06S0103 E3_H06W0103
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.tile CIB_R20C1:CIB_LR
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arc: S3_V06S0103 H06W0103
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.tile CIB_R22C1:CIB_LR
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arc: E3_H06E0003 S3_V06N0003
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.tile CIB_R23C1:CIB_LR
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arc: E1_H02E0101 S1_V02N0101
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arc: E1_H02E0601 E1_H01W0000
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.tile CIB_R24C1:CIB_LR
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arc: E1_H02E0101 V02N0101
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.tile CIB_R25C10:CIB_EBR
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arc: E1_H02E0001 V06N0003
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arc: E1_H02E0201 S3_V06N0103
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arc: E1_H02E0301 W1_H02E0201
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arc: E1_H02E0501 N1_V02S0501
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arc: E1_H02E0701 V06N0203
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arc: H00L0000 N1_V02S0001
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arc: H00L0100 W1_H02E0301
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arc: H00R0100 S1_V02N0701
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arc: JA0 S1_V02N0701
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arc: JA1 V02N0701
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arc: JA2 V00B0000
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arc: JA3 V00T0000
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arc: JA4 V00T0100
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arc: JA5 V02S0301
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arc: JC0 H00R0100
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arc: JC1 H02W0601
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arc: JC2 H00L0000
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arc: JC3 H00L0100
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arc: JC4 S1_V02N0001
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arc: JC5 V02S0001
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arc: JCE1 V02N0201
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arc: JCLK0 G_HPBX0100
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arc: JD6 V02S0601
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arc: JD7 V02N0601
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arc: N1_V02N0301 E1_H02W0301
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arc: N1_V02N0601 E1_H02W0601
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arc: N1_V02N0701 H06E0203
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arc: N3_V06N0003 S1_V02N0301
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arc: S1_V02S0001 E1_H01W0000
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arc: S1_V02S0401 JQ6
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arc: S1_V02S0501 H06W0303
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arc: S1_V02S0601 H06W0303
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arc: S1_V02S0701 JQ7
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arc: S3_V06S0303 E1_H01W0100
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arc: V00B0000 N1_V02S0001
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arc: V00T0000 W1_H02E0001
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arc: V00T0100 S1_V02N0501
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arc: W1_H02W0001 S3_V06N0003
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arc: W1_H02W0201 S1_V02N0201
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arc: W1_H02W0401 S1_V02N0401
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enum: CIB.JB5MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JLSR1MUX 0
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JD5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JB7MUX 0
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enum: CIB.JB6MUX 0
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.tile CIB_R25C11:CIB_EBR
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arc: E1_H02E0401 N1_V02S0401
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arc: E1_H02E0501 V06N0303
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arc: H00L0100 W1_H02E0301
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arc: H00R0000 S1_V02N0401
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arc: H01W0000 JQ3
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arc: H01W0100 JQ5
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arc: JA0 H02E0501
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arc: JA1 H02E0501
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arc: JA2 V00B0000
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arc: JA3 V00B0000
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arc: JA6 H00R0000
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arc: JA7 H00R0000
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arc: JB1 V02S0101
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arc: JB3 S1_V02N0101
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arc: JB5 H02E0301
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arc: JC0 H00L0100
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arc: JC1 H00L0100
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arc: JC2 V02S0401
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arc: JC3 V02S0401
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arc: JCLK0 G_HPBX0100
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arc: JD0 S1_V02N0201
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arc: JD2 H02E0201
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arc: JD4 H02E0001
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arc: JLSR1 V00T0000
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arc: N1_V02N0601 S1_V02N0301
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arc: S1_V02S0101 N1_V02S0101
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arc: S1_V02S0201 JQ0
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arc: S1_V02S0601 W1_H02E0601
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arc: S3_V06S0103 JQ2
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arc: S3_V06S0203 JQ4
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arc: V00B0000 V02N0201
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arc: V00T0000 W1_H02E0201
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arc: V01S0000 JQ1
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arc: W1_H02W0301 V02N0301
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arc: W1_H02W0601 V06N0303
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arc: W1_H02W0701 E1_H02W0601
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arc: N1_V02N0301 W3_H06E0003
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arc: S1_V02S0301 W3_H06E0003
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arc: E3_H06E0003 W3_H06E0003
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JB7MUX 0
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enum: CIB.JCE1MUX 1
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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.tile CIB_R25C12:CIB_EBR
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arc: H00L0000 V02S0201
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arc: JA0 H00L0000
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arc: JA1 H00L0000
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arc: JA4 H02E0501
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arc: JA5 H02E0501
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arc: JA6 W1_H02E0701
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arc: JA7 W1_H02E0701
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arc: JC0 S1_V02N0601
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arc: JC1 S1_V02N0601
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arc: JC4 V00T0100
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arc: JC5 V00T0100
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arc: JC6 H02E0401
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arc: JC7 H02E0401
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arc: JCE1 S1_V02N0201
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arc: JCLK0 G_HPBX0100
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arc: N1_V02N0001 S1_V02N0001
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arc: N1_V02N0301 H02W0301
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arc: N1_V02N0601 S1_V02N0301
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arc: N1_V02N0701 H02W0701
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arc: S3_V06S0103 N1_V01S0100
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arc: V00T0100 S1_V02N0501
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arc: W1_H02W0301 V06N0003
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arc: W1_H02W0601 V06N0303
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JLSR1MUX 0
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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.tile CIB_R25C13:CIB_EBR
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arc: E1_H02E0001 V06N0003
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arc: E1_H02E0601 V06S0303
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arc: N1_V02N0001 V01N0001
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arc: N1_V02N0101 E1_H02W0101
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arc: N1_V02N0301 E1_H02W0301
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arc: N1_V02N0701 E1_H02W0701
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arc: S1_V02S0101 N1_V02S0001
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arc: S1_V02S0401 N1_V02S0101
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arc: S3_V06S0203 N3_V06S0103
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arc: V01S0000 N3_V06S0103
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arc: V01S0100 S3_V06N0303
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arc: W1_H02W0301 V06S0003
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arc: W1_H02W0601 S3_V06N0303
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arc: W1_H02W0701 V06N0203
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arc: W3_H06W0303 S3_V06N0303
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arc: E3_H06E0103 W3_H06E0103
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.tile CIB_R25C14:CIB_EBR
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arc: N1_V02N0001 S1_V02N0501
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0601 H02E0601
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arc: S1_V02S0401 N1_V02S0401
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arc: S3_V06S0103 N1_V02S0101
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.tile CIB_R25C15:CIB_EBR
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arc: E1_H02E0101 V01N0101
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arc: E3_H06E0103 N1_V01S0100
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arc: N1_V02N0001 W1_H02E0001
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arc: N1_V02N0101 H02W0101
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arc: N1_V02N0301 V01N0101
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arc: N1_V02N0401 H02W0401
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arc: N1_V02N0601 S1_V02N0301
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arc: N1_V02N0701 H02W0701
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arc: S1_V02S0101 N1_V02S0101
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arc: S1_V02S0401 N1_V02S0101
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arc: S1_V02S0601 N1_V02S0301
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arc: W1_H02W0101 V01N0101
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arc: W1_H02W0301 V01N0101
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arc: E1_H02E0301 W3_H06E0003
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arc: E1_H02E0701 W3_H06E0203
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arc: W1_H02W0701 W3_H06E0203
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arc: E3_H06E0003 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0203
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arc: E3_H06E0303 W3_H06E0303
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.tile CIB_R25C16:CIB_EBR
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arc: N1_V02N0101 H02W0101
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arc: N1_V02N0301 H02E0301
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arc: N1_V02N0601 S1_V02N0301
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arc: N1_V02N0701 H02E0701
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arc: N3_V06N0203 S3_V06N0203
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arc: S1_V02S0101 H02W0101
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arc: S1_V02S0301 S3_V06N0003
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arc: S3_V06S0103 N3_V06S0103
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arc: W1_H02W0101 S1_V02N0101
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arc: W1_H02W0401 S1_V02N0401
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arc: W1_H02W0701 S3_V06N0203
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.tile CIB_R25C17:CIB_EBR
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arc: N1_V02N0101 W1_H02E0101
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arc: N1_V02N0201 S3_V06N0103
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arc: N1_V02N0401 S1_V02N0401
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arc: N1_V02N0501 S1_V02N0501
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arc: N1_V02N0701 S1_V02N0701
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arc: S1_V02S0001 N1_V02S0001
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arc: S1_V02S0101 E1_H02W0101
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arc: W1_H02W0101 E1_H02W0101
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arc: N1_V02N0301 W3_H06E0003
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.tile CIB_R25C18:CIB_EBR
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arc: N1_V02N0401 S1_V02N0401
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arc: N1_V02N0501 S3_V06N0303
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arc: N1_V02N0701 H06E0203
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arc: S1_V02S0401 H06W0203
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arc: S3_V06S0003 H06E0003
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.tile CIB_R25C19:CIB_EBR
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arc: S1_V02S0001 E1_H02W0001
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arc: S1_V02S0401 N1_V01S0000
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arc: W1_H02W0101 S1_V02N0101
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arc: N1_V02N0201 W3_H06E0103
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.tile CIB_R25C1:CIB_LR_S
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arc: E1_H02E0001 E3_H06W0003
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arc: E1_H02E0101 E3_H06W0103
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arc: E1_H02E0201 N3_V06S0103
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arc: E1_H02E0601 E3_H06W0303
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arc: N1_V02N0101 N3_V06S0103
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arc: V01S0100 S3_V06N0303
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.tile CIB_R25C20:CIB_EBR
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arc: N1_V02N0101 S1_V02N0001
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arc: N1_V02N0601 H02W0601
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.tile CIB_R25C21:CIB_EBR
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arc: E1_H02E0501 V06S0303
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arc: N1_V02N0301 S1_V02N0201
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arc: N1_V02N0501 N1_V01S0100
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arc: N1_V02N0601 S1_V02N0301
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arc: S1_V02S0201 N1_V02S0201
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arc: S1_V02S0501 S3_V06N0303
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arc: V01S0100 S3_V06N0303
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arc: W1_H02W0001 V01N0001
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arc: W1_H02W0601 V06N0303
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arc: N1_V02N0001 W3_H06E0003
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arc: N1_V02N0201 W3_H06E0103
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arc: N1_V02N0401 W3_H06E0203
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arc: N1_V02N0701 W3_H06E0203
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arc: S1_V02S0301 W3_H06E0003
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arc: S1_V02S0401 W3_H06E0203
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arc: S1_V02S0601 W3_H06E0303
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0203 W3_H06E0203
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arc: W3_H06W0203 V01N0001
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.tile CIB_R25C22:CIB_EBR
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arc: E1_H02E0001 N3_V06S0003
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arc: E1_H02E0301 N3_V06S0003
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arc: N1_V01N0001 N3_V06S0003
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arc: N1_V02N0001 N3_V06S0003
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arc: N1_V02N0101 S1_V02N0001
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arc: N1_V02N0301 N3_V06S0003
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arc: S1_V02S0501 H02E0501
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arc: S1_V02S0601 N1_V02S0601
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arc: V01S0100 S3_V06N0303
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.tile CIB_R25C23:CIB_EBR
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arc: N1_V02N0101 S1_V02N0101
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arc: N1_V02N0201 V01N0001
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arc: S1_V02S0101 N1_V02S0101
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.tile CIB_R25C24:CIB_EBR
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arc: N1_V02N0101 S3_V06N0103
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0203 S3_V06N0203
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arc: S1_V02S0001 W1_H02E0001
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arc: S1_V02S0301 W1_H02E0301
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.tile CIB_R25C2:CIB_EBR
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arc: N1_V02N0201 H02E0201
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arc: S1_V02S0001 N1_V02S0001
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arc: S1_V02S0401 E1_H02W0401
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arc: S1_V02S0501 E1_H02W0501
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arc: S1_V02S0601 E3_H06W0303
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arc: S1_V02S0701 E3_H06W0203
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.tile CIB_R25C3:CIB_EBR
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arc: E1_H02E0301 V02S0301
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arc: E1_H02E0501 E3_H06W0303
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arc: E1_H02E0601 S1_V02N0601
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arc: E3_H06E0303 V06S0303
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arc: N1_V02N0001 W1_H02E0001
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arc: N1_V02N0201 V01N0001
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arc: N1_V02N0301 S1_V02N0301
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arc: N1_V02N0401 H06W0203
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arc: N1_V02N0501 S1_V02N0401
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arc: N1_V02N0601 E1_H01W0000
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arc: S1_V02S0101 W1_H02E0101
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arc: S1_V02S0301 E1_H01W0100
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arc: S1_V02S0401 N1_V01S0000
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arc: S1_V02S0601 W1_H02E0601
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 E3_H06W0103
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arc: V01S0100 S3_V06N0303
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.tile CIB_R25C4:CIB_EBR
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arc: E1_H02E0201 S1_V02N0201
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arc: E1_H02E0301 JQ1
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arc: E1_H02E0601 S1_V02N0601
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arc: E1_H02E0701 N1_V01S0100
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arc: H00L0100 S1_V02N0101
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arc: H00R0100 V02S0701
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arc: H01W0000 JQ7
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arc: H01W0100 JQ3
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arc: JA0 V02S0501
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arc: JA1 V02S0501
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arc: JA2 V00B0000
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arc: JA3 V00B0000
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arc: JA6 S1_V02N0301
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arc: JA7 N1_V02S0101
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arc: JB1 V00T0000
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arc: JB3 V02N0101
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arc: JB5 H02E0301
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arc: JB7 H02W0101
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arc: JC0 E1_H02W0601
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arc: JC1 E1_H02W0601
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arc: JC2 H00R0100
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arc: JC3 H00R0100
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arc: JCLK0 G_HPBX0100
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arc: JD0 N1_V02S0201
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arc: JD2 E1_H02W0001
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arc: JD4 H00L0100
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arc: JD6 V02N0401
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arc: JLSR1 H02E0501
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arc: N1_V02N0201 V01N0001
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arc: N1_V02N0401 JQ4
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arc: N1_V02N0501 H06W0303
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arc: S1_V02S0001 JQ2
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arc: S1_V02S0501 H06W0303
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arc: S1_V02S0601 H06W0303
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arc: S1_V02S0701 H06W0203
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0203 N3_V06S0103
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arc: V00B0000 V02N0201
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arc: V00T0000 S1_V02N0401
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|
arc: W1_H02W0401 JQ6
|
|
arc: W1_H02W0501 JQ5
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R25C5:CIB_EBR
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: JA0 V02N0501
|
|
arc: JA1 H00R0000
|
|
arc: JA4 V02N0101
|
|
arc: JA5 V00B0000
|
|
arc: JA6 V02N0301
|
|
arc: JA7 S1_V02N0101
|
|
arc: JC0 H00L0000
|
|
arc: JC1 W1_H02E0601
|
|
arc: JC4 W1_H02E0601
|
|
arc: JC5 H02E0601
|
|
arc: JC6 H02E0601
|
|
arc: JC7 S1_V02N0001
|
|
arc: JCE1 H00R0100
|
|
arc: JCLK0 G_HPBX0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JLSR1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R25C6:CIB_EBR
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0000 JQ5
|
|
arc: JA0 W1_H02E0701
|
|
arc: JA1 W1_H02E0701
|
|
arc: JA2 V00T0000
|
|
arc: JA3 V00T0000
|
|
arc: JA6 H00L0000
|
|
arc: JA7 H00L0000
|
|
arc: JB3 H00R0000
|
|
arc: JB5 V02N0701
|
|
arc: JB7 V02N0501
|
|
arc: JC0 S1_V02N0601
|
|
arc: JC1 S1_V02N0601
|
|
arc: JC2 H00R0100
|
|
arc: JC3 H00R0100
|
|
arc: JCLK0 G_HPBX0100
|
|
arc: JD2 V00B0100
|
|
arc: JD4 V02N0601
|
|
arc: JD6 V02N0401
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0203 JQ4
|
|
arc: S3_V06S0303 JQ6
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 JQ7
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R25C7:CIB_EBR
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: JA0 H00R0000
|
|
arc: JA1 H00R0000
|
|
arc: JA4 W1_H02E0501
|
|
arc: JA5 W1_H02E0501
|
|
arc: JA6 H00L0000
|
|
arc: JA7 H00L0000
|
|
arc: JB1 H00R0100
|
|
arc: JC0 W1_H02E0601
|
|
arc: JC1 W1_H02E0601
|
|
arc: JC4 V00T0100
|
|
arc: JC5 V00T0100
|
|
arc: JC6 H02E0601
|
|
arc: JC7 H02E0601
|
|
arc: JCE1 S1_V02N0201
|
|
arc: JCLK0 G_HPBX0100
|
|
arc: JD0 H02E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 JQ0
|
|
arc: W1_H02W0301 JQ1
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JLSR1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
|
|
.tile CIB_R25C8:CIB_EBR
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H01W0000 JQ5
|
|
arc: H01W0100 JQ4
|
|
arc: JB5 V02N0501
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD4 V02N0601
|
|
arc: JD6 V00B0000
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W3_H06W0203 JQ7
|
|
arc: W3_H06W0303 JQ6
|
|
enum: CIB.JLSR1MUX 0
|
|
enum: CIB.JCLK1MUX 0
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCLK0MUX 0
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R25C9:CIB_EBR
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: H01W0000 JQ2
|
|
arc: H01W0100 JQ0
|
|
arc: JA0 S1_V02N0501
|
|
arc: JA1 S1_V02N0501
|
|
arc: JA2 V00T0000
|
|
arc: JA3 V00T0000
|
|
arc: JA6 S1_V02N0101
|
|
arc: JA7 S1_V02N0101
|
|
arc: JB1 H00R0100
|
|
arc: JB3 V02S0301
|
|
arc: JC0 H02E0401
|
|
arc: JC1 H02E0401
|
|
arc: JC2 V02S0401
|
|
arc: JC3 V02S0401
|
|
arc: JCLK0 G_HPBX0100
|
|
arc: JD0 H02W0201
|
|
arc: JD2 V00B0100
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: W3_H06W0103 JQ1
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R26C1:CIB_LR
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile CIB_R27C1:CIB_LR
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
|
|
.tile CIB_R28C1:CIB_LR
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: JD7 S1_V02N0601
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile CIB_R30C1:CIB_LR
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0501 V02N0501
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile CIB_R32C1:CIB_LR
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile CIB_R34C1:CIB_LR
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile CIB_R36C1:CIB_LR
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
|
|
.tile CIB_R37C10:CIB_EBR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile CIB_R37C11:CIB_EBR
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
|
|
.tile CIB_R37C12:CIB_EBR
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile CIB_R37C13:CIB_EBR
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile CIB_R37C14:CIB_EBR
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
|
|
.tile CIB_R37C15:CIB_EBR
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
|
|
.tile CIB_R37C16:CIB_EBR
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
|
|
.tile CIB_R37C17:CIB_EBR
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: W3_H06W0103 V06S0103
|
|
|
|
.tile CIB_R37C18:CIB_EBR
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
|
|
.tile CIB_R37C19:CIB_EBR
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
|
|
.tile CIB_R37C1:CIB_LR_S
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0701 V01N0101
|
|
|
|
.tile CIB_R37C20:CIB_EBR
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0301 H02W0301
|
|
|
|
.tile CIB_R37C21:CIB_EBR
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W1_H02W0301 V06S0003
|
|
|
|
.tile CIB_R37C22:CIB_EBR
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile CIB_R37C23:CIB_EBR
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile CIB_R37C24:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R37C2:CIB_EBR
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: N1_V02N0301 H02W0301
|
|
|
|
.tile CIB_R37C3:CIB_EBR
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile CIB_R37C4:CIB_EBR
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
|
|
.tile CIB_R37C5:CIB_EBR
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: W1_H02W0201 V06S0103
|
|
|
|
.tile CIB_R37C6:CIB_EBR
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
|
|
.tile CIB_R37C7:CIB_EBR
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile CIB_R37C8:CIB_EBR
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile CIB_R37C9:CIB_EBR
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R38C1:CIB_LR
|
|
arc: JA0 V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R39C1:CIB_LR
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
|
|
.tile CIB_R40C1:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R41C1:CIB_LR
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: JA0 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R43C1:CIB_LR
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R44C1:CIB_LR
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: N1_V01N0001 JF5
|
|
|
|
.tile CIB_R45C1:CIB_LR
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile CIB_R47C1:CIB_LR
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
|
|
.tile CIB_R49C13:CIB
|
|
arc: E1_H01E0101 JQ0
|
|
|
|
.tile CIB_R49C14:CIB
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile CIB_R49C18:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: N3_V06N0003 JQ0
|
|
|
|
.tile CIB_R49C1:CIB_LR_S
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R49C20:CIB
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R49C24:CIB
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R49C25:CIB
|
|
arc: JD7 E1_H01W0100
|
|
|
|
.tile CIB_R49C26:CIB
|
|
arc: H01W0100 W3_H06E0303
|
|
|
|
.tile CIB_R49C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R49C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R49C69:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R49C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R49C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile MIB_R13C21:DSP_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
arc: G_VPTX0100 G_HPRX0100
|
|
|
|
.tile MIB_R13C31:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFN0000
|
|
arc: G_ULPCLK1 G_HPFE0000
|
|
|
|
.tile MIB_R13C32:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFN0000
|
|
arc: G_URPCLK1 G_HPFE0000
|
|
|
|
.tile MIB_R13C3:DSP_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
arc: G_VPTX0100 G_HPRX0100
|
|
unknown: F2B0
|
|
unknown: F3B0
|
|
unknown: F5B0
|
|
unknown: F11B0
|
|
unknown: F13B0
|
|
|
|
.tile MIB_R25C3:LMID_0
|
|
arc: G_LDCC0CLKI G_JLLQPCLKCIB0
|
|
|
|
.tile MIB_R37C21:EBR_SPINE_LL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
arc: G_VPTX0100 G_HPRX0100
|
|
|
|
.tile MIB_R37C31:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFN0000
|
|
arc: G_LLPCLK1 G_HPFE0000
|
|
|
|
.tile MIB_R37C32:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFN0000
|
|
arc: G_LRPCLK1 G_HPFE0000
|
|
|
|
.tile MIB_R37C3:EBR_SPINE_LL3
|
|
arc: G_VPTX0100 G_HPRX0100
|
|
|
|
.tile MIB_R38C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R40C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R42C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R44C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R45C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R48C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R49C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R50C13:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R50C18:SPICB0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R50C1:BANKREF6
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R50C31:BMID_0V
|
|
arc: G_BDCC0CLKI G_JBLQPCLKCIB0
|
|
|
|
.tile MIB_R50C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile R15C13:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: V00B0000 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R15C14:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q2
|
|
arc: M0 H01E0001
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R15C15:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R16C10:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 H02W0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q2
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00B0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R16C11:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q0
|
|
arc: H01W0000 Q2
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R16C12:PLC2
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00T0000 H02E0001
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R16C13:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 V02N0601
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R16C14:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
|
|
.tile R16C15:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00B0000 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q6
|
|
arc: M0 H02E0601
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R16C9:PLC2
|
|
arc: V00B0000 V02N0201
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q6
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C10:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R17C11:PLC2
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
|
|
.tile R17C12:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C13:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R17C14:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R17C15:PLC2
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C17:PLC2
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R17C19:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
|
|
.tile R17C20:PLC2
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: LSR0 H02E0501
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R17C21:PLC2
|
|
arc: V00T0000 H02E0001
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0601 Q4
|
|
arc: LSR0 W1_H02E0501
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M2 H02W0601
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0001 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R17C22:PLC2
|
|
arc: H00R0100 V02N0701
|
|
arc: V00T0100 V02N0501
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 H02E0601
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C8:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
|
|
.tile R17C9:PLC2
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M2 V00B0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00B0000 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R18C11:PLC2
|
|
arc: S1_V02S0601 H06W0303
|
|
|
|
.tile R18C12:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 H00R0000
|
|
arc: A1 E1_H01E0001
|
|
arc: B0 V00B0000
|
|
arc: B1 V00T0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 E1_H01W0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 F0
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0001000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R18C13:PLC2
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02E0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0101
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C5 V00T0100
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V02S0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V01S0100
|
|
arc: D4 V02N0401
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F3
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICEC.K1.INIT 1101010111010101
|
|
word: SLICED.K0.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 1011111100111111
|
|
word: SLICEA.K0.INIT 1101110101010101
|
|
word: SLICEA.K1.INIT 0000000000001100
|
|
word: SLICEB.K0.INIT 1111001011111010
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R18C14:PLC2
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: B5 W1_H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01S0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 N1_V01S0000
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 0000111111110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R18C15:PLC2
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A3 V00T0000
|
|
arc: B2 H00R0100
|
|
arc: B3 S1_V02N0301
|
|
arc: B7 V00T0000
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H00R0100
|
|
arc: C7 V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D7 H00R0100
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 F3
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K0.INIT 0000110000000000
|
|
word: SLICEB.K1.INIT 1100110011000100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110011110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R18C16:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0301 V01N0101
|
|
|
|
.tile R18C17:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0000 H02W0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q0
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0000 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R18C18:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C19:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00B0000 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R18C20:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R18C21:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0401 Q4
|
|
arc: LSR0 W1_H02E0501
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00T0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R18C22:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 H02E0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R18C23:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R18C24:PLC2
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R18C7:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
|
|
.tile R18C8:PLC2
|
|
arc: V00T0000 V02N0601
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R19C10:PLC2
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A3 V02N0701
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0301
|
|
arc: C2 H00L0100
|
|
arc: C3 E1_H02W0601
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 S1_V02N0201
|
|
arc: E3_H06E0103 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: MUXCLK1 CLK0
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 1110001011100010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R19C11:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R19C12:PLC2
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B6 V01S0000
|
|
arc: B7 V00T0000
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C4 V00B0100
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 H02E0601
|
|
arc: C7 H02E0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 H02E0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 1111101000001010
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEC.K1.INIT 1111000010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R19C13:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: B3 V02S0301
|
|
arc: B4 V00B0100
|
|
arc: B6 V00B0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 Q4
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H00R0100
|
|
arc: D5 V00B0000
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0103 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEC.K0.INIT 0001010001010000
|
|
word: SLICEC.K1.INIT 0000000001011010
|
|
word: SLICED.K0.INIT 0000011100001111
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100000011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R19C14:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0201 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R19C15:PLC2
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0501
|
|
arc: C4 V00B0100
|
|
arc: C5 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V01S0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V00B0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R19C16:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R19C17:PLC2
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R19C18:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: V00B0000 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R19C19:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
|
|
.tile R19C20:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00R0100 V02N0701
|
|
arc: V00T0000 V02N0401
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0501
|
|
arc: M2 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R19C21:PLC2
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R19C22:PLC2
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00T0100 V02N0501
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: A3 V02N0501
|
|
arc: B2 F3
|
|
arc: C3 V02N0401
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0201
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K0.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 1111101000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R19C23:PLC2
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R19C24:PLC2
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
|
|
.tile R19C3:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R19C4:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile R19C5:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
|
|
.tile R19C6:PLC2
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C8:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R19C9:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: S1_V02S0301 H02W0301
|
|
|
|
.tile R20C10:PLC2
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: V00B0100 H02W0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A7 E1_H02W0701
|
|
arc: B1 E1_H02W0101
|
|
arc: C1 E1_H02W0601
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D7 H00L0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R20C11:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0000 V02N0001
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M2 V00T0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R20C12:PLC2
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 V02N0601
|
|
arc: C7 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D7 H02W0001
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R20C13:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0100 V02S0101
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0000
|
|
arc: M2 E1_H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R20C14:PLC2
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A0 H00L0000
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H01W0100
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H00R0000
|
|
arc: D1 E1_H02W0201
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0101 F1
|
|
arc: V00B0000 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0011000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R20C15:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A4 V00B0000
|
|
arc: B2 F3
|
|
arc: B3 H02E0101
|
|
arc: B4 N1_V02S0501
|
|
arc: C2 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 H00R0000
|
|
arc: D4 V01N0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: M0 H02E0601
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0601 F4
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0011000011110000
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 0001010101110111
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R20C16:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: CE0 V02S0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R20C17:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0100 V02N0701
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00R0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q4
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00T0000 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R20C18:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: M0 H02W0601
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R20C19:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 E1_H02W0501
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 E1_H02W0501
|
|
arc: B1 V02N0301
|
|
arc: C0 H00L0100
|
|
arc: C1 V02N0401
|
|
arc: C4 H02E0601
|
|
arc: C5 V00T0000
|
|
arc: CE0 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R20C20:PLC2
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0401 Q4
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R20C21:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: C1 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0601 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000111100001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R20C22:PLC2
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A1 H02W0701
|
|
arc: A6 F7
|
|
arc: A7 H02W0701
|
|
arc: B1 V02N0301
|
|
arc: B6 F1
|
|
arc: B7 V02N0501
|
|
arc: C1 H02E0601
|
|
arc: C6 V00T0000
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H02W0001
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 F7
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 1110110011111111
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000010000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX INV
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R20C23:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 V02N0701
|
|
arc: A3 V01N0101
|
|
arc: A4 N1_V01N0101
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0301
|
|
arc: B1 V01N0001
|
|
arc: B3 H00R0100
|
|
arc: B4 V01S0000
|
|
arc: B5 H00R0000
|
|
arc: B6 F1
|
|
arc: B7 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0001
|
|
arc: C5 E1_H02W0601
|
|
arc: C7 E1_H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 F0
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02S0401
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F6
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q4
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0111011111111111
|
|
word: SLICED.K1.INIT 0001001100110011
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 1100000000000000
|
|
word: SLICEC.K0.INIT 0000000010000000
|
|
word: SLICEC.K1.INIT 0000000011111100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R20C24:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
|
|
.tile R20C25:PLC2
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A7 Q7
|
|
arc: B0 V00B0000
|
|
arc: B4 V02N0501
|
|
arc: C0 H00L0100
|
|
arc: C1 F4
|
|
arc: C4 V00B0100
|
|
arc: C5 H02E0601
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D4 H00R0100
|
|
arc: D5 V01N0001
|
|
arc: D6 H02E0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q5
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0701 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000000000110010
|
|
word: SLICEC.K1.INIT 0000111100000000
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0000000011111010
|
|
word: SLICEA.K0.INIT 1111110000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R20C4:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C5:PLC2
|
|
arc: S1_V02S0201 V01N0001
|
|
|
|
.tile R20C6:PLC2
|
|
arc: S1_V02S0501 V01N0101
|
|
|
|
.tile R20C7:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0100 V02S0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S3_V06S0203 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R20C8:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: V00B0000 V02N0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0103 Q2
|
|
arc: H01W0000 Q6
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R20C9:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A7 V02N0301
|
|
arc: B1 V00T0000
|
|
arc: B7 S1_V02N0701
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1101110100010001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100000011001111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R21C10:PLC2
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A1 V02N0501
|
|
arc: B4 H02E0301
|
|
arc: C1 H02E0401
|
|
arc: C4 H01E0001
|
|
arc: C5 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V01S0100
|
|
arc: D4 S1_V02N0401
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M2 V00B0100
|
|
arc: M4 H02E0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010100000101
|
|
word: SLICEC.K0.INIT 0011001111110000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C11:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A6 H00L0000
|
|
arc: B2 V02N0101
|
|
arc: B6 H02W0101
|
|
arc: B7 V02N0701
|
|
arc: C3 F6
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 F6
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D6 H01W0000
|
|
arc: D7 V01N0001
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F2
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000010100110101
|
|
word: SLICED.K1.INIT 1100111100000011
|
|
word: SLICEB.K0.INIT 0000000000110011
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R21C12:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A2 V00B0000
|
|
arc: A3 E1_H02W0701
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 H00L0000
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1010110011001100
|
|
word: SLICEB.K1.INIT 1100101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C13:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 V02N0301
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 E1_H02W0501
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0000
|
|
arc: C2 H02E0601
|
|
arc: CE1 H00L0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 F2
|
|
arc: E1_H02E0301 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 F2
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0001000100011011
|
|
word: SLICEB.K1.INIT 1000100011011101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R21C14:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V00B0000
|
|
arc: B2 E1_H01W0100
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 V02N0401
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V01S0100
|
|
arc: D3 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F2
|
|
arc: M0 V00T0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000001001010111
|
|
word: SLICEB.K1.INIT 1010000010101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R21C15:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: A5 V02N0301
|
|
arc: A7 Q7
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 V02S0501
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 F4
|
|
arc: C6 V00B0100
|
|
arc: C7 V02S0001
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02N0601
|
|
arc: D5 H02W0001
|
|
arc: D6 V00B0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0401 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F5
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 F6
|
|
arc: V00B0100 Q7
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 0000000000000011
|
|
word: SLICED.K1.INIT 0000010100001010
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0000101100001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R21C16:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 H02E0701
|
|
arc: B1 S1_V02N0301
|
|
arc: B4 H00L0000
|
|
arc: C0 F4
|
|
arc: C4 V01N0101
|
|
arc: C5 F4
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 F1
|
|
arc: M2 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000010100110011
|
|
word: SLICEC.K1.INIT 1010111100000101
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 0000000000110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R21C17:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: A3 H02E0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 H00R0000
|
|
arc: B7 V02N0501
|
|
arc: C0 H02W0601
|
|
arc: C1 F6
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 F2
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D6 V02N0401
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F2
|
|
arc: M0 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000010111110101
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 0000111100001111
|
|
word: SLICEA.K1.INIT 0000000011111100
|
|
word: SLICEB.K0.INIT 0000000000110000
|
|
word: SLICEB.K1.INIT 0001000100011011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R21C18:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: B5 H02E0101
|
|
arc: C5 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 Q5
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000000110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R21C19:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: B7 V02N0701
|
|
arc: C7 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D7 W1_H02E0001
|
|
arc: F7 F7_SLICE
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: V00B0100 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011110011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R21C20:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: A5 H02E0701
|
|
arc: B5 F1
|
|
arc: C1 V02N0601
|
|
arc: C4 E1_H01E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0101 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0601 F4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000111100001111
|
|
word: SLICEC.K1.INIT 0000000000010001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R21C21:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: A3 W1_H02E0501
|
|
arc: B7 F3
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D6 V00B0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H02E0201 Q0
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R21C22:PLC2
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A1 V02S0701
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0701
|
|
arc: C1 N1_V02S0401
|
|
arc: C4 V00B0100
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D4 H02E0201
|
|
arc: D5 V01N0001
|
|
arc: E1_H02E0301 Q1
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00B0100 Q5
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R21C23:PLC2
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0000 H02W0001
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 H02W0601
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R21C24:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0000 H02W0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C25:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: A0 V02S0701
|
|
arc: A2 V02N0501
|
|
arc: A3 V02S0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B3 H00R0000
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C0 F4
|
|
arc: C2 H00R0100
|
|
arc: C3 F4
|
|
arc: C4 V02S0001
|
|
arc: C5 H02E0401
|
|
arc: C6 V00B0100
|
|
arc: C7 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V00B0100
|
|
arc: D3 F2
|
|
arc: D4 H01W0000
|
|
arc: D5 V02N0401
|
|
arc: D6 H00R0100
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEC.K0.INIT 0000000000000101
|
|
word: SLICEC.K1.INIT 1111000010100000
|
|
word: SLICEB.K0.INIT 1111111111111010
|
|
word: SLICEB.K1.INIT 0000000000000100
|
|
word: SLICED.K0.INIT 0000000000001100
|
|
word: SLICED.K1.INIT 0000111100001110
|
|
word: SLICEA.K0.INIT 1100110011001101
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R21C26:PLC2
|
|
arc: W1_H02W0301 H01E0101
|
|
|
|
.tile R21C2:PLC2
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
|
|
.tile R21C3:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 V02N0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q4
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C4:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: A2 V01N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 H00R0000
|
|
arc: C2 V02N0401
|
|
arc: C3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H01E0101
|
|
arc: D3 F2
|
|
arc: E3_H06E0003 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1010100010101010
|
|
word: SLICEB.K1.INIT 1111001100000011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R21C5:PLC2
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 H02W0101
|
|
arc: A3 H02E0501
|
|
arc: A4 N1_V01N0101
|
|
arc: B4 V02N0701
|
|
arc: B5 V01S0000
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 H02E0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02W0001
|
|
arc: D3 H00R0000
|
|
arc: D4 F2
|
|
arc: D5 H01W0000
|
|
arc: E1_H02E0701 F5
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F4
|
|
arc: M0 V00T0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000111111111111
|
|
word: SLICEB.K1.INIT 0000010111110101
|
|
word: SLICEC.K0.INIT 1111110100000000
|
|
word: SLICEC.K1.INIT 1111001100000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R21C6:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: B0 H01W0100
|
|
arc: B1 E1_H01W0100
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0401
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: S3_V06S0103 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111111101010011
|
|
word: SLICEA.K1.INIT 0000000011100010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C7:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 H01E0001
|
|
arc: A3 V00B0000
|
|
arc: B0 V02N0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02N0401
|
|
arc: C3 E1_H02W0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 F0
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F2
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0011111101110111
|
|
word: SLICEA.K1.INIT 1000101100000011
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
word: SLICEB.K1.INIT 0000110000001010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R21C8:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A1 H00L0000
|
|
arc: A7 V02N0101
|
|
arc: C1 V02N0401
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0501 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010000010101111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111000001010101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R21C9:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 S1_V02N0701
|
|
arc: A3 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 V01N0001
|
|
arc: C1 H00L0100
|
|
arc: C3 H02E0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 H00R0000
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 Q4
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 F0
|
|
arc: V00B0000 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111011100000000
|
|
word: SLICEA.K0.INIT 0000000001010101
|
|
word: SLICEA.K1.INIT 0001010100000100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R22C10:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A3 H02E0501
|
|
arc: A6 V02N0301
|
|
arc: A7 W1_H02E0501
|
|
arc: B2 F3
|
|
arc: B3 V01N0001
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02E0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H02E0001 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0101 Q3
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F6
|
|
word: SLICEB.K0.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 0111011101000100
|
|
word: SLICED.K0.INIT 0000000001010101
|
|
word: SLICED.K1.INIT 0000000001010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R22C11:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R22C12:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A0 V02N0701
|
|
arc: A1 H02W0501
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0301
|
|
arc: B0 V02N0301
|
|
arc: B6 V02N0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C6 V00T0000
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D6 H02E0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111011110000000
|
|
word: SLICED.K1.INIT 1101100011110000
|
|
word: SLICEA.K0.INIT 1111011110000000
|
|
word: SLICEA.K1.INIT 1010111100000101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R22C13:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0301
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 E1_H02W0501
|
|
arc: B1 H01W0100
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02N0701
|
|
arc: B7 H02W0101
|
|
arc: C1 H02W0401
|
|
arc: C2 V02S0601
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 V00T0000
|
|
arc: C6 H02E0601
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 V02N0401
|
|
arc: D5 H02W0201
|
|
arc: D6 H00R0100
|
|
arc: D7 N1_V02S0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEC.K0.INIT 1101100011110000
|
|
word: SLICEC.K1.INIT 1110001010101010
|
|
word: SLICEA.K0.INIT 0101010101010101
|
|
word: SLICEA.K1.INIT 0000000000000010
|
|
word: SLICED.K0.INIT 1111101000000000
|
|
word: SLICED.K1.INIT 0000000011000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000000001010101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R22C14:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A6 V02N0101
|
|
arc: A7 E1_H02W0701
|
|
arc: B6 H02E0101
|
|
arc: B7 N1_V01S0000
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1110010011001100
|
|
word: SLICED.K1.INIT 1110110001001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R22C15:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A7 H02E0501
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0201 Q0
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111010110100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R22C16:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: A2 H02E0501
|
|
arc: A3 V02S0501
|
|
arc: A6 V02N0101
|
|
arc: A7 V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B6 H01E0101
|
|
arc: B7 N1_V01S0000
|
|
arc: C3 H00R0100
|
|
arc: C6 V01N0101
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D6 H02E0201
|
|
arc: D7 H01W0000
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0103 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 F3
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1110110001001100
|
|
word: SLICED.K1.INIT 1110110001001100
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICEB.K1.INIT 0101010000010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R22C17:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 V02N0501
|
|
arc: A4 H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B1 H02E0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0301
|
|
arc: C1 V02S0401
|
|
arc: C4 H02E0401
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 F4
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D4 H00L0100
|
|
arc: D5 V00B0000
|
|
arc: D6 H01W0000
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0601 F6
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
word: SLICEA.K1.INIT 0000111000000010
|
|
word: SLICEC.K0.INIT 0000010100100111
|
|
word: SLICEC.K1.INIT 1100000011001111
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 0000000001010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R22C18:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R22C19:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H02E0701 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R22C20:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: A3 H02W0501
|
|
arc: A5 H02E0701
|
|
arc: B7 F1
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 F4
|
|
arc: C4 V02N0201
|
|
arc: C5 V02S0201
|
|
arc: C7 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V02S0401
|
|
arc: D6 V01N0001
|
|
arc: D7 V02S0401
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0401 F6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0100 F4
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010111100000101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000111100001111
|
|
word: SLICEC.K1.INIT 0000000000000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R22C21:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: B1 V00B0000
|
|
arc: B5 S1_V02N0501
|
|
arc: C1 V02N0601
|
|
arc: C5 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V01S0000
|
|
arc: D5 V02N0401
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q1
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q5
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1100111100000011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100000011001111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R22C22:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: CE1 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M2 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: S1_V02S0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R22C23:PLC2
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
|
|
.tile R22C24:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R22C25:PLC2
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A2 V00B0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 H00L0000
|
|
arc: C3 H02E0401
|
|
arc: C6 H02E0401
|
|
arc: C7 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 H00R0000
|
|
arc: D3 V01S0100
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H00R0100 Q7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q7
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K0.INIT 1111000011000000
|
|
word: SLICED.K1.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 0101010101010000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100000011000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R22C2:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R22C3:PLC2
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R22C4:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A5 H02E0701
|
|
arc: C4 H02E0401
|
|
arc: C5 S1_V02N0201
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H02E0201
|
|
arc: D5 W1_H02E0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q6
|
|
arc: F4 F5C_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000111111111111
|
|
word: SLICEC.K1.INIT 0000010110101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R22C5:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0201 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R22C6:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V02S0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 V02N0501
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 V02S0401
|
|
arc: D6 H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0100 F6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000111111111111
|
|
word: SLICED.K1.INIT 0011001100001111
|
|
word: SLICEC.K0.INIT 1111111100110101
|
|
word: SLICEC.K1.INIT 0000000011100100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R22C7:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: A2 V02S0701
|
|
arc: A3 V02N0501
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 H01W0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02S0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 F3
|
|
arc: E3_H06E0203 Q4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0101010000000100
|
|
word: SLICEB.K1.INIT 0001000100011011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R22C8:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: A4 V02N0301
|
|
arc: A5 V00B0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H00L0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 F4
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0303 Q6
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0011111101011111
|
|
word: SLICEC.K1.INIT 1010000000110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R22C9:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A0 H02W0701
|
|
arc: A1 V02N0701
|
|
arc: A3 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 E1_H01W0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 V02S0201
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 H00R0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0201 F2
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F1
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000001010101
|
|
word: SLICEA.K1.INIT 0000000001010101
|
|
word: SLICEB.K0.INIT 1100110011111111
|
|
word: SLICEB.K1.INIT 0011001101010101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R23C10:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: A4 H02W0701
|
|
arc: A5 V00T0000
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 V02S0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02S0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 H02W0101
|
|
arc: B5 N1_V02S0701
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 V02S0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 V02S0601
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 V02S0201
|
|
arc: C7 F6
|
|
arc: CE3 H00R0000
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 V02N0601
|
|
arc: D5 H00R0100
|
|
arc: D6 V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1010101000000000
|
|
word: SLICED.K1.INIT 0011111100110000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R23C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 V02S0701
|
|
arc: B0 H02E0101
|
|
arc: B1 V00T0000
|
|
arc: B2 H01W0100
|
|
arc: B7 H02E0301
|
|
arc: C0 V02S0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 V02N0401
|
|
arc: C7 H02W0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 V02N0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 0001010100111111
|
|
word: SLICEB.K0.INIT 0001010100111111
|
|
word: SLICEB.K1.INIT 1111010110100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111110000001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R23C12:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 H02E0101
|
|
arc: B5 N1_V02S0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 W1_H02E0401
|
|
arc: C7 V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 V02S0201
|
|
arc: D2 V02S0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F3
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V02N0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A3 V01N0101
|
|
arc: A7 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B5 V02N0701
|
|
arc: B7 V02N0701
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0601
|
|
arc: C5 S1_V02N0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q3
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111110000110000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1110111000100010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R23C14:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 H02E0501
|
|
arc: A5 V00B0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0101
|
|
arc: B5 H02E0101
|
|
arc: B7 F3
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H00R0100
|
|
arc: D5 H00L0100
|
|
arc: D7 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 F1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C15:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 H00L0000
|
|
arc: B5 N1_V02S0501
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 H02E0601
|
|
arc: C5 E1_H02W0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H02W0001
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C16:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A2 V01N0101
|
|
arc: A3 V02N0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V00B0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B7 F1
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 H02W0401
|
|
arc: C5 H02W0601
|
|
arc: C7 H01E0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H02W0201
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110011110000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R23C17:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A3 H01E0001
|
|
arc: B5 W1_H02E0301
|
|
arc: C3 V02N0401
|
|
arc: C5 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 W1_H02E0201
|
|
arc: D5 H00L0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0101 Q3
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R23C18:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: CE0 H00L0100
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0000 Q0
|
|
arc: M0 H01E0001
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0100 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0701
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B6 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C2 V02S0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C6 H01E0001
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0001
|
|
arc: D6 H01W0000
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111110100100000
|
|
word: SLICEB.K1.INIT 1111011110000000
|
|
word: SLICED.K0.INIT 1111001011010000
|
|
word: SLICED.K1.INIT 1111100001110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C20:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A3 H02W0701
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02W0001
|
|
arc: E1_H02E0401 Q6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F3
|
|
arc: M0 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0201 Q0
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000010100000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R23C21:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A5 H02E0701
|
|
arc: B1 H02E0301
|
|
arc: C1 V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C5 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H00R0000
|
|
arc: D1 H02E0201
|
|
arc: D2 V01S0100
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 V02N0601
|
|
arc: D5 V02S0601
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: M0 H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 F0
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0100 F4
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0000000000000011
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICEC.K1.INIT 0000000000000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R23C22:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 V02N0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: B7 H02W0101
|
|
arc: C3 H02E0401
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02S0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R23C23:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A5 S1_V02N0101
|
|
arc: B7 H02E0101
|
|
arc: C3 H02E0601
|
|
arc: C5 W1_H02E0601
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 H00R0000
|
|
arc: D5 W1_H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0501 Q5
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 F3
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011001111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1010000010101111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R23C24:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: V00B0100 H02E0501
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R23C25:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R23C2:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R23C3:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 V02S0201
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0100 H02E0501
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R23C4:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A4 V02S0301
|
|
arc: A5 H02E0701
|
|
arc: B4 V01S0000
|
|
arc: C4 H02E0401
|
|
arc: C5 F4
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 H01W0000
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: V01S0000 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111101100000000
|
|
word: SLICEC.K1.INIT 1010000011110101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R23C5:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0103 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R23C6:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A2 V02S0701
|
|
arc: B2 H01W0100
|
|
arc: B3 H00R0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02S0001
|
|
arc: D3 S1_V02N0201
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M0 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111000010110000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A1 H02E0701
|
|
arc: A7 V02S0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H00L0000
|
|
arc: C6 H02E0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000111111111111
|
|
word: SLICED.K1.INIT 0101010100001111
|
|
word: SLICEA.K0.INIT 0000111111111111
|
|
word: SLICEA.K1.INIT 0101000001011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R23C8:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 H02E0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A4 V02S0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 W1_H02E0101
|
|
arc: C4 H01E0001
|
|
arc: C5 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H01W0000
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0101 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1110000011110000
|
|
word: SLICEC.K1.INIT 1111110000001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R23C9:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: A0 V02S0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B1 V00T0000
|
|
arc: B6 V02S0701
|
|
arc: B7 V02N0501
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V02S0601
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 H00R0000
|
|
arc: D6 H02W0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
word: SLICEA.K1.INIT 0001001101011111
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0000011101110111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R24C10:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A5 E1_H02W0501
|
|
arc: A7 E1_H02W0501
|
|
arc: B3 H02E0101
|
|
arc: B7 H02E0301
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 H01E0001
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 E1_H02W0001
|
|
arc: D5 H02W0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 Q3
|
|
arc: S3_V06S0003 Q3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1101110110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R24C11:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02S0301
|
|
arc: A7 H02W0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0100
|
|
arc: C5 H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 H00L0100
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F1
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S1_V02S0501 Q7
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R24C12:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 V02N0701
|
|
arc: A4 H02W0701
|
|
arc: A5 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0000
|
|
arc: B4 H02E0301
|
|
arc: B5 V00B0100
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 N1_V02S0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 V00T0100
|
|
arc: C7 V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V02S0601
|
|
arc: D5 H02E0001
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0100 Q7
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R24C13:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V00T0100
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V02S0701
|
|
arc: B7 F1
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 H02W0601
|
|
arc: C5 W1_H02E0601
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 V00B0000
|
|
arc: D5 N1_V02S0601
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 F0
|
|
arc: S1_V02S0501 Q7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C14:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 H02E0701
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V00B0100
|
|
arc: B5 V02S0701
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0000
|
|
arc: C5 H02E0601
|
|
arc: C7 H01E0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 V02S0401
|
|
arc: D5 V02N0601
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F1
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V01N0001 Q7
|
|
arc: S3_V06S0203 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R24C15:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: A1 V02S0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V02S0501
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 H02E0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H02E0301
|
|
arc: B5 V01S0000
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 V02S0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 V02N0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C5 S1_V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 V02S0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 F2
|
|
arc: D5 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 F1
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K0.INIT 0001001101011111
|
|
word: SLICEB.K1.INIT 1010000010101111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010101000110011
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1100110000001111
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111011110000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R24C16:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V02S0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 V00B0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 H00R0000
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0100
|
|
arc: C5 V00T0000
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H00L0100
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F7
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110000001111
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R24C17:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N1_V02S0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02W0501
|
|
arc: A5 V02S0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 H00L0000
|
|
arc: B5 V02S0701
|
|
arc: B7 H02E0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0000
|
|
arc: C5 N1_V02S0201
|
|
arc: C7 V00T0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02W0001
|
|
arc: D5 H00L0100
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0100 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R24C18:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A1 E1_H02W0701
|
|
arc: A5 E1_H02W0701
|
|
arc: B7 W1_H02E0301
|
|
arc: C1 H02E0601
|
|
arc: C5 H01E0001
|
|
arc: C7 H02E0401
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H01E0101
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111101001010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R24C19:PLC2
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: A2 H02E0501
|
|
arc: A3 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0701
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: C4 V02S0201
|
|
arc: C5 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 V02S0201
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 H02E0201
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1011111110000000
|
|
word: SLICEC.K1.INIT 1111100001110000
|
|
word: SLICEB.K0.INIT 1011101010001010
|
|
word: SLICEB.K1.INIT 1010110011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C20:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: A7 H00R0000
|
|
arc: C7 H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D7 V02S0601
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0000
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010000010101111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R24C21:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: A5 N1_V01S0100
|
|
arc: B5 V02N0501
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 V02N0601
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q6
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1101110100010001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R24C22:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 H02W0401
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: A0 V02S0501
|
|
arc: A1 E1_H01E0001
|
|
arc: B3 E1_H02W0301
|
|
arc: B5 V02S0501
|
|
arc: B6 V00B0100
|
|
arc: B7 V01S0000
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 H02W0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 H02W0601
|
|
arc: C7 H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 H01E0101
|
|
arc: D3 H00R0000
|
|
arc: D5 V02S0401
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q5
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
word: SLICEA.K1.INIT 1010111110100000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R24C23:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q0
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R24C24:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H02E0501
|
|
arc: C2 H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0201
|
|
arc: D3 N1_V01S0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
word: SLICEB.K1.INIT 1111010110100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R24C2:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R24C3:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A3 S1_V02N0701
|
|
arc: A7 H02W0701
|
|
arc: B5 F3
|
|
arc: C3 V02N0601
|
|
arc: C4 V02S0201
|
|
arc: C5 V00T0100
|
|
arc: C7 V02N0001
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0001
|
|
arc: D5 H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R24C4:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 H02E0001
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A1 V02N0501
|
|
arc: B7 F1
|
|
arc: C1 V02N0401
|
|
arc: C7 V00T0100
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D6 V02S0601
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 Q6
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00T0100 Q1
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1111000011001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111101001010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R24C5:PLC2
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 H02W0601
|
|
arc: M2 V00T0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R24C6:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0000 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R24C7:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S3_V06S0103 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R24C8:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q2
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R24C9:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02S0101
|
|
arc: B0 V00T0000
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 H00R0000
|
|
arc: B5 H02W0101
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 H02E0601
|
|
arc: C5 N1_V02S0001
|
|
arc: C6 V00B0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V02S0601
|
|
arc: D5 H00L0100
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S3_V06S0303 F6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C10:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A6 H02W0501
|
|
arc: B1 W1_H02E0301
|
|
arc: B3 W1_H02E0301
|
|
arc: B6 H02E0101
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02N0601
|
|
arc: C3 H00L0000
|
|
arc: C7 F6
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 F0
|
|
arc: D2 V02S0001
|
|
arc: D3 F2
|
|
arc: D6 V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F0
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: S3_V06S0003 F3
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 0000110000111111
|
|
word: SLICED.K0.INIT 1101110110001000
|
|
word: SLICED.K1.INIT 0000001111001111
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
word: SLICEB.K1.INIT 0000110000111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R26C11:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: B2 F3
|
|
arc: C2 H00L0100
|
|
arc: C3 H02E0601
|
|
arc: C4 V02S0201
|
|
arc: C5 F4
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V02N0601
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H02E0001 F2
|
|
arc: E3_H06E0303 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 F4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 F3
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
word: SLICEC.K1.INIT 0101010100001111
|
|
word: SLICEB.K0.INIT 0000111100110011
|
|
word: SLICEB.K1.INIT 1111010110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R26C12:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 V02S0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0101
|
|
arc: B5 H00R0000
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 H02W0401
|
|
arc: C5 N1_V02S0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V00B0000
|
|
arc: D5 W1_H02E0201
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C14:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 H02E0501
|
|
arc: A5 V00B0000
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V02N0701
|
|
arc: B5 H02W0301
|
|
arc: B6 F3
|
|
arc: B7 H02E0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0100
|
|
arc: C5 H02W0601
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 N1_V02S0001
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 V02S0401
|
|
arc: D5 H00L0100
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0501 F7
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 0101010111000101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R26C15:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H00R0000
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0000
|
|
arc: C5 H01E0001
|
|
arc: C7 H02W0401
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H02W0001
|
|
arc: D5 V02N0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F3
|
|
arc: LSR1 H02W0301
|
|
arc: N1_V01N0101 F7
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010101000001111
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R26C16:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V02S0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 H00R0000
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 H02W0401
|
|
arc: C5 V02N0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 V02N0601
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C17:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V02S0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 H02E0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B7 F1
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0201
|
|
arc: C7 H01E0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H02W0001
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: V01S0000 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1101100011011000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C18:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 N1_V02S0501
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 H02W0501
|
|
arc: A5 V02N0301
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V02N0201
|
|
arc: C5 V00T0000
|
|
arc: C7 H01E0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111010110100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0100
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: B7 H02E0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00L0000
|
|
arc: C2 H00R0100
|
|
arc: C3 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: C5 V02S0001
|
|
arc: C7 H02W0401
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 V02N0601
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0100 F1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C20:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: B1 H02W0301
|
|
arc: B2 H01W0100
|
|
arc: B3 N1_V02S0301
|
|
arc: B5 H02W0301
|
|
arc: C1 H02E0601
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C5 H01E0001
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H01E0101
|
|
arc: D2 H00R0000
|
|
arc: D3 N1_V02S0201
|
|
arc: D5 W1_H02E0201
|
|
arc: E3_H06E0303 Q5
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEB.K0.INIT 1111000011011000
|
|
word: SLICEB.K1.INIT 1110110001001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C21:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A4 V02S0301
|
|
arc: A5 V02S0301
|
|
arc: C0 V02S0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 H00R0000
|
|
arc: D3 V00B0100
|
|
arc: D4 H00R0100
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F0
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F1
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000000001010101
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R26C22:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: A3 V02S0501
|
|
arc: A5 N1_V01S0100
|
|
arc: B1 F3
|
|
arc: B7 V02S0501
|
|
arc: C1 V02N0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 H02E0401
|
|
arc: C7 H02E0601
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 V02N0201
|
|
arc: D5 F0
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0501 F7
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0000000000000011
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1010000010101111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010000010100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C23:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: A1 V02N0701
|
|
arc: A5 V02S0101
|
|
arc: C1 W1_H02E0401
|
|
arc: C5 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H00R0000
|
|
arc: D4 V01N0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00R0000 F4
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICEC.K1.INIT 0000000000000101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010000010101111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R26C24:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 V00T0000
|
|
arc: A7 H02E0501
|
|
arc: B1 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: B6 V00B0100
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C6 H02E0601
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H02E0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D6 V01N0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 Q3
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1111010110100000
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R26C2:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 V02S0401
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: V00B0000 V02N0001
|
|
arc: A1 H02E0501
|
|
arc: B1 V02N0101
|
|
arc: B3 F1
|
|
arc: C3 S1_V02N0601
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H00R0000
|
|
arc: D2 V02S0001
|
|
arc: D3 V00T0100
|
|
arc: E3_H06E0103 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0101 F1
|
|
arc: V00T0100 Q1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1101110110001000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R26C3:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0100 V02N0301
|
|
arc: A7 V00T0100
|
|
arc: B1 V02S0301
|
|
arc: B3 V02S0101
|
|
arc: B5 F1
|
|
arc: B7 F3
|
|
arc: C1 E1_H02W0601
|
|
arc: C3 V02S0601
|
|
arc: C5 H02E0601
|
|
arc: C6 H02E0401
|
|
arc: C7 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H00R0000
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H01W0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: V00T0100 Q3
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111110000001100
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1010110010101100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R26C4:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: A1 V02S0501
|
|
arc: A3 V02S0701
|
|
arc: A7 V00T0100
|
|
arc: B5 F3
|
|
arc: B7 F1
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 V02S0601
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 H02E0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D3 H02E0001
|
|
arc: D5 H00L0100
|
|
arc: E1_H01E0001 F1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M4 H02E0401
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0100 Q1
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1010110010101100
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111101000001010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R26C5:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 H00L0100
|
|
arc: B1 V02S0301
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 H02W0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V01S0100
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q4
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 F1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1110010011100100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R26C6:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A3 V00B0000
|
|
arc: B3 E1_H01W0100
|
|
arc: C3 E1_H01W0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00B0100
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111100010001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R26C7:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0103 V06N0103
|
|
arc: A1 F7
|
|
arc: A3 H00L0100
|
|
arc: A5 H02W0501
|
|
arc: A6 V02N0301
|
|
arc: A7 H02W0501
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B5 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H02E0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 V00T0000
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 S1_V02N0001
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 F0
|
|
arc: D3 V00B0100
|
|
arc: D5 V02N0401
|
|
arc: D6 H00R0100
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F5
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F6
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICED.K1.INIT 0101001011110010
|
|
word: SLICEA.K0.INIT 0011001100110000
|
|
word: SLICEA.K1.INIT 1011111110000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0001010100111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0100110001101110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R26C8:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: A2 H02E0501
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 H02E0701
|
|
arc: A7 V02N0301
|
|
arc: B0 F3
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0100
|
|
arc: B3 V02S0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 H02E0101
|
|
arc: B7 V01S0000
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0000
|
|
arc: C5 V01N0101
|
|
arc: C7 V00T0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0001
|
|
arc: D2 H02W0201
|
|
arc: D3 F2
|
|
arc: D4 F2
|
|
arc: D5 V00B0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 F2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0103 F2
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0000000000100111
|
|
word: SLICEC.K0.INIT 0000111111011101
|
|
word: SLICEC.K1.INIT 1000000010111111
|
|
word: SLICEA.K0.INIT 1011001100010011
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0011111101010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R26C9:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: A4 V02S0101
|
|
arc: B5 H02E0301
|
|
arc: C4 V02N0201
|
|
arc: C5 F4
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H00R0100
|
|
arc: D5 H01W0000
|
|
arc: E3_H06E0303 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0203 F4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEC.K1.INIT 0000001111001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R27C10:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A1 F7
|
|
arc: A6 H02W0501
|
|
arc: A7 E1_H02W0501
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02N0101
|
|
arc: B3 F1
|
|
arc: B6 V00B0100
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C6 V00T0000
|
|
arc: C7 E1_H02W0401
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 W1_H02E0201
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0601 F6
|
|
arc: V00B0100 F7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0011010100000000
|
|
word: SLICED.K1.INIT 0000010111110101
|
|
word: SLICEB.K0.INIT 0000001111110011
|
|
word: SLICEB.K1.INIT 1100110011001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0011010100110101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R27C11:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A1 V01N0101
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 F5
|
|
arc: A5 V02N0301
|
|
arc: A6 N1_V01N0101
|
|
arc: B3 H00L0000
|
|
arc: B4 E1_H02W0101
|
|
arc: B6 V02S0501
|
|
arc: B7 V00B0000
|
|
arc: C0 V02S0401
|
|
arc: C1 H02W0401
|
|
arc: C3 V02N0401
|
|
arc: C4 H02E0601
|
|
arc: C5 V00B0100
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 V01S0100
|
|
arc: D2 H02W0201
|
|
arc: D3 H02W0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q4
|
|
arc: M2 W1_H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEB.K0.INIT 0101010100000000
|
|
word: SLICEB.K1.INIT 0011111100100010
|
|
word: SLICEC.K0.INIT 0100010001000111
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 0101000001011111
|
|
word: SLICED.K0.INIT 1000100010001000
|
|
word: SLICED.K1.INIT 0000001111110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R27C12:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: A0 H01E0001
|
|
arc: A5 V02N0101
|
|
arc: A6 E1_H01W0000
|
|
arc: B1 V00T0000
|
|
arc: B3 V02N0101
|
|
arc: B6 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 H02W0401
|
|
arc: C6 V02S0201
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 W1_H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D5 V02S0601
|
|
arc: D6 H01W0000
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H02E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICED.K0.INIT 1101110001010000
|
|
word: SLICED.K1.INIT 0000001111110011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
word: SLICEA.K0.INIT 1010111110101010
|
|
word: SLICEA.K1.INIT 0000001111110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C13:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V02N0701
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 H00L0000
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 V02S0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q3
|
|
arc: M0 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0100 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0011111111110101
|
|
word: SLICEB.K1.INIT 1111001000100010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C14:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: W3_H06W0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A1 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: B7 V02S0501
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 V02S0401
|
|
arc: C7 V02S0001
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D7 H02W0201
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111101001010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R27C15:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 V01N0101
|
|
arc: A4 H02W0501
|
|
arc: A6 H02W0501
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B4 H02E0101
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 H02E0101
|
|
arc: B7 H02W0101
|
|
arc: C1 W1_H02E0401
|
|
arc: C4 V00T0100
|
|
arc: C5 F4
|
|
arc: C6 H02W0601
|
|
arc: C7 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02S0601
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0701 Q7
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 1100000011001111
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 1100110000001111
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICEA.K1.INIT 1100000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C16:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: A6 H02W0701
|
|
arc: A7 H02W0501
|
|
arc: B3 H02E0101
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C3 E1_H02W0401
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0203 Q4
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 1111000010111000
|
|
word: SLICED.K1.INIT 1111000010111000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C17:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: A0 H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A4 V02S0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 V02S0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B6 V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H02E0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 H02E0601
|
|
arc: C5 F4
|
|
arc: C6 H02E0601
|
|
arc: C7 F6
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 F0
|
|
arc: D2 V02S0201
|
|
arc: D3 V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 H02E0201
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0100 Q7
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 1100110000001111
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1010101000001111
|
|
word: SLICEB.K0.INIT 0001010100111111
|
|
word: SLICEB.K1.INIT 1100110000001111
|
|
word: SLICEA.K0.INIT 0001001101011111
|
|
word: SLICEA.K1.INIT 1100000011001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C18:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A5 H02E0701
|
|
arc: C5 V02S0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 H02E0001
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0303 Q5
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R27C19:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A1 V02S0701
|
|
arc: A6 H00L0000
|
|
arc: B6 H02E0101
|
|
arc: C1 N1_V01S0100
|
|
arc: C6 V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D6 E1_H02W0001
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0103 Q1
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R27C20:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q2
|
|
arc: H01W0100 Q0
|
|
arc: M0 H01E0001
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0303 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R27C21:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H02E0501
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 H02W0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H01E0101
|
|
arc: C0 H02W0601
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 H02W0401
|
|
arc: C5 F4
|
|
arc: C6 H02W0401
|
|
arc: C7 F6
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D2 H02E0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 H02E0201
|
|
arc: D5 V02N0401
|
|
arc: D6 H02E0201
|
|
arc: D7 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F1
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0100 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1100110000001111
|
|
word: SLICEB.K0.INIT 1111100001110000
|
|
word: SLICEB.K1.INIT 1101100011110000
|
|
word: SLICED.K0.INIT 0101001101010000
|
|
word: SLICED.K1.INIT 1010101000001111
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 0000001100000011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R27C22:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: A3 V02S0501
|
|
arc: B7 H02E0101
|
|
arc: C3 H02W0401
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 H02W0201
|
|
arc: D7 F2
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000000000101
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R27C23:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A6 V02N0101
|
|
arc: A7 N1_V01N0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B3 W1_H02E0101
|
|
arc: C3 F6
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H00R0000
|
|
arc: D3 V02S0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0101010101010101
|
|
word: SLICED.K1.INIT 0000000000000101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100111100000011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R27C24:PLC2
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 V02N0701
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 H01E0001
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R27C2:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A1 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 V02N0301
|
|
arc: B5 F1
|
|
arc: B7 F3
|
|
arc: C1 S1_V02N0601
|
|
arc: C3 N1_V02S0601
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00T0100
|
|
arc: D3 H02E0201
|
|
arc: D5 V02N0601
|
|
arc: D6 V00B0000
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F1
|
|
arc: S3_V06S0203 Q4
|
|
word: SLICEC.K0.INIT 1010101010101010
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1110111001000100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R27C3:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: B1 V02N0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 N1_V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00T0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C4:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R27C5:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A3 S1_V02N0501
|
|
arc: C3 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 N1_V02S0201
|
|
arc: E1_H02E0101 F3
|
|
arc: E3_H06E0003 Q3
|
|
arc: F3 F3_SLICE
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N3_V06N0003 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111010110100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R27C6:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A3 V02S0701
|
|
arc: A4 H02E0501
|
|
arc: B1 N1_V02S0301
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 E1_H02W0301
|
|
arc: C1 V02S0401
|
|
arc: C3 V02N0401
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H01W0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0201 F2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 F1
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0301 F1
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1010101010101010
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0001001101011111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R27C7:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A6 V00T0100
|
|
arc: A7 N1_V01S0100
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B4 V02S0501
|
|
arc: B5 V01S0000
|
|
arc: B6 V02S0501
|
|
arc: B7 H02E0101
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 V01N0101
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V00B0100
|
|
arc: D3 F2
|
|
arc: D4 F2
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V01N0001
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0601 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 F5
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEB.K0.INIT 0000000000000100
|
|
word: SLICEB.K1.INIT 0000010000000000
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0001010100111111
|
|
word: SLICEC.K0.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 0011001111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C8:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V02S0101
|
|
arc: B2 F3
|
|
arc: B7 V02N0701
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C6 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D3 V02N0201
|
|
arc: D6 H02E0001
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F3
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1101110110001000
|
|
word: SLICEB.K0.INIT 1100000011000000
|
|
word: SLICEB.K1.INIT 0000000010100000
|
|
word: SLICEA.K0.INIT 1111000011100010
|
|
word: SLICEA.K1.INIT 1111000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R27C9:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V02N0701
|
|
arc: B0 F3
|
|
arc: B5 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C2 V02N0601
|
|
arc: C3 H02E0601
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 V00T0100
|
|
arc: CE0 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 F2
|
|
arc: D2 H02W0001
|
|
arc: D3 V02S0201
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 F3
|
|
arc: M0 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0101000001011111
|
|
word: SLICEB.K1.INIT 0101111100000000
|
|
word: SLICEA.K0.INIT 0011000000111111
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1111110000110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R28C10:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H00R0000
|
|
arc: A1 H02W0501
|
|
arc: A2 V02N0701
|
|
arc: A4 F5
|
|
arc: A6 H02E0701
|
|
arc: A7 V02S0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V01N0001
|
|
arc: B4 V02S0701
|
|
arc: B5 V01S0000
|
|
arc: B6 F1
|
|
arc: B7 V00B0100
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 H00R0100
|
|
arc: C2 H02E0401
|
|
arc: C4 H02W0601
|
|
arc: C5 V00T0000
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02W0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 F0
|
|
arc: D2 H01E0101
|
|
arc: D4 V02N0401
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 V01N0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F5
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEC.K0.INIT 0101001100000000
|
|
word: SLICEC.K1.INIT 0011000000111111
|
|
word: SLICEB.K0.INIT 1111010001000100
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1111101111111010
|
|
word: SLICED.K1.INIT 0011010100000000
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 0101100011111101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R28C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A0 V02N0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: A5 V00B0000
|
|
arc: A6 F7
|
|
arc: A7 H00R0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 F3
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 E1_H02W0301
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 F6
|
|
arc: C3 F4
|
|
arc: C4 V00T0100
|
|
arc: C5 V02S0201
|
|
arc: C6 V00B0100
|
|
arc: C7 V02S0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 F0
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 S1_V02N0601
|
|
arc: D7 E1_H01W0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q2
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K0.INIT 1011100010111000
|
|
word: SLICED.K1.INIT 0000101001011111
|
|
word: SLICEC.K0.INIT 1100111111000000
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICEB.K0.INIT 0000111100010001
|
|
word: SLICEB.K1.INIT 0110111100101011
|
|
word: SLICEA.K0.INIT 1101110110001000
|
|
word: SLICEA.K1.INIT 0110001011111011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R28C12:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A1 E1_H01E0001
|
|
arc: A4 V02N0101
|
|
arc: A6 H00L0000
|
|
arc: B0 V02S0301
|
|
arc: B1 H02W0101
|
|
arc: B4 H02W0301
|
|
arc: B6 V02S0701
|
|
arc: B7 V01S0000
|
|
arc: C1 E1_H02W0601
|
|
arc: C4 H02E0401
|
|
arc: C6 H02W0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 V00T0100
|
|
arc: D4 V01N0001
|
|
arc: D6 V02S0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q0
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEC.K0.INIT 1111111100000010
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 1001000101111001
|
|
word: SLICED.K0.INIT 1000100011111000
|
|
word: SLICED.K1.INIT 0000001111110011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 V01N0101
|
|
arc: A2 V02S0701
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V00B0000
|
|
arc: A6 H02E0501
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0101
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 V02N0701
|
|
arc: B6 W1_H02E0101
|
|
arc: C0 V02N0601
|
|
arc: C1 H02E0401
|
|
arc: C2 H00L0000
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 F2
|
|
arc: D4 V02N0601
|
|
arc: D5 H01W0000
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F5
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K0.INIT 1111100010001000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 0101001101010011
|
|
word: SLICEC.K0.INIT 1111010001000100
|
|
word: SLICEC.K1.INIT 1001001000101111
|
|
word: SLICEB.K0.INIT 0001001101011111
|
|
word: SLICEB.K1.INIT 0100010011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R28C14:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H01E0001
|
|
arc: A2 V02N0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01N0101
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H00R0100
|
|
arc: B4 S1_V02N0701
|
|
arc: B6 H02E0301
|
|
arc: B7 V00B0000
|
|
arc: C0 H02W0601
|
|
arc: C1 V02S0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0001
|
|
arc: C6 V02S0201
|
|
arc: C7 V02N0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 F0
|
|
arc: D6 V02S0601
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F3
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 Q5
|
|
arc: W3_H06W0003 F3
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0011001100000101
|
|
word: SLICEA.K0.INIT 0001110100000000
|
|
word: SLICEA.K1.INIT 0011000000111111
|
|
word: SLICEC.K0.INIT 0010111011001111
|
|
word: SLICEC.K1.INIT 1111111101010000
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
word: SLICEB.K1.INIT 1111000010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R28C15:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0601 Q6
|
|
arc: H01W0000 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R28C16:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V02S0701
|
|
arc: A2 H01E0001
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0100
|
|
arc: A6 N1_V02S0101
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 S1_V02N0301
|
|
arc: B4 V00B0100
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02W0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 F4
|
|
arc: C6 W1_H02E0601
|
|
arc: C7 F6
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 F0
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V02S0601
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02S0601
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 1100111100000011
|
|
word: SLICEA.K0.INIT 0001010100111111
|
|
word: SLICEA.K1.INIT 1100000011110011
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 1100111100000011
|
|
word: SLICEB.K0.INIT 1010101011110000
|
|
word: SLICEB.K1.INIT 1010000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R28C17:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 N1_V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 H01E0001
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 H02W0701
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 S1_V02N0101
|
|
arc: B2 H02E0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q5
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C18:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 H00L0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 H02E0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V02S0101
|
|
arc: B1 V02S0301
|
|
arc: B2 H00R0000
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q2
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0501 Q7
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: A0 H02W0501
|
|
arc: A1 V01N0101
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0100
|
|
arc: A5 V02N0301
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: B0 V01N0001
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H02W0301
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 V02N0501
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V00B0000
|
|
arc: B7 E1_H02W0101
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0601 Q4
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C20:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 V00B0000
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 V02N0301
|
|
arc: B3 H00R0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0000
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R28C21:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B6 V01S0000
|
|
arc: B7 V00B0100
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 H00R0100
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q0
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1100101010101010
|
|
word: SLICED.K1.INIT 1110110001001100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R28C22:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0101
|
|
arc: B2 H00R0100
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0701
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 V00B0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F5
|
|
arc: M0 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1011100011110000
|
|
word: SLICEB.K1.INIT 1110010011001100
|
|
word: SLICEC.K0.INIT 1011111110000000
|
|
word: SLICEC.K1.INIT 1111100001110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C23:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 W1_H02E0301
|
|
arc: B3 H02E0301
|
|
arc: C0 F6
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 F6
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H00R0000
|
|
arc: D3 V00B0100
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0301 Q3
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICED.K1.INIT 0000000000000101
|
|
word: SLICEA.K0.INIT 0000001100000011
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100110000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R28C24:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: B3 F1
|
|
arc: B7 V02S0701
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C7 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V01S0100
|
|
arc: D3 V00B0100
|
|
arc: D7 F2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICEB.K0.INIT 0000111100001111
|
|
word: SLICEB.K1.INIT 0000000000000011
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R28C2:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0100 H02W0301
|
|
arc: A1 H02E0501
|
|
arc: A7 S1_V02N0301
|
|
arc: B1 H02W0101
|
|
arc: B7 F1
|
|
arc: CE0 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0201
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 H01W0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0103 F1
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1110111001000100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1101110110001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R28C3:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02S0301
|
|
|
|
.tile R28C4:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: B2 E1_H01W0100
|
|
arc: C2 S1_V02N0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 S1_V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0203 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R28C5:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A1 V02S0701
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H02W0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V01S0100
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111000010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R28C6:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A2 H00L0100
|
|
arc: B2 E1_H01W0100
|
|
arc: C2 S1_V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 E1_H02W0201
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M4 H02W0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1110010011100100
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A0 H00L0100
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 N1_V02S0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 F3
|
|
arc: B2 H00R0100
|
|
arc: B3 V02S0301
|
|
arc: C0 H00L0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 H02W0401
|
|
arc: C3 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 F0
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 F2
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q4
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0101 Q1
|
|
arc: S3_V06S0303 Q6
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0000010000000000
|
|
word: SLICEB.K0.INIT 0000000000100000
|
|
word: SLICEB.K1.INIT 0000001100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R28C8:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 H02E0701
|
|
arc: A5 V02S0301
|
|
arc: A7 S1_V02N0101
|
|
arc: B2 H00R0100
|
|
arc: B4 H02E0301
|
|
arc: B5 F1
|
|
arc: B6 H02E0301
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 H02E0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 F6
|
|
arc: C6 E1_H01E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V00T0100
|
|
arc: D3 F2
|
|
arc: D4 H01W0000
|
|
arc: D5 H00L0100
|
|
arc: D6 V02S0601
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q5
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F2
|
|
arc: LSR1 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0103 F2
|
|
word: SLICEC.K0.INIT 1100000000000000
|
|
word: SLICEC.K1.INIT 0100111011001100
|
|
word: SLICEB.K0.INIT 1111100011110000
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000011111010
|
|
word: SLICED.K0.INIT 0011111111111111
|
|
word: SLICED.K1.INIT 1010101000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R28C9:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H02W0301
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C7 H02W0601
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 F0
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 F0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000010100000
|
|
word: SLICEA.K0.INIT 0100010001000000
|
|
word: SLICEA.K1.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C10:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 V01N0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A0 V02S0701
|
|
arc: A1 W1_H02E0701
|
|
arc: B2 F3
|
|
arc: C0 H00L0000
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 H02W0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 H00R0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q1
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111000011111100
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1111000010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R29C11:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 H01E0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A5 V00B0000
|
|
arc: A6 V02N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00T0000
|
|
arc: B5 H02W0301
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 H00L0000
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 F4
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 H02W0201
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 F2
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0100 F3
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0301 F1
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110101110110000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 0011001100001111
|
|
word: SLICED.K0.INIT 1111101011110000
|
|
word: SLICED.K1.INIT 0011001100110011
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
word: SLICEB.K1.INIT 1111000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R29C12:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 H02W0701
|
|
arc: A7 H02E0501
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 H02W0101
|
|
arc: B3 F1
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 W1_H02E0301
|
|
arc: B7 V00B0100
|
|
arc: C1 H02W0401
|
|
arc: C2 H00L0000
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0201
|
|
arc: D4 V02S0401
|
|
arc: D5 V00B0000
|
|
arc: D6 H00L0100
|
|
arc: D7 S1_V02N0601
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: V00B0000 F4
|
|
arc: V00T0100 F3
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 0000110000011101
|
|
word: SLICEB.K1.INIT 0111001010111011
|
|
word: SLICEC.K0.INIT 1001010001001111
|
|
word: SLICEC.K1.INIT 0000110010001100
|
|
word: SLICED.K0.INIT 1111010110100000
|
|
word: SLICED.K1.INIT 0110111101001101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A0 H02E0701
|
|
arc: A1 H00L0000
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A5 V02N0301
|
|
arc: A6 V02S0101
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 H02W0301
|
|
arc: B1 H02E0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 N1_V02S0301
|
|
arc: B6 H02W0101
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02W0401
|
|
arc: C2 V02S0401
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 E1_H02W0401
|
|
arc: C7 F6
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 H02E0001
|
|
arc: D3 F2
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 H00L0100
|
|
arc: D7 V01N0001
|
|
arc: E1_H02E0101 Q3
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0203 Q4
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 1001010001001111
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
word: SLICED.K0.INIT 0101010100110011
|
|
word: SLICED.K1.INIT 1111001111100010
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 0000010110101111
|
|
word: SLICEB.K0.INIT 0001001101011111
|
|
word: SLICEB.K1.INIT 0100010011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R29C14:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 H00R0000
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 V00B0000
|
|
arc: A3 H02W0501
|
|
arc: A4 V00T0100
|
|
arc: A5 V02N0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02N0301
|
|
arc: B0 H02W0301
|
|
arc: B1 V02N0301
|
|
arc: B2 H00R0100
|
|
arc: B3 V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B6 H02E0301
|
|
arc: C0 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: C4 H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V00B0100
|
|
arc: C7 F6
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 F0
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 F2
|
|
arc: D4 V02S0401
|
|
arc: D5 H01W0000
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 1010000011110101
|
|
word: SLICEA.K0.INIT 0001001101011111
|
|
word: SLICEA.K1.INIT 1000100010111011
|
|
word: SLICEB.K0.INIT 1000110010101111
|
|
word: SLICEB.K1.INIT 1011101110001000
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 1010111100000101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R29C15:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: A2 F7
|
|
arc: A5 H02E0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 E1_H02W0701
|
|
arc: B2 H02W0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B5 V01S0000
|
|
arc: B7 W1_H02E0101
|
|
arc: C2 H00L0100
|
|
arc: C3 H02E0401
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 V00B0100
|
|
arc: C6 V02N0201
|
|
arc: C7 V00T0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V01S0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 S1_V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0601 Q4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEB.K0.INIT 0010111011001111
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
word: SLICED.K0.INIT 1010000010100000
|
|
word: SLICED.K1.INIT 1001010001110011
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1000011000111011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R29C16:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: A0 E1_H02W0701
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V00T0100
|
|
arc: B0 H01W0100
|
|
arc: B1 H02E0301
|
|
arc: B6 V00B0100
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H02W0601
|
|
arc: C1 H02E0401
|
|
arc: C6 V00T0000
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0201
|
|
arc: D6 H00L0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q4
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q1
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1010101011100010
|
|
word: SLICED.K1.INIT 1010000011100100
|
|
word: SLICEA.K0.INIT 1011100010101010
|
|
word: SLICEA.K1.INIT 0000000000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R29C17:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0701
|
|
arc: A5 V00B0000
|
|
arc: A6 H00L0000
|
|
arc: B2 H00R0100
|
|
arc: B4 W1_H02E0101
|
|
arc: B7 E1_H02W0101
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F3
|
|
arc: N3_V06N0303 F6
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C18:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0701
|
|
arc: A7 H00L0000
|
|
arc: B0 H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B6 S1_V02N0501
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F7
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V02N0001 F2
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: A0 V02N0501
|
|
arc: A4 S1_V02N0301
|
|
arc: A6 V02N0301
|
|
arc: B1 H02E0301
|
|
arc: B2 V01N0001
|
|
arc: B3 N1_V02S0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 S1_V02N0701
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C20:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A2 V02N0501
|
|
arc: A3 V01N0101
|
|
arc: A4 H02E0701
|
|
arc: A5 H02W0501
|
|
arc: A6 V02N0301
|
|
arc: A7 H02W0701
|
|
arc: B0 H02E0101
|
|
arc: B1 V01N0001
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0601 F6
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F3
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C21:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 H00R0000
|
|
arc: B6 V01S0000
|
|
arc: B7 H02W0101
|
|
arc: C6 H02W0401
|
|
arc: C7 V01N0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 V02N0401
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F6
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0000 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1101111110000000
|
|
word: SLICED.K1.INIT 1111011110000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R29C22:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A3 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B4 H02W0301
|
|
arc: B5 F3
|
|
arc: B7 H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C5 H02W0401
|
|
arc: C7 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0001
|
|
arc: D5 H02W0201
|
|
arc: D7 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: V00B0000 F4
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEC.K0.INIT 0011001100110011
|
|
word: SLICEC.K1.INIT 0000000000000011
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011110011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICEA.K0.INIT 0000001100000011
|
|
word: SLICEA.K1.INIT 0000001100000011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R29C23:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A3 N1_V02S0701
|
|
arc: B3 F1
|
|
arc: B7 W1_H02E0101
|
|
arc: C1 E1_H01W0000
|
|
arc: C7 V00T0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00B0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 V02S0201
|
|
arc: D7 F2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F2
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000000010001
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011110011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R29C24:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: A1 E1_H01E0001
|
|
arc: A5 H02E0701
|
|
arc: B3 H02E0101
|
|
arc: B5 F1
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 F4
|
|
arc: C4 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0001
|
|
arc: D5 H02E0201
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEC.K0.INIT 0000111100001111
|
|
word: SLICEC.K1.INIT 0000000000010001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100111100000011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010000010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R29C2:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: A3 V01N0101
|
|
arc: A5 N1_V01N0101
|
|
arc: B3 H01W0100
|
|
arc: B5 S1_V02N0501
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V02N0401
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1110110010100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1110110010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R29C3:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R29C4:PLC2
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R29C5:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A1 S1_V02N0501
|
|
arc: B1 S1_V02N0101
|
|
arc: C1 H02E0601
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V01S0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R29C6:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H02W0701
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 F3
|
|
arc: B3 S1_V02N0101
|
|
arc: B5 S1_V02N0701
|
|
arc: C1 V02N0401
|
|
arc: C5 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02S0001
|
|
arc: D5 S1_V02N0601
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0301 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0101010100110011
|
|
word: SLICEB.K1.INIT 1011101110001000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: B0 V02S0101
|
|
arc: B3 H02E0301
|
|
arc: C1 W1_H02E0601
|
|
arc: C3 H00L0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 V02N0001
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 H02E0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q0
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICEA.K0.INIT 1110111001000100
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R29C8:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 H01E0001
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 V01N0101
|
|
arc: C5 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V00B0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: E1_H02E0301 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: M0 E1_H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100110011001010
|
|
word: SLICEB.K1.INIT 1111101000001010
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R29C9:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 V01N0001
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
arc: A2 V02S0701
|
|
arc: A7 N1_V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B7 V01S0000
|
|
arc: C2 V02S0401
|
|
arc: C3 H00L0000
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 V02S0001
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0203 F7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0301 F3
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100100011001100
|
|
word: SLICEB.K0.INIT 1110110010100000
|
|
word: SLICEB.K1.INIT 0000110011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R30C10:PLC2
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 V02N0701
|
|
arc: A1 S1_V02N0701
|
|
arc: A5 E1_H02W0701
|
|
arc: B0 V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 F1
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02N0201
|
|
arc: C5 V02S0201
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 F2
|
|
arc: D4 H01W0000
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V02N0601
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0501 Q5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 0000001100001111
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0011001100001111
|
|
word: SLICEA.K0.INIT 0100010000000100
|
|
word: SLICEA.K1.INIT 1010101001010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R30C11:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A1 F7
|
|
arc: A2 V02N0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A5 V00T0000
|
|
arc: A7 H00R0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H02W0301
|
|
arc: B3 W1_H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C0 H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 W1_H02E0401
|
|
arc: C5 H02W0601
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 F0
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 V00T0100
|
|
arc: D5 V01N0001
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q0
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 0010110011101111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110101110110000
|
|
word: SLICEB.K0.INIT 0101111100011011
|
|
word: SLICEB.K1.INIT 0000000000000100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1001010001001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R30C12:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H02E0101
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 H00L0000
|
|
arc: C4 H02W0401
|
|
arc: C5 F4
|
|
arc: C7 H02E0601
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 V00B0000
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 F3
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
word: SLICEC.K1.INIT 0011111110001011
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 0110111101001101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100111111111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R30C13:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 H02W0501
|
|
arc: A3 H00L0100
|
|
arc: A5 V00T0000
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 H02E0101
|
|
arc: B1 V00B0000
|
|
arc: B5 V02S0701
|
|
arc: B7 V01S0000
|
|
arc: C0 F4
|
|
arc: C1 E1_H02W0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V00B0100
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 V02S0001
|
|
arc: D5 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F3
|
|
arc: M4 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: S3_V06S0003 Q3
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0101010001010000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110100011011010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
word: SLICED.K0.INIT 1010000010100000
|
|
word: SLICED.K1.INIT 1001011100011001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R30C14:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A1 W1_H02E0701
|
|
arc: A5 V02N0101
|
|
arc: A7 H00L0000
|
|
arc: B1 F3
|
|
arc: B2 F3
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H02W0301
|
|
arc: C0 H00L0100
|
|
arc: C3 H02E0601
|
|
arc: C4 H02E0401
|
|
arc: C5 H02E0601
|
|
arc: C6 V00B0100
|
|
arc: C7 F4
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V02S0201
|
|
arc: D2 V01S0100
|
|
arc: D3 H00R0000
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 Q1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F3
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00B0100 Q7
|
|
word: SLICEB.K0.INIT 0011001100000000
|
|
word: SLICEB.K1.INIT 0000111100001100
|
|
word: SLICEC.K0.INIT 1111110011111111
|
|
word: SLICEC.K1.INIT 0000111000001111
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0010001011111111
|
|
word: SLICED.K0.INIT 0000111111110000
|
|
word: SLICED.K1.INIT 1010111100001111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R30C15:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: A0 V02S0501
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: B0 N1_V02S0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B6 H01E0101
|
|
arc: B7 V01S0000
|
|
arc: C0 W1_H02E0401
|
|
arc: C2 H00L0100
|
|
arc: C4 V02N0201
|
|
arc: C5 V00T0000
|
|
arc: C6 H02E0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V02S0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H01E0101
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q0
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0101 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEC.K0.INIT 1110110010100000
|
|
word: SLICEC.K1.INIT 0000010111110101
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0011001110111011
|
|
word: SLICED.K0.INIT 0011111100001111
|
|
word: SLICED.K1.INIT 0011001111001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R30C16:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A0 V02N0501
|
|
arc: A1 H00L0000
|
|
arc: A4 V00T0000
|
|
arc: A5 V00B0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B4 H01E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V02S0401
|
|
arc: C4 V00T0100
|
|
arc: C5 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 F0
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 W1_H02E0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 F0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000101000000000
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 0000111101010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R30C17:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A6 F7
|
|
arc: B6 V00B0100
|
|
arc: B7 E1_H02W0101
|
|
arc: C6 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 V02N0401
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F7
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F6
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0601 F6
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0100110001000100
|
|
word: SLICED.K1.INIT 0011001100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R30C18:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A4 V00T0000
|
|
arc: A5 H02E0701
|
|
arc: A6 H00L0000
|
|
arc: A7 H02E0701
|
|
arc: B4 E1_H02W0301
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 N1_V01S0000
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 F4
|
|
arc: C6 H02E0401
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02S0401
|
|
arc: D5 V02S0601
|
|
arc: D6 V02N0401
|
|
arc: D7 V00B0000
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 1000100011011101
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 1010111100000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R30C19:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 H02W0501
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 H02W0701
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H02W0701
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B4 H00L0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00B0100
|
|
arc: C0 H02W0401
|
|
arc: C1 V02S0601
|
|
arc: C2 H02W0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02N0201
|
|
arc: C5 F4
|
|
arc: C6 V02N0201
|
|
arc: C7 V02S0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 F0
|
|
arc: D2 V02N0201
|
|
arc: D3 F2
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 H02E0201
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H02E0301 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 Q5
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1000110110001101
|
|
word: SLICEB.K0.INIT 0001001101011111
|
|
word: SLICEB.K1.INIT 1010000011110101
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 1010000011110101
|
|
word: SLICEA.K0.INIT 0001010100111111
|
|
word: SLICEA.K1.INIT 1010000011110101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R30C20:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 H02E0701
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0101
|
|
arc: B0 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B4 S1_V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 V02N0401
|
|
arc: C2 V02S0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02N0201
|
|
arc: C5 F4
|
|
arc: C6 V02N0001
|
|
arc: C7 F6
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 F0
|
|
arc: D2 V02N0201
|
|
arc: D3 F2
|
|
arc: D4 V02S0401
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q1
|
|
word: SLICEB.K0.INIT 0001010100111111
|
|
word: SLICEB.K1.INIT 1010000011110101
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 1010101000001111
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 1100110000001111
|
|
word: SLICEA.K0.INIT 0001010100111111
|
|
word: SLICEA.K1.INIT 1010000010101111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R30C21:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R30C22:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 V02S0701
|
|
arc: B0 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: C0 V02S0401
|
|
arc: C1 N1_V01N0001
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: M2 V00T0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 F0
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1011111110000000
|
|
word: SLICEA.K1.INIT 1110010011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C23:PLC2
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: H01W0100 Q6
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R30C24:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R30C25:PLC2
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile R30C2:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R30C3:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: A1 W1_H02E0501
|
|
arc: B3 H02E0301
|
|
arc: C1 H02W0601
|
|
arc: C3 H00L0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: E3_H06E0103 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0103 F1
|
|
arc: V00T0100 F1
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R30C4:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A4 V00T0100
|
|
arc: B0 E1_H02W0301
|
|
arc: B4 V01S0000
|
|
arc: B5 H00L0000
|
|
arc: C0 H00L0000
|
|
arc: C1 V02N0401
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 S1_V02N0401
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0601 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
word: SLICEC.K0.INIT 1100110111001000
|
|
word: SLICEC.K1.INIT 1111110000001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R30C5:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 H02W0601
|
|
arc: M4 V00T0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0401 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R30C6:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A1 V02N0701
|
|
arc: A7 H02E0701
|
|
arc: B7 H02E0101
|
|
arc: C1 V02N0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 F1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1110101011000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111101001010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R30C7:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 V02N0501
|
|
arc: A3 V02N0501
|
|
arc: A5 H02E0501
|
|
arc: B5 H02E0101
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 N1_V02S0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02W0201
|
|
arc: D3 V02N0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H02W0001
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F1
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N3_V06N0003 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F1
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1100110010101010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111010110100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R30C8:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 W1_H02E0701
|
|
arc: B2 V02N0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B6 V02S0501
|
|
arc: C0 V02S0601
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D6 H02E0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 F7
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 F6
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
word: SLICED.K0.INIT 0000000100000000
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1010101110101000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R30C9:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 H02E0701
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 E1_H02W0301
|
|
arc: B5 V01S0000
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 E1_H02W0601
|
|
arc: C4 V02N0201
|
|
arc: C5 F4
|
|
arc: C6 H02E0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H00R0000
|
|
arc: D1 V00B0100
|
|
arc: D4 V02S0401
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02S0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q6
|
|
arc: N3_V06N0303 F5
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1010111110100000
|
|
word: SLICED.K1.INIT 1111000011100010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R31C10:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: A1 H02W0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A7 H00R0000
|
|
arc: B1 H02E0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C1 H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C6 H02W0401
|
|
arc: C7 F6
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00T0100
|
|
arc: D2 H02W0201
|
|
arc: D3 F2
|
|
arc: D6 H01W0000
|
|
arc: D7 V00B0000
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0401 F6
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1011101110001000
|
|
word: SLICEB.K1.INIT 0000101001011111
|
|
word: SLICED.K0.INIT 1111110000110000
|
|
word: SLICED.K1.INIT 0101010100001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111100010001000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R31C11:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 N1_V01S0100
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H02E0301
|
|
arc: B3 F1
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 H02W0301
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H00L0000
|
|
arc: C3 H02E0601
|
|
arc: C5 V00B0100
|
|
arc: C6 H02W0601
|
|
arc: C7 E1_H01E0101
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 W1_H02E0001
|
|
arc: D3 V02S0001
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 V02N0601
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100110010001100
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1110101011000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R31C12:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A7 V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: B3 H00L0000
|
|
arc: B4 H02E0301
|
|
arc: B5 V00B0100
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00T0100
|
|
arc: C7 E1_H01E0101
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 H00R0100
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S1_V02S0001 F0
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0501 Q7
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111000010101010
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R31C13:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A7 V02N0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 W1_H02E0101
|
|
arc: B3 V01N0001
|
|
arc: C0 H02E0401
|
|
arc: C3 F6
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00B0100
|
|
arc: D3 V02N0001
|
|
arc: D6 V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q6
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 F7
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1000011000111011
|
|
word: SLICEA.K1.INIT 1011101100110011
|
|
word: SLICED.K0.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 1111010101010101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0011111100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R31C14:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0303 V06N0303
|
|
arc: A1 H02E0701
|
|
arc: A2 V02S0701
|
|
arc: A7 H02W0701
|
|
arc: B1 V00B0000
|
|
arc: B2 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: B7 V02S0501
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C4 H02E0601
|
|
arc: C6 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V00T0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q1
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0001111100001111
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 0011001111001100
|
|
word: SLICED.K0.INIT 0000111111110000
|
|
word: SLICED.K1.INIT 1101110101010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R31C15:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A5 V02S0301
|
|
arc: A7 N1_V02S0101
|
|
arc: B2 V02N0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B5 V02N0501
|
|
arc: B7 V02S0701
|
|
arc: C4 V00B0100
|
|
arc: C7 V02S0201
|
|
arc: CE0 H02W0101
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 H02W0201
|
|
arc: D4 H02W0201
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q5
|
|
arc: E3_H06E0203 F7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00B0100 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0011001111001100
|
|
word: SLICEB.K1.INIT 0011001111001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1001000000001001
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 0100010011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R31C16:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 H00R0000
|
|
arc: A1 F5
|
|
arc: A5 V02S0101
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V02S0301
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 N1_V02S0101
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0501
|
|
arc: B7 H01E0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 V02S0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 H01E0001
|
|
arc: C7 V00T0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 F0
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D5 V00B0000
|
|
arc: D6 H02W0001
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 F7
|
|
arc: V01S0100 F2
|
|
word: SLICED.K0.INIT 1001011101000011
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0000111111110000
|
|
word: SLICEA.K0.INIT 1000001001000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R31C17:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: A0 H00R0000
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 H02E0501
|
|
arc: A3 F5
|
|
arc: A4 V02S0101
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 F3
|
|
arc: B3 H02E0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 V01S0000
|
|
arc: B7 V02N0701
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 V02S0401
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0401
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 V00B0100
|
|
arc: C7 E1_H02W0601
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 V00B0100
|
|
arc: D2 H02W0001
|
|
arc: D3 H02E0001
|
|
arc: D4 H02W0201
|
|
arc: D5 S1_V02N0601
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K0.INIT 0000111100010001
|
|
word: SLICEB.K1.INIT 0010111011001111
|
|
word: SLICEA.K0.INIT 1001000000001001
|
|
word: SLICEA.K1.INIT 1000001101101011
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111110000110000
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 1000011000111011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C18:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0701
|
|
arc: A6 N1_V02S0301
|
|
arc: B3 H00R0100
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B6 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: C3 H02W0401
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0201
|
|
arc: C7 V00B0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 H00R0000
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 H02E0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 F5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0203 F7
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICED.K0.INIT 1111111111001110
|
|
word: SLICED.K1.INIT 0011001100001111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 1000010101101101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C19:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 V02S0701
|
|
arc: A2 H00L0100
|
|
arc: A3 V02S0701
|
|
arc: A4 H02W0501
|
|
arc: A6 V02S0101
|
|
arc: B0 V01N0001
|
|
arc: B2 E1_H02W0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 H02W0301
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 N1_V02S0401
|
|
arc: C4 V02N0001
|
|
arc: C5 F4
|
|
arc: C6 V02N0001
|
|
arc: C7 F6
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 F0
|
|
arc: D2 V02N0001
|
|
arc: D3 F2
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H00R0100
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICEB.K0.INIT 0001001101011111
|
|
word: SLICEB.K1.INIT 1010000011110101
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1100110000001111
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 1100110000001111
|
|
word: SLICEA.K0.INIT 0001001101011111
|
|
word: SLICEA.K1.INIT 1010000011110101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R31C20:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 E1_H01W0000
|
|
arc: A6 V02S0101
|
|
arc: A7 W1_H02E0701
|
|
arc: B3 V02S0301
|
|
arc: B4 W1_H02E0301
|
|
arc: B6 H02E0301
|
|
arc: B7 V01S0000
|
|
arc: C3 H02W0401
|
|
arc: C4 H02W0601
|
|
arc: C6 N1_V02S0001
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 H02E0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 V02N0601
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 F7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0401 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0011000010111010
|
|
word: SLICED.K0.INIT 1111100010001000
|
|
word: SLICED.K1.INIT 1001011101000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C21:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C22:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 V02N0501
|
|
arc: A1 H02W0701
|
|
arc: B0 H02W0101
|
|
arc: B1 V02N0101
|
|
arc: C0 V02S0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 V01S0100
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0101 F1
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1110101011000000
|
|
word: SLICEA.K1.INIT 0010001001110111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R31C23:PLC2
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C24:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R31C2:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00B0100 V02S0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C3:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A7 E1_H02W0501
|
|
arc: B7 E1_H02W0301
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1110101011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R31C4:PLC2
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: B1 H02W0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0103 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R31C5:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A1 H00L0000
|
|
arc: A4 F5
|
|
arc: A5 V00T0000
|
|
arc: B0 F1
|
|
arc: B1 V00B0000
|
|
arc: B5 H00R0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 N1_V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H02W0201
|
|
arc: D5 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 F4
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0501 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 0000000100000000
|
|
word: SLICEC.K0.INIT 1010000010100000
|
|
word: SLICEC.K1.INIT 0000000000010000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R31C6:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A4 V00T0000
|
|
arc: B4 N1_V02S0701
|
|
arc: C4 H02E0601
|
|
arc: C5 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V00B0000
|
|
arc: D5 V02S0401
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0203 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M0 W1_H02E0601
|
|
arc: M2 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R31C7:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A2 H02E0501
|
|
arc: A6 H00R0000
|
|
arc: B1 V02S0301
|
|
arc: B3 V02S0101
|
|
arc: B5 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 N1_V02S0401
|
|
arc: C4 V01N0101
|
|
arc: C5 V02S0001
|
|
arc: C6 V00T0000
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D3 V02S0001
|
|
arc: D5 H02E0201
|
|
arc: D6 H01W0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1100111111000000
|
|
word: SLICED.K0.INIT 1100110010001100
|
|
word: SLICED.K1.INIT 1111111111110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R31C8:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A6 H02E0501
|
|
arc: A7 V02N0101
|
|
arc: B6 V01S0000
|
|
arc: B7 V00B0000
|
|
arc: C6 H02E0401
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 E1_H02W0001
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0000 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 0011101100001010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C9:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 H02W0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: W3_H06W0103 V06S0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H00L0100
|
|
arc: A1 E1_H01E0001
|
|
arc: A6 V02N0101
|
|
arc: B0 V02S0301
|
|
arc: B1 V02N0101
|
|
arc: B3 H02W0101
|
|
arc: B6 F3
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 V02N0601
|
|
arc: C2 H02E0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 S1_V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 F0
|
|
arc: D2 V02N0001
|
|
arc: D3 V02S0201
|
|
arc: D6 V02N0601
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0303 F6
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0100 F7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0011111000101110
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1111000011000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R32C10:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A4 H02E0501
|
|
arc: A5 V00T0000
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 V02N0301
|
|
arc: B4 H01E0101
|
|
arc: B5 V02S0701
|
|
arc: B6 V00B0100
|
|
arc: B7 V01S0000
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 F4
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 F6
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02S0401
|
|
arc: D5 V01N0001
|
|
arc: D6 V02S0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0303 Q5
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 1100111000001010
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 1010111000001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C11:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 E1_H02W0501
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00T0000
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 S1_V02N0201
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0101 F1
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
word: SLICEA.K1.INIT 0000000010000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C12:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0101
|
|
arc: A6 V02S0301
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V02S0701
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00T0100
|
|
arc: C6 S1_V02N0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 V02S0601
|
|
arc: D5 H00R0100
|
|
arc: D6 V02S0401
|
|
arc: D7 V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0203 Q7
|
|
arc: S1_V02S0001 F0
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111000010100000
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C13:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A1 H00R0000
|
|
arc: A5 N1_V01S0100
|
|
arc: B1 V02S0301
|
|
arc: B3 H01W0100
|
|
arc: B5 W1_H02E0301
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0100
|
|
arc: C6 Q6
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 V00T0100
|
|
arc: D6 H00L0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0301 F1
|
|
arc: E3_H06E0003 Q3
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q6
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 Q3
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 0011111100111111
|
|
word: SLICED.K0.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 0000000011110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0001000100010001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R32C14:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: A2 H02W0501
|
|
arc: A3 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 V02N0301
|
|
arc: A7 H02E0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 H00R0000
|
|
arc: B3 H00L0000
|
|
arc: B4 V02S0501
|
|
arc: B5 V00B0100
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0401 F6
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C15:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 H02E0501
|
|
arc: A1 V02S0701
|
|
arc: A2 H00L0100
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 H02E0301
|
|
arc: B6 V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0601 F6
|
|
arc: S3_V06S0203 F7
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C16:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: A0 V01N0101
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H02E0701
|
|
arc: A7 H00L0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B5 H00R0000
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 E1_H02W0101
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C17:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 H02W0701
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 H02E0701
|
|
arc: A7 V02S0101
|
|
arc: B0 V02S0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 H00L0000
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0101
|
|
arc: B6 V02N0701
|
|
arc: B7 V00T0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R32C18:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 F5
|
|
arc: A1 H00R0000
|
|
arc: A4 W1_H02E0501
|
|
arc: B0 V02N0301
|
|
arc: B1 N1_V02S0301
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 W1_H02E0301
|
|
arc: C5 V00T0000
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F6
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0101010110101010
|
|
word: SLICEC.K1.INIT 0000111111110000
|
|
word: SLICED.K0.INIT 0011001111001100
|
|
word: SLICED.K1.INIT 0011001111001100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R32C19:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 V01N0101
|
|
arc: A1 S1_V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A6 H02E0501
|
|
arc: A7 V02S0301
|
|
arc: B0 H00R0100
|
|
arc: B1 H02W0101
|
|
arc: B2 H02E0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0301
|
|
arc: B5 F1
|
|
arc: B6 V02N0501
|
|
arc: B7 V01S0000
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0100
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H02E0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C6 V02S0001
|
|
arc: C7 H02W0401
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 F2
|
|
arc: D2 H01E0101
|
|
arc: D3 F2
|
|
arc: D4 F0
|
|
arc: D6 V02S0401
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F3
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 0101100011111101
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0100001011100111
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1110001011010001
|
|
word: SLICEC.K1.INIT 0110011001100110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R32C20:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A0 H02E0501
|
|
arc: A1 F5
|
|
arc: A4 V02N0301
|
|
arc: A6 F5
|
|
arc: B0 H01W0100
|
|
arc: B1 F3
|
|
arc: B2 H00R0000
|
|
arc: B3 H01W0100
|
|
arc: B5 H02E0301
|
|
arc: B6 F3
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 H02E0401
|
|
arc: C3 H00L0000
|
|
arc: C4 H02E0401
|
|
arc: C5 V02S0201
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H01E0001
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 F0
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0201
|
|
arc: D5 V00B0000
|
|
arc: D6 F0
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: V00B0000 Q4
|
|
arc: W3_H06W0103 F1
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0001110100011101
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
word: SLICEC.K1.INIT 0000001111001111
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 0000110000111111
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0000110000111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R32C21:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 H02W0501
|
|
arc: A1 H00L0000
|
|
arc: A3 F5
|
|
arc: A4 V02N0101
|
|
arc: A5 H02E0501
|
|
arc: A6 E1_H02W0701
|
|
arc: B0 F1
|
|
arc: B1 V00T0000
|
|
arc: B2 H01W0100
|
|
arc: B3 H00L0000
|
|
arc: B4 H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: B7 V01S0000
|
|
arc: C0 F6
|
|
arc: C1 H02W0401
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V00T0100
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 V02N0001
|
|
arc: C7 V01N0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 H02E0001
|
|
arc: D2 V00B0100
|
|
arc: D3 F2
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0201
|
|
arc: D6 H00R0100
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F3
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 0000111100010001
|
|
word: SLICEA.K1.INIT 0101100011111101
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 0011100011111011
|
|
word: SLICEC.K0.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 1000001101101011
|
|
word: SLICED.K0.INIT 1111101000001010
|
|
word: SLICED.K1.INIT 0000111100110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R32C22:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: A0 H00L0100
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 F5
|
|
arc: A5 E1_H02W0701
|
|
arc: A7 H00L0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H02W0101
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: C0 H02W0401
|
|
arc: C1 V02N0401
|
|
arc: C2 H02E0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 V00T0100
|
|
arc: C6 H02E0401
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 F0
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 V02S0601
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 F3
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1101100011011000
|
|
word: SLICEA.K1.INIT 0011100011111011
|
|
word: SLICED.K0.INIT 1100110011110000
|
|
word: SLICED.K1.INIT 0011111110001011
|
|
word: SLICEC.K0.INIT 0010110011101111
|
|
word: SLICEC.K1.INIT 1001011101000011
|
|
word: SLICEB.K0.INIT 1110101011000000
|
|
word: SLICEB.K1.INIT 1000001101101011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C23:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A0 H02E0501
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 H02E0501
|
|
arc: A3 V02N0501
|
|
arc: A4 H02E0501
|
|
arc: B0 F1
|
|
arc: B1 H02E0301
|
|
arc: B2 V01N0001
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0301
|
|
arc: B7 V02N0701
|
|
arc: C0 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C4 H02E0401
|
|
arc: C5 V02N0001
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 V00B0100
|
|
arc: D2 H01E0101
|
|
arc: D3 H00R0000
|
|
arc: D4 H01W0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V02S0601
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0000001111001111
|
|
word: SLICEB.K0.INIT 0011000000110101
|
|
word: SLICEB.K1.INIT 0000101001011111
|
|
word: SLICEA.K0.INIT 0011000000110101
|
|
word: SLICEA.K1.INIT 1011101110001000
|
|
word: SLICEC.K0.INIT 0000000111001101
|
|
word: SLICEC.K1.INIT 0000001111001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R32C24:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A3 W1_H02E0701
|
|
arc: B3 V02N0301
|
|
arc: C3 V02N0601
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0001
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0101 Q3
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0011001100000101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R32C25:PLC2
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R32C2:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R32C3:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R32C4:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00B0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R32C5:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 E1_H02W0701
|
|
arc: B1 V01N0001
|
|
arc: C1 V02N0401
|
|
arc: D1 V02N0201
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C6:PLC2
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A6 H02E0501
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 W1_H02E0101
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 H02E0201
|
|
arc: D7 V00B0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 1111000011111100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R32C7:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0100
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B4 V02S0701
|
|
arc: B5 H02W0301
|
|
arc: B6 V01S0000
|
|
arc: B7 H02W0301
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0001
|
|
arc: C6 V00B0100
|
|
arc: C7 V02N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 H01W0000
|
|
arc: D6 H02W0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 Q2
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
arc: V01S0000 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 0101000011011100
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 1111010001000100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C8:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R32C9:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R33C10:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H02E0501
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A4 V02N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: B1 H02E0101
|
|
arc: B4 H01E0101
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 F4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V02S0401
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0103 Q1
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 1010111000001100
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1111000011100100
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R33C11:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: A2 V02N0501
|
|
arc: A3 V02S0501
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 V02N0301
|
|
arc: B7 V02N0701
|
|
arc: C2 H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02E0201
|
|
arc: D3 F2
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0203 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 F2
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000010
|
|
word: SLICEB.K1.INIT 0010000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R33C12:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02S0101
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: B2 V01N0001
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 H02E0101
|
|
arc: B7 V02S0701
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 V00T0000
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 V02N0201
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0001
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0203 Q7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100111011101110
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R33C13:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0203 H01E0001
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W3_H06W0103 V06S0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A5 V02N0301
|
|
arc: B1 E1_H01W0100
|
|
arc: B7 H02W0101
|
|
arc: C1 N1_V02S0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C7 E1_H02W0601
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D5 H02E0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q5
|
|
arc: S3_V06S0103 Q2
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R33C14:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 S1_V02N0701
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V00T0100
|
|
arc: B1 H02E0101
|
|
arc: B3 F1
|
|
arc: B7 V01S0000
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 F4
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 F4
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 H00R0100
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0103 F2
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K0.INIT 0000010110101111
|
|
word: SLICED.K1.INIT 1110111100000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000011101111
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 0000000001010101
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R33C15:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A5 V02N0101
|
|
arc: A7 H02E0501
|
|
arc: B2 F3
|
|
arc: C2 V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C5 V02N0201
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02S0001
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 H02W0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0501 F7
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F2
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F6
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0011111100111111
|
|
word: SLICEB.K1.INIT 1111111100001111
|
|
word: SLICED.K0.INIT 0000111111110000
|
|
word: SLICED.K1.INIT 0101010110101010
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R33C16:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A2 H00L0100
|
|
arc: A3 V02S0501
|
|
arc: A5 V02N0301
|
|
arc: A6 V02N0101
|
|
arc: A7 F5
|
|
arc: B2 E1_H02W0301
|
|
arc: B5 H02E0301
|
|
arc: B6 N1_V02S0701
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 V02S0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V02S0001
|
|
arc: C5 H02E0401
|
|
arc: C6 V02S0201
|
|
arc: C7 F6
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V00T0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 H02E0001
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F4
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: V00T0100 F3
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 0101100011111101
|
|
word: SLICEB.K1.INIT 1111000010101010
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0000111111110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R33C17:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A5 V00B0000
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B0 H02W0101
|
|
arc: B1 V02S0301
|
|
arc: B3 V02N0101
|
|
arc: B7 V02S0501
|
|
arc: C3 H00R0100
|
|
arc: C5 H02E0601
|
|
arc: C6 V02S0001
|
|
arc: CE1 H00L0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 H02W0001
|
|
arc: D5 N1_V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 F0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEA.K0.INIT 0011001111001100
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
word: SLICED.K0.INIT 0101101001011010
|
|
word: SLICED.K1.INIT 0110011001100110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R33C18:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H02W0501
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B1 H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 V02N0501
|
|
arc: B5 V02S0501
|
|
arc: C0 H02E0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 H00L0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 V00T0100
|
|
arc: D2 V01S0100
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0301 F1
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEA.K1.INIT 1001011100011001
|
|
word: SLICEC.K0.INIT 1110110010100000
|
|
word: SLICEC.K1.INIT 1001010001001111
|
|
word: SLICEB.K0.INIT 0001110101010101
|
|
word: SLICEB.K1.INIT 1111100010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C19:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0501
|
|
arc: A4 H02E0701
|
|
arc: A5 V00B0000
|
|
arc: A6 H02W0501
|
|
arc: A7 S1_V02N0101
|
|
arc: B2 V02S0301
|
|
arc: B3 H02W0301
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 V02S0501
|
|
arc: B6 V02N0701
|
|
arc: B7 N1_V02S0701
|
|
arc: C2 H00L0000
|
|
arc: C3 H02E0601
|
|
arc: C4 H01E0001
|
|
arc: C5 H02E0601
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 F6
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H00R0000
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 H02W0201
|
|
arc: D6 H00L0100
|
|
arc: D7 V02N0601
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q4
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0101 F3
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 1000011001011101
|
|
word: SLICEC.K0.INIT 1110110010100000
|
|
word: SLICEC.K1.INIT 1000011001011101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C20:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 H02E0501
|
|
arc: A1 V02S0501
|
|
arc: A2 N1_V02S0501
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 V02S0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 H01W0100
|
|
arc: B2 V02N0101
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 H02W0301
|
|
arc: B7 V02S0501
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 H02E0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00B0100
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 H00R0000
|
|
arc: D2 H02W0001
|
|
arc: D5 H01W0000
|
|
arc: D6 H00R0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: S1_V02S0501 F7
|
|
arc: S3_V06S0003 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K0.INIT 1111100010001000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEA.K1.INIT 1000001101101011
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1000011001011101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C21:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: A1 H02W0501
|
|
arc: A2 N1_V02S0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 V00B0000
|
|
arc: A6 H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0101
|
|
arc: B1 H02W0101
|
|
arc: B2 V02N0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H02E0301
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 S1_V02N0701
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 E1_H02W0401
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 V00B0100
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 F0
|
|
arc: D2 V02N0001
|
|
arc: D4 V02S0401
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0103 Q1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
word: SLICEA.K1.INIT 0011001100000101
|
|
word: SLICEB.K0.INIT 1111100010001000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1001011100100101
|
|
word: SLICEC.K0.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 1000010101101101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C22:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A0 V02S0501
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A5 V02S0301
|
|
arc: A6 V02N0101
|
|
arc: A7 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: B3 S1_V02N0101
|
|
arc: B5 H02E0101
|
|
arc: B7 H01E0101
|
|
arc: C0 V02N0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 F4
|
|
arc: C6 H02E0601
|
|
arc: C7 F6
|
|
arc: CE0 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 F0
|
|
arc: D2 V02S0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V02N0401
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 H02W0001
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F3
|
|
word: SLICED.K0.INIT 1111010110100000
|
|
word: SLICED.K1.INIT 0101111110001101
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 0110001011111011
|
|
word: SLICEB.K0.INIT 0000000000000101
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEC.K1.INIT 0101111110001101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R33C23:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A0 E1_H01E0001
|
|
arc: A5 W1_H02E0701
|
|
arc: B0 H02E0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H02E0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 H00R0000
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 V02S0401
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 F4
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V01S0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F2
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
word: SLICEA.K1.INIT 0000001111001111
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 0000001111001111
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
word: SLICEC.K1.INIT 0010111011001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R33C24:PLC2
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: A0 V02N0501
|
|
arc: A3 H02E0501
|
|
arc: A5 H02E0701
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 F1
|
|
arc: B1 W1_H02E0301
|
|
arc: B4 H02E0101
|
|
arc: B5 V02N0501
|
|
arc: B6 F3
|
|
arc: B7 V02N0501
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V02N0001
|
|
arc: C5 F4
|
|
arc: C6 V02N0001
|
|
arc: C7 F6
|
|
arc: CE0 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00T0100
|
|
arc: D3 V01S0100
|
|
arc: D4 V01N0001
|
|
arc: D5 V02N0401
|
|
arc: D6 V02S0601
|
|
arc: D7 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICEA.K0.INIT 0011000000110101
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 1111110000001100
|
|
word: SLICEC.K1.INIT 0000111100010001
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 0000111100010001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000010111110101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R33C25:PLC2
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
|
|
.tile R33C26:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R33C2:PLC2
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: A3 V00B0000
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 F0
|
|
arc: D3 E1_H02W0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M2 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 0011001100111111
|
|
word: SLICEA.K1.INIT 1111000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R33C3:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 V02S0701
|
|
arc: A2 H02E0701
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E3_H06E0003 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q6
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R33C4:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R33C5:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V02N0101
|
|
arc: A6 V02S0301
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B5 H00L0000
|
|
arc: B6 W1_H02E0101
|
|
arc: C5 H02E0601
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 V02N0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02S0601
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F6
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
word: SLICEC.K1.INIT 0001001101011111
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R33C6:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A7 N1_V01N0101
|
|
arc: B6 V02N0501
|
|
arc: B7 N1_V02S0501
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 0000011101110111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R33C7:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A4 F5
|
|
arc: A5 H02W0701
|
|
arc: A6 H02E0501
|
|
arc: A7 F5
|
|
arc: B4 V02N0501
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V02N0501
|
|
arc: B7 H01E0101
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 V02N0001
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 V02N0601
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F5
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1000100010001000
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
word: SLICED.K0.INIT 1000100010001000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R33C8:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: A0 V02S0501
|
|
arc: A3 H02E0701
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B3 H01W0100
|
|
arc: C0 V02N0601
|
|
arc: C3 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 F0
|
|
arc: D3 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1110101011000000
|
|
word: SLICEA.K0.INIT 0000000001000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R33C9:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R34C10:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: B1 V00B0000
|
|
arc: B4 V02N0501
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C4 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 E1_H02W0001
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M2 H02E0601
|
|
arc: M4 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1100110011001010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R34C11:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V02N0101
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: B5 V00B0100
|
|
arc: B7 H02W0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 H02W0401
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V02N0401
|
|
arc: D5 H02E0201
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F1
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V01N0101 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R34C12:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A1 H02E0501
|
|
arc: A5 N1_V02S0301
|
|
arc: B0 F1
|
|
arc: B1 H02E0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 H00L0000
|
|
arc: C1 S1_V02N0601
|
|
arc: C3 H00L0100
|
|
arc: C5 S1_V02N0001
|
|
arc: C7 W1_H02E0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0001
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 V02S0201
|
|
arc: D5 V02S0601
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F1
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 0111010101000101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1100110000001111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000001010101
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R34C13:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A4 V02N0101
|
|
arc: A5 E1_H02W0701
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 V00B0100
|
|
arc: B5 H00L0000
|
|
arc: B7 V02N0501
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 H02E0401
|
|
arc: C5 V00T0100
|
|
arc: C7 E1_H02W0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 V02N0401
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0000
|
|
arc: N3_V06N0203 F7
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100000011001111
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R34C14:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 V00B0000
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H00R0000
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: B5 H00L0000
|
|
arc: B6 V00B0100
|
|
arc: B7 V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V01N0101
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V02S0201
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 H00L0100
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 N1_V02S0401
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F2
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00B0100 Q7
|
|
word: SLICED.K0.INIT 0100010011101100
|
|
word: SLICED.K1.INIT 1111111110101110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R34C15:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V00B0000
|
|
arc: A6 V02S0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: B5 V02S0701
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00B0100
|
|
arc: C7 F6
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 H02W0201
|
|
arc: D5 V02N0401
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R34C16:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V00T0000
|
|
arc: A6 H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B0 H00R0100
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H02W0301
|
|
arc: B7 V02S0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 V00T0100
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 W1_H02E0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0401
|
|
arc: D5 V01N0001
|
|
arc: D6 V02S0601
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 F1
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000101
|
|
word: SLICED.K1.INIT 1010110010101100
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R34C17:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A1 V02N0701
|
|
arc: A2 V02S0501
|
|
arc: A5 V02S0301
|
|
arc: A6 F7
|
|
arc: B2 H02E0301
|
|
arc: B3 V01N0001
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02S0701
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 V00T0000
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D3 H00R0000
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 H01W0000
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q5
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 0000000000000100
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R34C18:PLC2
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: B0 H01W0100
|
|
arc: B1 H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B3 H01W0100
|
|
arc: B4 V02N0501
|
|
arc: B5 H02E0301
|
|
arc: B7 F3
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00B0100
|
|
arc: C5 V02N0201
|
|
arc: C7 H02E0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0201
|
|
arc: D4 V02N0401
|
|
arc: D5 W1_H02E0001
|
|
arc: D7 H01W0000
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0003 F0
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R34C19:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0000
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: B5 H00R0000
|
|
arc: B7 H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00B0100
|
|
arc: C7 V00T0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 V02N0401
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R34C20:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0100
|
|
arc: B0 H00R0100
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 V01N0101
|
|
arc: C5 V00B0100
|
|
arc: C7 H01E0001
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 V02N0401
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F1
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0100 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R34C21:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V00B0000
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B7 H02E0301
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00B0100
|
|
arc: C7 H02E0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H00L0100
|
|
arc: D7 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R34C22:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: A2 E1_H02W0501
|
|
arc: A6 H02E0701
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0301
|
|
arc: B6 H02E0301
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 H02E0601
|
|
arc: C6 V00T0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D2 W1_H02E0201
|
|
arc: D6 H02E0201
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1110110010100000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R34C23:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 F5
|
|
arc: A3 F5
|
|
arc: A5 H02E0701
|
|
arc: A7 V02N0101
|
|
arc: B1 V02S0301
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0501
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: C3 F4
|
|
arc: C5 H02E0601
|
|
arc: C6 S1_V02N0001
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 S1_V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: V00B0100 F7
|
|
arc: W3_H06W0103 F1
|
|
word: SLICED.K0.INIT 0000000000000011
|
|
word: SLICED.K1.INIT 0101010100000000
|
|
word: SLICEC.K0.INIT 0000000000110011
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0101111111111111
|
|
word: SLICEA.K1.INIT 0001001100110011
|
|
word: SLICEB.K0.INIT 0101111111111111
|
|
word: SLICEB.K1.INIT 0101111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R34C24:PLC2
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A4 H02E0501
|
|
arc: A5 V02N0101
|
|
arc: C4 V02S0001
|
|
arc: C5 F4
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02N0601
|
|
arc: D5 H02W0001
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F5
|
|
arc: N3_V06N0103 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000101001011111
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R34C25:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R34C2:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: A3 E1_H01E0001
|
|
arc: D3 V00B0100
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R34C3:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B6 V01S0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0301 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0701 Q5
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R34C4:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R34C5:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A4 F5
|
|
arc: A5 H02E0701
|
|
arc: A6 F7
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B5 H02E0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0001
|
|
arc: C6 H02E0601
|
|
arc: C7 F4
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H00R0100
|
|
arc: D5 H00L0100
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0000 F6
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEC.K0.INIT 1010000000001010
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 1111101011110000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R34C6:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A1 H01E0001
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V00T0100
|
|
arc: B0 F1
|
|
arc: B1 V02N0301
|
|
arc: B6 V01S0000
|
|
arc: B7 W1_H02E0101
|
|
arc: C1 N1_V01S0100
|
|
arc: C6 V02N0201
|
|
arc: C7 F6
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 N1_V01S0000
|
|
arc: D6 H00R0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1110101010101010
|
|
word: SLICED.K1.INIT 1111111100010000
|
|
word: SLICEA.K0.INIT 1100110011111111
|
|
word: SLICEA.K1.INIT 1111111110000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R34C7:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A1 H00L0000
|
|
arc: A2 N1_V02S0501
|
|
arc: A6 H02E0701
|
|
arc: A7 E1_H02W0701
|
|
arc: B1 H02E0301
|
|
arc: B2 E1_H01W0100
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0100
|
|
arc: C1 V02S0401
|
|
arc: C3 W1_H02E0601
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 H02W0401
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0201
|
|
arc: D2 V00T0100
|
|
arc: D3 H00R0000
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F6
|
|
arc: M0 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0000 F2
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0101 F3
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 0000000001000000
|
|
word: SLICED.K0.INIT 0010101010101010
|
|
word: SLICED.K1.INIT 1110110010100000
|
|
word: SLICEB.K0.INIT 0011001101110111
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R34C8:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 H00L0000
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 W1_H02E0701
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 F3
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 F6
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 F6
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D4 F2
|
|
arc: D5 V02S0601
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 F3
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0501 F7
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000010111111
|
|
word: SLICEC.K0.INIT 1111111100000100
|
|
word: SLICEC.K1.INIT 1110110000000000
|
|
word: SLICEB.K0.INIT 0111000011110000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0001000000000000
|
|
word: SLICED.K1.INIT 1110110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R34C9:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0303 Q6
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R35C10:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q4
|
|
arc: LSR1 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R35C11:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0303 V06N0303
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R35C12:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0000
|
|
arc: M2 H02E0601
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R35C13:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A0 S1_V02N0501
|
|
arc: A5 F7
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 H02E0101
|
|
arc: B1 V00T0000
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 V02S0501
|
|
arc: C0 V02N0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 N1_V02S0201
|
|
arc: C6 V00T0100
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 V01S0100
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0000 F4
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F7
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 F7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0011000000000000
|
|
word: SLICED.K1.INIT 0000000000010011
|
|
word: SLICEA.K0.INIT 0001000000110000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 0000111100001111
|
|
word: SLICEC.K1.INIT 0101011101110111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R35C14:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V00B0000
|
|
arc: A6 N1_V02S0301
|
|
arc: B0 S1_V02N0301
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0201 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q5
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICED.K1.INIT 1111111111110000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R35C15:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A5 N1_V01S0100
|
|
arc: A7 H02E0701
|
|
arc: B3 V02S0101
|
|
arc: B6 H02E0101
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V02S0201
|
|
arc: C6 H01E0001
|
|
arc: C7 H02E0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H02W0201
|
|
arc: D6 H00R0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 Q3
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N3_V06N0303 Q5
|
|
word: SLICED.K0.INIT 1111000011001100
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101000001010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R35C16:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0103 V06N0103
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: A2 V02S0701
|
|
arc: A3 V02S0701
|
|
arc: A4 V00T0100
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0501
|
|
arc: B5 N1_V02S0701
|
|
arc: B7 F3
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V02N0001
|
|
arc: C7 V02S0201
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 V02S0001
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 H00R0100
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C17:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A5 V00T0000
|
|
arc: A6 V02N0101
|
|
arc: B1 V02S0101
|
|
arc: B3 H02E0301
|
|
arc: B5 V02N0701
|
|
arc: B6 H02W0301
|
|
arc: C1 N1_V02S0401
|
|
arc: C3 H00L0000
|
|
arc: C6 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D5 V02S0401
|
|
arc: D6 H00L0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0701 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0701 Q5
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K0.INIT 1110110010100000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1101110110001000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R35C18:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 F5
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V01N0001
|
|
arc: B1 F3
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0301
|
|
arc: B5 V02N0701
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V00B0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 W1_H02E0601
|
|
arc: C3 V02N0401
|
|
arc: C4 V01N0101
|
|
arc: C5 H02E0401
|
|
arc: C6 V02N0201
|
|
arc: C7 F6
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V02S0001
|
|
arc: D1 V02N0201
|
|
arc: D3 H02E0201
|
|
arc: D5 V02N0401
|
|
arc: D6 V00B0000
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q7
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 0011001100000101
|
|
word: SLICEA.K1.INIT 0011101011110011
|
|
word: SLICED.K0.INIT 0101111111000101
|
|
word: SLICED.K1.INIT 0000000111001101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 0011000000110000
|
|
word: SLICEC.K1.INIT 1001010001001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R35C19:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: A0 V01N0101
|
|
arc: A1 H02E0501
|
|
arc: A3 V00B0000
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H02E0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 H02E0301
|
|
arc: C1 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 W1_H02E0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 V00B0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D5 H02E0201
|
|
arc: D6 V02S0601
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: V00B0000 Q6
|
|
arc: V00T0100 F1
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1110111001000100
|
|
word: SLICEA.K1.INIT 0101010100001111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R35C20:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0103 V06N0103
|
|
arc: A0 H01E0001
|
|
arc: A1 N1_V02S0501
|
|
arc: A3 H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 F1
|
|
arc: B1 W1_H02E0101
|
|
arc: B6 V00B0100
|
|
arc: B7 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 V02S0201
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0001
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 V02S0201
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0201
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101000001010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 0101010100000011
|
|
word: SLICEA.K1.INIT 0011101011110011
|
|
word: SLICED.K0.INIT 1111100010001000
|
|
word: SLICED.K1.INIT 1001001001110101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C21:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 H02E0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B1 W1_H02E0101
|
|
arc: B4 V00B0100
|
|
arc: B5 W1_H02E0301
|
|
arc: B7 V02S0701
|
|
arc: C1 V02S0401
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 V01N0101
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V01S0100
|
|
arc: D3 V02S0201
|
|
arc: D4 H02E0201
|
|
arc: D5 V00B0000
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEB.K0.INIT 1111101001010000
|
|
word: SLICEB.K1.INIT 0000101001011111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1110111000100010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 1001001000101111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C22:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: A1 V02N0701
|
|
arc: A2 F7
|
|
arc: A4 H02W0701
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 F1
|
|
arc: B2 F3
|
|
arc: B3 V02N0101
|
|
arc: B5 V02N0501
|
|
arc: B6 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00R0100
|
|
arc: C2 V02N0401
|
|
arc: C3 V02S0401
|
|
arc: C4 V02N0001
|
|
arc: C5 N1_V02S0001
|
|
arc: C6 V00T0000
|
|
arc: C7 W1_H02E0401
|
|
arc: CE1 H00L0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 H02E0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 F2
|
|
arc: D6 H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0101 Q3
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 0101000001011111
|
|
word: SLICEB.K0.INIT 0011101011110011
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
word: SLICEC.K1.INIT 0101000001010011
|
|
word: SLICED.K0.INIT 1110110010100000
|
|
word: SLICED.K1.INIT 1001010001110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C23:PLC2
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: A0 W1_H02E0501
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 H02E0501
|
|
arc: B0 F1
|
|
arc: B1 H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 N1_V02S0501
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H02E0601
|
|
arc: C3 H02E0401
|
|
arc: C4 H01E0001
|
|
arc: C5 W1_H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D3 V00B0100
|
|
arc: D4 F0
|
|
arc: D5 V00B0000
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000110000011101
|
|
word: SLICEC.K1.INIT 0000001111001111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000010110101111
|
|
word: SLICEA.K0.INIT 0011101011110011
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R35C24:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R35C25:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
|
|
.tile R35C26:PLC2
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R35C2:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0100 V02S0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R35C3:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A2 V02S0701
|
|
arc: A3 V02N0501
|
|
arc: A5 V00T0100
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 H02E0301
|
|
arc: C2 V02S0601
|
|
arc: C3 V02S0601
|
|
arc: C4 H02E0401
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02S0001
|
|
arc: D3 V02N0201
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0303 Q6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0011000000110000
|
|
word: SLICEC.K1.INIT 0001010100111111
|
|
word: SLICEB.K0.INIT 1000010000100001
|
|
word: SLICEB.K1.INIT 0000100010001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C4:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0501
|
|
arc: A5 H02E0701
|
|
arc: A6 H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 H02E0101
|
|
arc: B5 H00L0000
|
|
arc: B6 V02S0701
|
|
arc: B7 V00B0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 V02N0201
|
|
arc: C6 H02E0401
|
|
arc: C7 W1_H02E0601
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 V01N0001
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0701 F5
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 0111111111111111
|
|
word: SLICEC.K0.INIT 0011001100000000
|
|
word: SLICEC.K1.INIT 0010101000000000
|
|
word: SLICED.K0.INIT 1100001101000001
|
|
word: SLICED.K1.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R35C5:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0701
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V02S0101
|
|
arc: A5 V02N0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B1 H02E0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 V02N0701
|
|
arc: B5 H01E0101
|
|
arc: B6 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C1 F6
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 F4
|
|
arc: C6 H02E0601
|
|
arc: C7 H02E0601
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H00L0100
|
|
arc: D5 N1_V02S0401
|
|
arc: D6 H02W0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 F2
|
|
arc: M0 H01E0001
|
|
arc: M2 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: V01S0000 F0
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 0100000011000000
|
|
word: SLICEB.K0.INIT 0000010000000001
|
|
word: SLICEB.K1.INIT 0000100000000010
|
|
word: SLICED.K0.INIT 0000000000001001
|
|
word: SLICED.K1.INIT 0000100100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R35C6:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A1 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 F5
|
|
arc: B1 H02E0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 V02N0001
|
|
arc: C6 H02W0401
|
|
arc: C7 F6
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0201
|
|
arc: D4 V02S0601
|
|
arc: D5 V00B0000
|
|
arc: D6 H02W0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0701 F7
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 F4
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0000 F4
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0401 F4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 0010000010100000
|
|
word: SLICEC.K0.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 0001001101011111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0010001011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R35C7:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A0 H00L0000
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V02N0701
|
|
arc: A3 E1_H02W0501
|
|
arc: A7 V02N0301
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 V00B0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0401
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 H01E0001
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 F0
|
|
arc: D2 H02E0001
|
|
arc: D3 V00T0100
|
|
arc: D6 H01W0000
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0001010100111111
|
|
word: SLICEA.K1.INIT 0101000001010011
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R35C8:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: A1 V02S0501
|
|
arc: B1 H02E0301
|
|
arc: C1 H02E0401
|
|
arc: D1 H01E0101
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H01E0001
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111110
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R35C9:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 V02N0501
|
|
arc: A7 H02E0701
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0301
|
|
arc: B7 V02S0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 V02N0401
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 F0
|
|
arc: D7 V02S0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0001001101011111
|
|
word: SLICEA.K1.INIT 1111110011111110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0100010011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R36C10:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R36C11:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A3 V02N0501
|
|
arc: B3 H00R0000
|
|
arc: C3 N1_V01S0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V02N0201
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1110110010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R36C12:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: V00B0000 V02S0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0000 Q6
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R36C13:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V02S0701
|
|
arc: A5 H02W0501
|
|
arc: A6 H02E0701
|
|
arc: A7 E1_H02W0501
|
|
arc: B3 H01W0100
|
|
arc: B5 H00R0000
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C2 F6
|
|
arc: C4 V00T0100
|
|
arc: C5 V02S0001
|
|
arc: C7 F6
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V02S0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H02W0001
|
|
arc: D6 V02S0601
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F2
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F5
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0303 F5
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K0.INIT 0100010000000000
|
|
word: SLICED.K1.INIT 0000010101000101
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 0000010000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 1010000011110000
|
|
word: SLICEB.K1.INIT 0011001111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R36C14:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A1 N1_V02S0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A7 H02E0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02S0301
|
|
arc: B3 Q3
|
|
arc: B4 H02W0101
|
|
arc: B5 V02S0501
|
|
arc: B7 F1
|
|
arc: C0 H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C2 V02S0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C7 V02S0001
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 F0
|
|
arc: D2 H02E0201
|
|
arc: D3 F2
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 F4
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M4 V00T0100
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000001000000000
|
|
word: SLICEC.K0.INIT 1100000001000000
|
|
word: SLICEC.K1.INIT 0000111111001111
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
word: SLICEA.K1.INIT 0000000000010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R36C15:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 H02W0501
|
|
arc: A1 V02S0501
|
|
arc: A3 H00L0100
|
|
arc: A4 F5
|
|
arc: A5 W1_H02E0501
|
|
arc: B0 F1
|
|
arc: B2 V02N0301
|
|
arc: B3 H00R0000
|
|
arc: B4 H02E0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 H02W0601
|
|
arc: C3 V02S0601
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V00T0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D5 H02E0201
|
|
arc: D6 V00B0000
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F7
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0111011101110111
|
|
word: SLICEC.K1.INIT 1111111101011111
|
|
word: SLICEB.K0.INIT 1111110000000000
|
|
word: SLICEB.K1.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 0001001100000000
|
|
word: SLICEA.K1.INIT 0000000000001010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R36C16:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A4 F5
|
|
arc: A7 V02N0101
|
|
arc: B1 H01W0100
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 E1_H02W0101
|
|
arc: C1 V02N0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02S0201
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 H02W0401
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 H00R0000
|
|
arc: D3 N1_V02S0201
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0201
|
|
arc: D7 V02S0401
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M0 H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 F5
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1100000011001111
|
|
word: SLICEC.K0.INIT 0011001100000101
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000111110101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R36C17:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A1 E1_H01E0001
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: B1 H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 N1_V02S0501
|
|
arc: C2 V02N0401
|
|
arc: C4 V00T0000
|
|
arc: C5 S1_V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1010101000110011
|
|
word: SLICEC.K0.INIT 0000110011111100
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0101010110101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R36C18:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A1 V02N0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 F1
|
|
arc: B3 V02N0101
|
|
arc: B5 F1
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 V02N0401
|
|
arc: C5 V00T0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 V02N0201
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 F3
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 0000010111110101
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0011001111001100
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1101110110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R36C19:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: A1 V02N0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0100
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 V02S0301
|
|
arc: B1 V00T0000
|
|
arc: B4 V01S0000
|
|
arc: B5 H00L0000
|
|
arc: B7 V00B0000
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C4 V02S0201
|
|
arc: C5 F4
|
|
arc: C6 V02N0201
|
|
arc: C7 V00T0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F3
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0501 F7
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K0.INIT 0110001011111011
|
|
word: SLICEC.K1.INIT 0100010001000111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0100011100000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICED.K0.INIT 1010111100000000
|
|
word: SLICED.K1.INIT 1111110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R36C20:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0303 H01E0101
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A0 H01E0001
|
|
arc: A1 V02N0701
|
|
arc: A2 H01E0001
|
|
arc: A3 H02E0701
|
|
arc: A4 E1_H02W0501
|
|
arc: B0 F1
|
|
arc: B2 F3
|
|
arc: B4 H02W0301
|
|
arc: C1 V02N0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00B0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V02S0201
|
|
arc: D4 H00R0100
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 Q4
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
arc: V00T0100 F1
|
|
arc: W1_H02W0001 F0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1101110110001000
|
|
word: SLICEB.K1.INIT 0000111101010101
|
|
word: SLICEA.K0.INIT 1101110110001000
|
|
word: SLICEA.K1.INIT 0000010110101111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R36C21:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H00L0000
|
|
arc: A1 V02S0701
|
|
arc: A4 N1_V02S0301
|
|
arc: A6 N1_V02S0301
|
|
arc: B0 H02E0301
|
|
arc: B1 H02W0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 V02N0501
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 H02W0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C6 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 H02E0001
|
|
arc: D4 H00R0100
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00T0100 F1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1110110010100000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0101000001010011
|
|
word: SLICEA.K1.INIT 0011100011111011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R36C22:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q6
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00B0000 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R36C23:PLC2
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: H01W0000 Q4
|
|
arc: M0 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R36C24:PLC2
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
|
|
.tile R36C25:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
|
|
.tile R36C2:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: M2 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R36C3:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: A1 V02S0501
|
|
arc: A7 H00R0000
|
|
arc: B1 H01W0100
|
|
arc: B7 V02S0701
|
|
arc: C1 V02S0601
|
|
arc: C7 V02N0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000011101110111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100001101000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R36C4:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 H02W0101
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 V02S0101
|
|
arc: A7 E1_H02W0501
|
|
arc: B1 H02W0101
|
|
arc: B3 V02N0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H00R0000
|
|
arc: C1 V02N0601
|
|
arc: C3 H00L0000
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 W1_H02E0401
|
|
arc: C7 V00T0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 V00T0100
|
|
arc: D5 H02E0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H02E0601 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F1
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N3_V06N0203 Q7
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEC.K0.INIT 1100000011000000
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0001010100111111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0001001101011111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0101010111110101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R36C5:PLC2
|
|
arc: E3_H06E0103 V06N0103
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A0 V02S0701
|
|
arc: A1 H00L0000
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 W1_H02E0501
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 N1_V02S0101
|
|
arc: B4 V01S0000
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 F1
|
|
arc: C1 V02S0601
|
|
arc: C4 H02E0401
|
|
arc: C5 F4
|
|
arc: C7 H02E0601
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D4 H00R0100
|
|
arc: D5 V02S0401
|
|
arc: D7 F0
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1000100010001000
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 0010000010100000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111111111111011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R36C6:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V02N0301
|
|
arc: A7 H02E0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B4 V02N0701
|
|
arc: B5 W1_H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C1 V02S0401
|
|
arc: C4 V02N0201
|
|
arc: C5 H02E0601
|
|
arc: C7 H02W0401
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 F0
|
|
arc: D4 V02N0601
|
|
arc: D5 V00B0000
|
|
arc: D7 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M2 H02W0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0000 F4
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0101000011111111
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1111010111111101
|
|
word: SLICEA.K0.INIT 1000001011000011
|
|
word: SLICEA.K1.INIT 1100001100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R36C7:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A2 H00L0100
|
|
arc: A3 E1_H02W0501
|
|
arc: A7 E1_H01W0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02S0101
|
|
arc: B7 V02S0501
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H02W0601
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02S0001
|
|
arc: D3 V02N0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0601 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M4 H02E0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0001010100111111
|
|
word: SLICEB.K1.INIT 0000100000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R36C8:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A3 V02S0501
|
|
arc: A4 V02N0101
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V02N0101
|
|
arc: B3 V02S0301
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: B7 V02S0501
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V02S0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 H02E0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V00B0000
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F6
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F2
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
arc: V00B0000 F4
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0101000001010000
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 0111011100000111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R36C9:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A3 V02N0501
|
|
arc: B3 H00L0000
|
|
arc: C3 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 H02E0201
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0101 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000010011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R38C10:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A1 V02S0701
|
|
arc: A3 V01N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B2 V02N0301
|
|
arc: B3 E1_H01W0100
|
|
arc: B6 V02S0501
|
|
arc: B7 V02N0501
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H02E0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C6 H02W0601
|
|
arc: C7 F6
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02W0201
|
|
arc: D3 F2
|
|
arc: D6 N1_V02S0401
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0701 F7
|
|
arc: N3_V06N0103 F2
|
|
arc: S3_V06S0103 F2
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0001 F2
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 0111000001110111
|
|
word: SLICEB.K0.INIT 0000001100000011
|
|
word: SLICEB.K1.INIT 1011001110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R38C11:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A4 F5
|
|
arc: A7 E1_H01W0000
|
|
arc: B4 V02N0701
|
|
arc: B7 V00T0000
|
|
arc: C4 H02E0601
|
|
arc: C5 H02W0601
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V01N0001
|
|
arc: D5 H02W0001
|
|
arc: D7 V02S0601
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0303 F5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F5
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R38C12:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: H00L0100 H02E0301
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q6
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R38C13:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A7 V02N0301
|
|
arc: B7 S1_V02N0701
|
|
arc: C7 E1_H02W0401
|
|
arc: D7 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0003 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R38C14:PLC2
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A1 S1_V02N0701
|
|
arc: A5 N1_V02S0301
|
|
arc: A7 V00T0100
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 F3
|
|
arc: B4 H02W0101
|
|
arc: B7 V01S0000
|
|
arc: C1 V02N0601
|
|
arc: C3 V02N0401
|
|
arc: C5 F4
|
|
arc: C7 V02S0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 H00R0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 F4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEC.K1.INIT 0000101000000000
|
|
word: SLICEB.K0.INIT 1100110011111111
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
word: SLICED.K1.INIT 1010111010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R38C15:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 H02W0501
|
|
arc: A4 V02S0301
|
|
arc: A5 V00T0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 H00R0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C4 H02W0601
|
|
arc: C5 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D4 H02W0201
|
|
arc: D5 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0601 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0001010101010101
|
|
word: SLICEA.K1.INIT 0011111111111111
|
|
word: SLICEC.K0.INIT 0000000100000000
|
|
word: SLICEC.K1.INIT 0001010100111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R38C16:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H02W0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 N1_V01S0100
|
|
arc: B0 H02E0301
|
|
arc: B3 H01W0100
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0301
|
|
arc: C0 N1_V02S0601
|
|
arc: C3 H02E0401
|
|
arc: C5 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D2 V00B0100
|
|
arc: D3 H02W0001
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0000
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q2
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1111111011001100
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1100000011001111
|
|
word: SLICEC.K0.INIT 0001000100000000
|
|
word: SLICEC.K1.INIT 0000000011100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R38C17:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A4 S1_V02N0301
|
|
arc: A6 S1_V02N0301
|
|
arc: B4 V02N0501
|
|
arc: C4 V01N0101
|
|
arc: C5 V01N0101
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 F3
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: N3_V06N0003 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEC.K0.INIT 0111111111111111
|
|
word: SLICEC.K1.INIT 0000111111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0101010111111111
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R38C18:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00B0000 V02S0001
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B3 N1_V02S0301
|
|
arc: C0 N1_V02S0601
|
|
arc: C3 H00L0000
|
|
arc: C5 V02S0201
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q7
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111101001010000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111010110100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R38C19:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: A1 V02N0501
|
|
arc: A2 H02E0501
|
|
arc: B0 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B5 H02W0301
|
|
arc: C0 V02S0401
|
|
arc: C2 N1_V01S0100
|
|
arc: C5 V02S0201
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0201
|
|
arc: D1 V01S0100
|
|
arc: D2 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00T0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1101110011001100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111001111110000
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000110000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R38C20:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A4 V02S0301
|
|
arc: B4 H02E0101
|
|
arc: C4 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H00L0100
|
|
arc: F4 F5C_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: W1_H02W0601 Q6
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R38C21:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A0 V01N0101
|
|
arc: A6 H00R0000
|
|
arc: B0 V02S0301
|
|
arc: B6 W1_H02E0101
|
|
arc: C0 V02S0601
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D6 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1110110010100000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R38C22:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: A0 S1_V02N0701
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 V02S0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: E1_H02E0401 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1110101011000000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R38C23:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: V00B0100 H02E0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R38C24:PLC2
|
|
arc: V00T0000 H02W0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00B0000 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R38C25:PLC2
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
|
|
.tile R38C2:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R38C3:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A3 E1_H01E0001
|
|
arc: A7 V02N0301
|
|
arc: B1 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B7 V01S0000
|
|
arc: C3 V02N0601
|
|
arc: C7 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D3 H02W0201
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0103 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F1
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R38C4:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A2 V02N0701
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V02N0301
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: CE1 V02S0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R38C5:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R38C6:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 V02N0101
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B5 H00L0000
|
|
arc: B6 H02E0301
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 V01N0001
|
|
arc: D6 H02E0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1100001101000001
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R38C7:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02W0201
|
|
arc: A3 F5
|
|
arc: A4 F5
|
|
arc: B4 W1_H02E0301
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V02N0401
|
|
arc: D5 V00B0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0303 F5
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R38C8:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q4
|
|
arc: LSR1 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R38C9:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: A0 V02N0701
|
|
arc: A2 V02S0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V02N0301
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 V01N0001
|
|
arc: B2 F3
|
|
arc: B4 H01E0101
|
|
arc: B5 E1_H02W0301
|
|
arc: C0 H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C3 V02N0601
|
|
arc: C4 H02E0601
|
|
arc: C5 F4
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 V02S0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V00T0100
|
|
arc: D4 H02E0201
|
|
arc: D5 N1_V02S0601
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F0
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1111111101011101
|
|
word: SLICEB.K0.INIT 0001000100000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 0001001100110011
|
|
word: SLICEA.K1.INIT 1111111100111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R39C10:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A4 F5
|
|
arc: B0 F1
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0501
|
|
arc: C2 H02E0401
|
|
arc: C3 H00L0000
|
|
arc: C4 H02E0601
|
|
arc: C5 V02S0001
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D3 V02S0201
|
|
arc: D4 F0
|
|
arc: D6 V00B0000
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F2
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 F7
|
|
arc: N3_V06N0003 F3
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 1111111110000000
|
|
word: SLICEC.K1.INIT 1100000011000000
|
|
word: SLICED.K0.INIT 0000000011001100
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000110000001100
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R39C11:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A2 V02S0701
|
|
arc: A5 H02E0701
|
|
arc: A6 H00L0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B2 V02S0101
|
|
arc: B4 V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00B0100
|
|
arc: B7 H02E0101
|
|
arc: C2 V02N0601
|
|
arc: C5 F4
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 F6
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H01E0101
|
|
arc: D4 V00B0000
|
|
arc: D5 V02S0601
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0501 F5
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0401 F4
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0111111111111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 1000111110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C12:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: A2 V01N0101
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: A6 V02N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B4 H00R0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F2
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0303 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K0.INIT 0011001100110000
|
|
word: SLICEC.K1.INIT 0101010101010000
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0101010101010000
|
|
word: SLICEB.K1.INIT 0101010101010000
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICED.K1.INIT 1111111111110000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R39C13:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A7 W1_H02E0501
|
|
arc: B6 N1_V01S0000
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 H01W0000
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0101 Q7
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0203 Q7
|
|
arc: W1_H02W0001 Q2
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000110011
|
|
word: SLICED.K1.INIT 0101010101010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R39C14:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: B0 V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B7 V02N0501
|
|
arc: C1 V02S0601
|
|
arc: C2 V02N0401
|
|
arc: C5 H02W0601
|
|
arc: C7 N1_V02S0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V01S0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00T0100
|
|
arc: D5 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F1
|
|
arc: S1_V02S0201 F0
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K0.INIT 1111111100110011
|
|
word: SLICEA.K1.INIT 0000000000110000
|
|
word: SLICEB.K0.INIT 0000001100000000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000111111111111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R39C15:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A1 V02N0701
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 H02E0701
|
|
arc: B1 V01N0001
|
|
arc: B5 H02E0101
|
|
arc: B6 V01S0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C5 V00T0000
|
|
arc: C6 V00T0100
|
|
arc: C7 V02S0001
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 W1_H02E0201
|
|
arc: D5 H00L0100
|
|
arc: D6 N1_V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0100 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1101000000001101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0101010100001100
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1100110011000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R39C16:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A5 H02E0501
|
|
arc: A6 V02N0101
|
|
arc: A7 H00R0000
|
|
arc: B1 H02W0301
|
|
arc: B2 H02W0301
|
|
arc: B4 H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 N1_V01S0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 F4
|
|
arc: C6 V02N0001
|
|
arc: C7 H02E0401
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D6 V02N0401
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 Q5
|
|
arc: S1_V02S0401 F4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEC.K0.INIT 0000000000111111
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
word: SLICEB.K0.INIT 1010001001010001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000001010
|
|
word: SLICED.K1.INIT 1000000000100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010001001010001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R39C17:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A0 F7
|
|
arc: A1 V02N0701
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 V02S0101
|
|
arc: A5 V02S0301
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 V02N0501
|
|
arc: B7 H02E0301
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: C3 F4
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 V02N0201
|
|
arc: C7 E1_H02W0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0201
|
|
arc: D5 V02N0601
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F1
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 F7
|
|
arc: V01S0100 F5
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEC.K0.INIT 1011000000001011
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICED.K0.INIT 0011111100001100
|
|
word: SLICED.K1.INIT 1100000000001100
|
|
word: SLICEB.K0.INIT 0101111111111111
|
|
word: SLICEB.K1.INIT 0101111111111111
|
|
word: SLICEA.K0.INIT 0111111101111111
|
|
word: SLICEA.K1.INIT 0001010101010101
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R39C18:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: A6 H02W0501
|
|
arc: B6 V02N0501
|
|
arc: C6 W1_H02E0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 V02N0601
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M0 W1_H02E0601
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111100010001000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R39C19:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A5 H02E0501
|
|
arc: A6 H02E0701
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 H02W0301
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 H00L0100
|
|
arc: D6 H02E0001
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N3_V06N0303 Q6
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000100000000
|
|
word: SLICED.K0.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R39C20:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: A0 H02E0501
|
|
arc: A2 H02E0501
|
|
arc: B0 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 W1_H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0001
|
|
arc: D2 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: W1_H02W0001 Q2
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1110101011000000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1110101011000000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R39C21:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q6
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: V00B0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R39C22:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R39C23:PLC2
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0201
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R39C24:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R39C2:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0000 V02N0201
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H00R0000
|
|
arc: A4 N1_V01N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H02E0701
|
|
arc: B1 Q1
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 F6
|
|
arc: C4 Q4
|
|
arc: C5 V00B0100
|
|
arc: C6 V01N0101
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 F0
|
|
arc: D4 F0
|
|
arc: D5 H01W0000
|
|
arc: D6 F0
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F6
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000101011111010
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 0000000001010000
|
|
word: SLICEA.K1.INIT 0110000011101100
|
|
word: SLICED.K0.INIT 1010101100000000
|
|
word: SLICED.K1.INIT 0110000011101100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C3:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 H02E0501
|
|
arc: B6 H01E0101
|
|
arc: B7 H02E0301
|
|
arc: C6 V02N0001
|
|
arc: C7 H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 V02N0401
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0601 Q4
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0100 F7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0010001001101010
|
|
word: SLICED.K1.INIT 1000000000100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C4:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00T0000 H02E0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: A1 H02W0701
|
|
arc: A2 V02N0501
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0101
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B1 H02W0101
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 V02N0701
|
|
arc: B5 F3
|
|
arc: B6 H02E0101
|
|
arc: B7 E1_H02W0301
|
|
arc: C1 V02S0401
|
|
arc: C2 V02N0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 H02E0601
|
|
arc: C5 H02E0601
|
|
arc: C6 H01E0001
|
|
arc: C7 F6
|
|
arc: D1 V02N0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02W0201
|
|
arc: D4 V01N0001
|
|
arc: D5 H00L0100
|
|
arc: D6 V02S0601
|
|
arc: D7 S1_V02N0601
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H00R0000 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N3_V06N0103 F2
|
|
arc: S3_V06S0303 F5
|
|
word: SLICEC.K0.INIT 1000010000100001
|
|
word: SLICEC.K1.INIT 0100110000000000
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R39C5:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A3 F5
|
|
arc: A4 V02N0301
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V00T0000
|
|
arc: B3 F1
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0701
|
|
arc: B7 V02S0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02E0401
|
|
arc: C3 F4
|
|
arc: C4 V02S0201
|
|
arc: C5 V02S0001
|
|
arc: C6 V02N0001
|
|
arc: C7 F6
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 H02W0201
|
|
arc: D5 V02N0601
|
|
arc: D6 V00B0000
|
|
arc: D7 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F2
|
|
arc: M2 N1_V01N0001
|
|
arc: N1_V01N0001 F0
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0701 F7
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 0100000011000000
|
|
word: SLICEC.K0.INIT 1001000000000000
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 0111111111111111
|
|
word: SLICEA.K0.INIT 1001000000001001
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C6:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R39C7:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R39C8:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 H00R0000
|
|
arc: A6 V02N0301
|
|
arc: A7 H00R0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 V00B0000
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0401
|
|
arc: C6 H02W0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 F0
|
|
arc: D6 H00R0100
|
|
arc: D7 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0203 F7
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 F6
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 0000000001111111
|
|
word: SLICED.K0.INIT 0100111101111111
|
|
word: SLICED.K1.INIT 1011001100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C9:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 H02W0501
|
|
arc: A1 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H02W0701
|
|
arc: B0 V01N0001
|
|
arc: B1 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B6 S1_V02N0501
|
|
arc: C1 F6
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 H02W0601
|
|
arc: C6 V02N0001
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0001
|
|
arc: D1 F0
|
|
arc: D3 V00B0100
|
|
arc: D4 H00R0100
|
|
arc: D5 V00B0000
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02S0401
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 F4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICEA.K1.INIT 0000000001111111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
word: SLICED.K0.INIT 0000101000000011
|
|
word: SLICED.K1.INIT 1010000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R40C10:PLC2
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: B0 F1
|
|
arc: B2 F3
|
|
arc: B3 V02S0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V02S0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0101 Q3
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0101 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100110011000011
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
word: SLICEA.K0.INIT 0011000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R40C11:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 F7
|
|
arc: A7 N1_V01N0101
|
|
arc: B5 H00L0000
|
|
arc: B7 H02E0301
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 F4
|
|
arc: C7 V02S0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H02E0001
|
|
arc: D5 V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0601 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0100 F4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000101011111010
|
|
word: SLICEC.K1.INIT 1011000010111011
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R40C12:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A1 F5
|
|
arc: A3 V01N0101
|
|
arc: A6 H02E0501
|
|
arc: A7 Q7
|
|
arc: B1 V01N0001
|
|
arc: B3 V02N0101
|
|
arc: B6 H02E0101
|
|
arc: C1 H00L0100
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 V00B0100
|
|
arc: C6 V00T0100
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D5 V02N0601
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02W0601
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000100001100001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000111111110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000001000001
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICED.K1.INIT 0101101001011010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R40C13:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: E3_H06E0203 Q4
|
|
arc: F2 F5B_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0203 Q4
|
|
arc: W1_H02W0201 F2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0010001000101000
|
|
word: SLICEB.K1.INIT 1000100010000001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R40C14:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02E0001
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A7 V02N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 H01W0100
|
|
arc: B2 F3
|
|
arc: B3 V02S0101
|
|
arc: B7 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0601
|
|
arc: C3 S1_V02N0401
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0001
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F1
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000000001000000
|
|
word: SLICEA.K1.INIT 1111111000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0101010100010101
|
|
word: SLICEB.K0.INIT 0011001111111111
|
|
word: SLICEB.K1.INIT 0011000000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R40C15:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: A3 V02S0701
|
|
arc: A7 N1_V01N0101
|
|
arc: B3 V02S0101
|
|
arc: C6 H02W0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M0 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q3
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1010000011110101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000010001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R40C16:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A7 S1_V02N0301
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B7 V01S0000
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C7 N1_V02S0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000101001000101
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1001000010011001
|
|
word: SLICEB.K0.INIT 1000101001000101
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R40C17:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A1 V02S0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 V02S0301
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V01S0000
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: C3 F4
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 H02E0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0201
|
|
arc: D1 H01E0101
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H02E0001
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 Q6
|
|
word: SLICEB.K0.INIT 0011111111111111
|
|
word: SLICEB.K1.INIT 0011111111111111
|
|
word: SLICEA.K0.INIT 0011111111111111
|
|
word: SLICEA.K1.INIT 0000000001111111
|
|
word: SLICED.K0.INIT 1100110011001100
|
|
word: SLICED.K1.INIT 1000100011011101
|
|
word: SLICEC.K0.INIT 1010001001010001
|
|
word: SLICEC.K1.INIT 1000110000100011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R40C18:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A5 E1_H01W0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B5 N1_V01S0000
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C5 H02E0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D5 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0101 F1
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R40C19:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F2
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100001100
|
|
word: SLICEB.K1.INIT 0000000011000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R40C20:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R40C21:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R40C22:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00T0100 V02S0701
|
|
arc: CE1 V02S0201
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M2 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0601 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R40C24:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R40C2:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: V00B0000 V02N0001
|
|
arc: A0 H00L0100
|
|
arc: A1 S1_V02N0501
|
|
arc: A3 S1_V02N0501
|
|
arc: A5 V00T0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V00T0000
|
|
arc: B2 V02N0301
|
|
arc: B3 H01W0100
|
|
arc: B5 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02S0201
|
|
arc: C5 E1_H01E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D4 H01W0000
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q1
|
|
word: SLICEB.K0.INIT 1100110011111100
|
|
word: SLICEB.K1.INIT 0000011100001111
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0010101010101010
|
|
word: SLICEA.K1.INIT 1111010011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R40C3:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 H02E0301
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H02E0701
|
|
arc: A2 V02N0701
|
|
arc: A4 V00T0100
|
|
arc: A5 N1_V01N0101
|
|
arc: A7 V02S0101
|
|
arc: B0 V02S0301
|
|
arc: B1 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: B3 Q3
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H02E0101
|
|
arc: B7 V02S0501
|
|
arc: C0 V02S0601
|
|
arc: C1 H02E0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 F4
|
|
arc: C4 H02E0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H01E0101
|
|
arc: D1 F0
|
|
arc: D2 V00T0100
|
|
arc: D3 F2
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 H00L0100
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F4
|
|
arc: S1_V02S0701 Q5
|
|
word: SLICEC.K0.INIT 0111000000110000
|
|
word: SLICEC.K1.INIT 1111101111110011
|
|
word: SLICEA.K0.INIT 0100100000000000
|
|
word: SLICEA.K1.INIT 1111111100100000
|
|
word: SLICEB.K0.INIT 1111100011110000
|
|
word: SLICEB.K1.INIT 1111111100001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111100011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R40C4:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A1 V02S0501
|
|
arc: A3 V00T0000
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B3 V02S0101
|
|
arc: B6 V02N0501
|
|
arc: B7 V01S0000
|
|
arc: C1 V02S0401
|
|
arc: C3 F6
|
|
arc: C7 F6
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0003 Q3
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F6
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001000100010001
|
|
word: SLICED.K1.INIT 1110110001001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1110111100100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R40C5:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 H02E0701
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 H02E0101
|
|
arc: C4 V00T0000
|
|
arc: C5 F4
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H02E0701 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 0100000011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R40C6:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A2 V01N0101
|
|
arc: A3 H02W0701
|
|
arc: A5 V02S0101
|
|
arc: A7 H02W0501
|
|
arc: B2 H00R0000
|
|
arc: B3 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: B7 V01S0000
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0000
|
|
arc: C5 V00T0100
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 N1_V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 H02E0001
|
|
arc: D3 V02N0201
|
|
arc: D5 V02N0401
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H02E0701 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0601 F6
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
word: SLICEB.K0.INIT 0000011101110111
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0001001101011111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R40C7:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A3 N1_V02S0501
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 W1_H02E0701
|
|
arc: B3 V01N0001
|
|
arc: B6 V01S0000
|
|
arc: B7 V00B0000
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 V02S0201
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 F6
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 F2
|
|
arc: D6 H02W0201
|
|
arc: D7 H00R0100
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0203 Q4
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 1010101011111111
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 0101010100000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R40C8:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A3 E1_H02W0501
|
|
arc: B3 V01N0001
|
|
arc: C2 H02E0601
|
|
arc: C3 N1_V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 H00R0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F3
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 0001010100111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R40C9:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: A0 H02W0701
|
|
arc: A1 H02E0701
|
|
arc: A7 Q7
|
|
arc: B0 V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0000
|
|
arc: C0 V02S0401
|
|
arc: C1 H00L0100
|
|
arc: C6 V02N0201
|
|
arc: C7 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00T0100
|
|
arc: D1 F0
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 F6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000110011111100
|
|
word: SLICED.K1.INIT 1010100110101010
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0000000011110100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R41C10:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A1 V02N0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 N1_V01N0101
|
|
arc: A7 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B2 V02S0101
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0701
|
|
arc: B7 H01E0101
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 H00L0000
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 N1_V02S0201
|
|
arc: C7 H02E0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H01E0101
|
|
arc: D2 Q2
|
|
arc: D3 H02E0001
|
|
arc: D4 V02S0601
|
|
arc: D5 V02S0401
|
|
arc: D7 V01N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 F0
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K0.INIT 0011001111001100
|
|
word: SLICEB.K1.INIT 1111000000001111
|
|
word: SLICEC.K0.INIT 0100010001001000
|
|
word: SLICEC.K1.INIT 1000100010000001
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001010010000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0010000000010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R41C11:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01N0101
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V00B0100
|
|
arc: C5 V00T0100
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 H00R0100
|
|
arc: D5 H00L0100
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R41C12:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A0 F7
|
|
arc: A1 V02S0701
|
|
arc: A3 H02E0701
|
|
arc: A5 Q5
|
|
arc: A6 F7
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 F3
|
|
arc: B5 F3
|
|
arc: B7 V02S0701
|
|
arc: C0 H00L0100
|
|
arc: C1 V02N0401
|
|
arc: C2 H00R0100
|
|
arc: C3 H02W0601
|
|
arc: C4 Q4
|
|
arc: C6 V00T0100
|
|
arc: C7 H02W0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 F2
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 H02W0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F4
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0000000001000000
|
|
word: SLICEC.K0.INIT 0011110000111100
|
|
word: SLICEC.K1.INIT 0110011010101010
|
|
word: SLICEA.K0.INIT 0111000110001110
|
|
word: SLICEA.K1.INIT 0110110011001100
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICED.K1.INIT 0010000011110010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R41C13:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A3 H02E0701
|
|
arc: A5 V02S0101
|
|
arc: A6 H00L0000
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 F4
|
|
arc: C3 H00R0100
|
|
arc: C5 F4
|
|
arc: C6 Q6
|
|
arc: C7 S1_V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 Q2
|
|
arc: D3 H02E0001
|
|
arc: D4 V02S0601
|
|
arc: D6 V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0701 F7
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0111111111111111
|
|
word: SLICEC.K0.INIT 0000000000110011
|
|
word: SLICEC.K1.INIT 0101101001011010
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0101101000001111
|
|
word: SLICED.K0.INIT 1111000011010010
|
|
word: SLICED.K1.INIT 1111000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R41C14:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A2 S1_V02N0701
|
|
arc: A4 V00B0000
|
|
arc: A6 N1_V01S0100
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B7 V00T0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C4 H02W0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 V00T0100
|
|
arc: D2 V01S0100
|
|
arc: D3 V02N0001
|
|
arc: D4 F0
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 F1
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0601 F4
|
|
arc: V00B0000 Q6
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F3
|
|
word: SLICEC.K0.INIT 0000100011111111
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111000011100000
|
|
word: SLICEB.K1.INIT 0011001100110000
|
|
word: SLICED.K0.INIT 1010101000000000
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEA.K0.INIT 0000000001000000
|
|
word: SLICEA.K1.INIT 1010101000100010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R41C15:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A0 H02E0701
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 H00R0000
|
|
arc: B0 F1
|
|
arc: B5 E1_H02W0301
|
|
arc: C1 E1_H01W0000
|
|
arc: C5 H01E0001
|
|
arc: C7 V02S0001
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D1 V00B0100
|
|
arc: D5 H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F4
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F4
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1010101010101010
|
|
word: SLICED.K1.INIT 1010000010101111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000001000000000
|
|
word: SLICEA.K0.INIT 0111011111111111
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R41C16:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 F7
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V02S0301
|
|
arc: B0 V02N0101
|
|
arc: B3 N1_V02S0301
|
|
arc: B5 V02N0501
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V00B0000
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 H00L0000
|
|
arc: C4 S1_V02N0001
|
|
arc: C6 E1_H01E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 E1_H02W0001
|
|
arc: D3 V00T0100
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 N1_V02S0401
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 F7
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0010000000100000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0000000011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0100010011111111
|
|
word: SLICEC.K0.INIT 0000111111111111
|
|
word: SLICEC.K1.INIT 0010001000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R41C17:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A4 V02N0301
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 V02S0101
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H02E0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C1 S1_V02N0601
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 E1_H02W0401
|
|
arc: C7 V02N0001
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H02W0201
|
|
arc: D5 V01N0001
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 E1_H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F5
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: N1_V02N0301 F1
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0000 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K0.INIT 0111011111111111
|
|
word: SLICEB.K1.INIT 0111011111111111
|
|
word: SLICEA.K0.INIT 0111011111111111
|
|
word: SLICEA.K1.INIT 0000011100001111
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICED.K0.INIT 0101010100000000
|
|
word: SLICED.K1.INIT 1011000000001011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R41C18:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 F5
|
|
arc: A3 F5
|
|
arc: A5 V00T0000
|
|
arc: A6 V02N0101
|
|
arc: A7 W1_H02E0501
|
|
arc: B1 H02W0101
|
|
arc: B5 V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V02S0501
|
|
arc: C0 F6
|
|
arc: C1 F6
|
|
arc: C2 F6
|
|
arc: C3 F6
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V00T0100
|
|
arc: C6 V02N0001
|
|
arc: C7 S1_V02N0001
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 H00R0100
|
|
arc: D5 V01N0001
|
|
arc: D6 V02N0401
|
|
arc: D7 E1_H01W0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: N3_V06N0203 F4
|
|
arc: V00B0100 F7
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 0101111111111111
|
|
word: SLICEA.K1.INIT 0000000001111111
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICEC.K1.INIT 1000001000000000
|
|
word: SLICEB.K0.INIT 0101111111111111
|
|
word: SLICEB.K1.INIT 0101111111111111
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICED.K1.INIT 1000000000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R41C19:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A3 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: B3 V01N0001
|
|
arc: C3 W1_H02E0401
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V02S0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q6
|
|
arc: M0 H02E0601
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0401 Q6
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R41C20:PLC2
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: B7 W1_H02E0301
|
|
arc: C7 V02S0201
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 F7
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000110000001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R41C21:PLC2
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
|
|
.tile R41C22:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
|
|
.tile R41C23:PLC2
|
|
arc: A1 F5
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V02N0101
|
|
arc: A7 F5
|
|
arc: B4 V00B0100
|
|
arc: B5 S1_V02N0701
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 F4
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q1
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111111110101010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0101010100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R41C24:PLC2
|
|
arc: A1 H02E0701
|
|
arc: A5 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D5 V01N0001
|
|
arc: D7 S1_V02N0601
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0101010100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0101010100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0101010100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R41C25:PLC2
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 W1_H02E0701
|
|
arc: B1 V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: C2 H00L0100
|
|
arc: C5 V01N0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V01S0100
|
|
arc: D3 V02N0001
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0100010001000100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R41C2:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: V00T0000 H02W0201
|
|
arc: A0 V02N0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02W0701
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 Q7
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 F3
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 F3
|
|
arc: B5 F3
|
|
arc: B7 F3
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0401
|
|
arc: C4 Q4
|
|
arc: C5 V00B0100
|
|
arc: C7 F6
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 Q0
|
|
arc: D1 V02S0201
|
|
arc: D2 H00R0000
|
|
arc: D3 V02N0001
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 F6
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1011111110000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 1111110011111100
|
|
word: SLICEC.K1.INIT 1100110011111110
|
|
word: SLICED.K0.INIT 0000000010101010
|
|
word: SLICED.K1.INIT 0001001000000010
|
|
word: SLICEB.K0.INIT 0010000100110000
|
|
word: SLICEB.K1.INIT 0000000000001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R41C3:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A7 V02N0101
|
|
arc: C1 V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0001
|
|
arc: D7 H02E0001
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000010101010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R41C4:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: A0 V02S0501
|
|
arc: A1 V02N0501
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 Q7
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 N1_V02S0101
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C1 H02E0601
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H00L0000
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 F6
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 F0
|
|
arc: D2 V00T0100
|
|
arc: D3 V01S0100
|
|
arc: D5 F0
|
|
arc: D6 H00R0100
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 1010101000000000
|
|
word: SLICED.K1.INIT 1010101011001010
|
|
word: SLICEA.K0.INIT 0000000010101010
|
|
word: SLICEA.K1.INIT 1011100011110000
|
|
word: SLICEB.K0.INIT 1111001011010000
|
|
word: SLICEB.K1.INIT 1111011110000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1110010011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R41C5:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: A5 H02W0701
|
|
arc: A6 H02E0701
|
|
arc: A7 F5
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V01S0000
|
|
arc: B7 V01S0000
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0201
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 V02N0401
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICED.K1.INIT 0010000010100000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0001001101011111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R41C6:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 V01N0101
|
|
arc: A3 H02W0501
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 H02W0501
|
|
arc: A7 F5
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 H02E0401
|
|
arc: C7 F6
|
|
arc: D0 F2
|
|
arc: D1 F2
|
|
arc: D2 H02E0201
|
|
arc: D3 V02S0001
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V00B0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0100
|
|
arc: V01S0000 F7
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 0010000010100000
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEB.K1.INIT 0001001101011111
|
|
word: SLICEA.K0.INIT 0000000000001001
|
|
word: SLICEA.K1.INIT 0000000010010000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000011101110111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R41C7:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R41C8:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A4 V02N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H00R0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 V02S0001
|
|
arc: CE3 V02N0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 H02W0201
|
|
arc: D3 H02W0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 W1_H02E0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N3_V06N0103 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R41C9:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H00L0000
|
|
arc: A2 V01N0101
|
|
arc: A3 E1_H01E0001
|
|
arc: A5 V02N0301
|
|
arc: A6 H00L0000
|
|
arc: A7 H00R0000
|
|
arc: B1 V01N0001
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0000
|
|
arc: B5 H00R0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V01S0000
|
|
arc: C0 V02S0601
|
|
arc: C1 H00L0000
|
|
arc: C2 H00R0100
|
|
arc: C3 V02N0401
|
|
arc: C4 Q4
|
|
arc: C5 V02N0001
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 V00B0000
|
|
arc: D5 F2
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0303 F5
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEB.K0.INIT 0101000011010100
|
|
word: SLICEB.K1.INIT 1001011000000000
|
|
word: SLICEA.K0.INIT 1010101010100101
|
|
word: SLICEA.K1.INIT 0011001111000011
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 1001101001011001
|
|
word: SLICED.K0.INIT 0000001000000000
|
|
word: SLICED.K1.INIT 0110110001101100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R42C10:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: A4 V00T0000
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 N1_V02S0301
|
|
arc: B4 V02N0501
|
|
arc: B5 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
arc: C4 H02W0401
|
|
arc: C5 F4
|
|
arc: C7 H02E0401
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02N0401
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 H00R0100
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0501 Q7
|
|
arc: V00T0000 Q2
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 0011000111110101
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0111111110000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R42C11:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0101
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 H02W0301
|
|
arc: B5 H00L0000
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: C2 V02S0601
|
|
arc: C3 V02S0601
|
|
arc: C4 H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D4 H00R0100
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXCLK3 CLK1
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R42C12:PLC2
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H01E0001
|
|
arc: A1 V01N0101
|
|
arc: A2 V02N0701
|
|
arc: A3 V02S0501
|
|
arc: A4 H02E0501
|
|
arc: A5 V02N0301
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0100
|
|
arc: B3 V01N0001
|
|
arc: B4 V00B0100
|
|
arc: B5 V00B0100
|
|
arc: B6 V02N0501
|
|
arc: C0 H00R0100
|
|
arc: C1 F6
|
|
arc: C2 H02E0601
|
|
arc: C3 F4
|
|
arc: C4 V02S0201
|
|
arc: C5 V02N0001
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 F0
|
|
arc: D2 V00B0100
|
|
arc: D3 F2
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: D6 H02E0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F1
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q7
|
|
word: SLICEC.K0.INIT 1111111100011101
|
|
word: SLICEC.K1.INIT 0100011001001100
|
|
word: SLICED.K0.INIT 1100010011001100
|
|
word: SLICED.K1.INIT 0101010100001010
|
|
word: SLICEA.K0.INIT 0011111101011111
|
|
word: SLICEA.K1.INIT 0111000000000000
|
|
word: SLICEB.K0.INIT 0101010100010101
|
|
word: SLICEB.K1.INIT 0111000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R42C13:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: A3 V02S0701
|
|
arc: B3 Q3
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V00B0100
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q3
|
|
arc: V01S0000 Q3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R42C14:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0100 V02S0301
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: A1 F5
|
|
arc: A3 V02N0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0101
|
|
arc: A6 N1_V02S0101
|
|
arc: B1 V02S0101
|
|
arc: B2 F3
|
|
arc: B4 H02W0101
|
|
arc: B5 H02W0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C6 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V01S0100
|
|
arc: D3 H02W0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0100 F3
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0201 F2
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K0.INIT 1110101110111110
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000001100000011
|
|
word: SLICEB.K1.INIT 1010000000000000
|
|
word: SLICEC.K0.INIT 0000111101011011
|
|
word: SLICEC.K1.INIT 0000000000010001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000001100001110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R42C15:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 N1_V01S0100
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: C4 V02N0001
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0001
|
|
arc: D7 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 0000010100000000
|
|
word: SLICED.K1.INIT 1111101011111111
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 0000000011000000
|
|
word: SLICEC.K1.INIT 1111111100111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R42C16:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A3 V00T0000
|
|
arc: A7 H00L0000
|
|
arc: B1 H01W0100
|
|
arc: B7 V00B0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 V02S0401
|
|
arc: C3 V02N0401
|
|
arc: C7 V00T0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02S0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H00R0000
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 F7
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1010101000001111
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 1100000011001111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000001011000011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R42C17:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: A1 V02S0701
|
|
arc: A2 V00B0000
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V02N0301
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H01W0100
|
|
arc: B7 V02S0501
|
|
arc: C1 H02W0401
|
|
arc: C2 V02S0401
|
|
arc: C7 H02E0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D6 V02N0401
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H01E0001
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0601 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1010111100100011
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1101110100001101
|
|
word: SLICED.K0.INIT 1010101001010101
|
|
word: SLICED.K1.INIT 1000000000100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R42C18:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A1 V02S0501
|
|
arc: B1 V00B0000
|
|
arc: C1 E1_H01W0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000010010100101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R42C19:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0401 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R42C20:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
|
|
.tile R42C21:PLC2
|
|
arc: N1_V02N0301 H02E0301
|
|
|
|
.tile R42C22:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: H00R0100 H02W0501
|
|
arc: V00B0100 V02N0301
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: A1 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A4 N1_V01N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B4 V01S0000
|
|
arc: B5 E1_H02W0301
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V00T0100
|
|
arc: C7 E1_H02W0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 H01W0000
|
|
arc: D5 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0701 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q5
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 1111111111001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111111111110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0100010001000100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0101000001010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R42C23:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F6
|
|
arc: V01S0000 F7
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R42C24:PLC2
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: A1 V02S0701
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B2 V01N0001
|
|
arc: B6 V00B0000
|
|
arc: B7 N1_V01S0000
|
|
arc: E1_H01E0001 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V02N0001 F0
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R42C25:PLC2
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0101
|
|
arc: B5 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0001 F0
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F4
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R42C2:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R42C3:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0000 V02S0201
|
|
arc: A3 V02N0501
|
|
arc: A4 V02N0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 V00B0000
|
|
arc: B2 V01N0001
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 N1_V01S0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F3
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R42C4:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: A0 H02E0501
|
|
arc: A6 V02N0301
|
|
arc: A7 H02E0701
|
|
arc: B6 H02E0101
|
|
arc: B7 H02E0301
|
|
arc: C6 H02E0401
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 H02E0001
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 0000000000100000
|
|
word: SLICED.K1.INIT 1010101010100010
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R42C5:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A1 H02W0501
|
|
arc: A7 H02W0501
|
|
arc: C1 N1_V01S0100
|
|
arc: C7 H02E0601
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V02N0001
|
|
arc: D7 V00B0000
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000111110101111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000101011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R42C6:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: B7 V02N0501
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V02S0601
|
|
arc: C7 H02W0401
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D7 H00R0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0011001111110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R42C7:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A6 V02N0301
|
|
arc: A7 N1_V01N0101
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0100
|
|
arc: C6 V02N0201
|
|
arc: C7 F6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D6 V01N0001
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 0000000110101011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R42C8:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0701
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 V00T0100
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 H01E0101
|
|
arc: B7 V00B0000
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: C4 H02W0401
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 V02N0201
|
|
arc: C7 E1_H02W0401
|
|
arc: CLK1 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H02E0001
|
|
arc: D6 V02N0601
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0203 F7
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00B0000 F6
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 0100110001011111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R42C9:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0301
|
|
arc: B5 N1_V02S0501
|
|
arc: C1 H00L0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02S0001
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02S0001
|
|
arc: D3 V02S0001
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0701 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0301 F1
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0111111111111111
|
|
word: SLICEC.K0.INIT 0011111111000000
|
|
word: SLICEC.K1.INIT 1100110000110011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000111111110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R43C10:PLC2
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R43C11:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R43C12:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A1 H00L0100
|
|
arc: A3 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 N1_V01S0100
|
|
arc: B0 V01N0001
|
|
arc: B1 V02S0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 H00L0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H00R0100
|
|
arc: C5 F6
|
|
arc: C7 H02W0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 F0
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 F2
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0100 Q5
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0501 Q5
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
word: SLICED.K0.INIT 1000100010001000
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 1010001010101010
|
|
word: SLICEA.K0.INIT 0000111100001100
|
|
word: SLICEA.K1.INIT 0000000000011111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0001001010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R43C13:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: A0 H02E0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V00T0100
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B3 Q3
|
|
arc: B4 V00B0100
|
|
arc: B5 V00B0100
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 F4
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 F4
|
|
arc: C6 F4
|
|
arc: C7 V02S0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H02E0001
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0001
|
|
arc: D6 V00B0000
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F4
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0401 F4
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEB.K0.INIT 0101101010101010
|
|
word: SLICEB.K1.INIT 0110100011001100
|
|
word: SLICEC.K0.INIT 0000001000000000
|
|
word: SLICEC.K1.INIT 0000001100001100
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1101010111000000
|
|
word: SLICED.K1.INIT 0000000000000111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R43C14:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0000 Q1
|
|
word: SLICEB.K0.INIT 1100001111001100
|
|
word: SLICEB.K1.INIT 1100110000111100
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R43C15:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B3 Q3
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 N1_V02S0401
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 V02S0001
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEB.K0.INIT 1010010101011010
|
|
word: SLICEB.K1.INIT 1100100101101100
|
|
word: SLICEA.K0.INIT 1100110010011100
|
|
word: SLICEA.K1.INIT 1100011011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R43C16:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R43C17:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: A5 H02E0501
|
|
arc: B4 H02E0101
|
|
arc: C4 V00T0000
|
|
arc: C5 H02W0601
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02N0601
|
|
arc: D5 S1_V02N0601
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R43C18:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: CE1 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R43C19:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
|
|
.tile R43C22:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R43C23:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: C5 V02S0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 H00R0100
|
|
arc: E1_H02E0701 Q5
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R43C24:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0501
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: A3 V02S0701
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V01S0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 V00T0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 F4
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q3
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0101010100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R43C25:PLC2
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A3 N1_V02S0501
|
|
arc: B5 N1_V02S0701
|
|
arc: B7 N1_V02S0701
|
|
arc: C1 N1_V01S0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D1 V00T0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 V02S0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0011001100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0011001100000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R43C26:PLC2
|
|
arc: W1_H02W0601 H01E0001
|
|
|
|
.tile R43C2:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0401 Q4
|
|
arc: M4 V00B0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R43C3:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00B0000 V02S0201
|
|
arc: A0 V02S0501
|
|
arc: A1 N1_V02S0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B1 V00T0000
|
|
arc: B5 H00R0000
|
|
arc: C1 H00L0100
|
|
arc: C5 N1_V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02N0001
|
|
arc: D1 V00B0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V00B0000
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 F5
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000010101010
|
|
word: SLICEA.K1.INIT 0000000000000010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000010101010
|
|
word: SLICEC.K0.INIT 0101010100000000
|
|
word: SLICEC.K1.INIT 1011101010111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R43C4:PLC2
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 V02N0301
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B6 V01S0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R43C5:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0701
|
|
arc: B4 H02E0301
|
|
arc: C4 H02E0401
|
|
arc: C5 F4
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0701 F5
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 Q5
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 0101111111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R43C6:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: V00B0000 V02S0001
|
|
arc: A0 H01E0001
|
|
arc: A1 H02E0501
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 H02E0401
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 V02S0201
|
|
arc: D1 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 F0
|
|
arc: V01S0000 F1
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R43C7:PLC2
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R43C8:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V02N0101
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H00L0000
|
|
arc: B6 V01S0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C4 V00T0000
|
|
arc: C5 F4
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D4 V02N0601
|
|
arc: D5 V02S0401
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V00B0000
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: V00B0000 F6
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICED.K1.INIT 0011111100010101
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
word: SLICEC.K1.INIT 0011000111110101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R43C9:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE ASYNC
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R44C10:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: CLK0 G_HPBX0100
|
|
arc: M0 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R44C11:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R44C12:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0701
|
|
arc: A5 Q5
|
|
arc: A6 H02E0701
|
|
arc: A7 Q7
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B7 V02S0701
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 F6
|
|
arc: C6 H02W0601
|
|
arc: C7 F6
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D2 V00T0100
|
|
arc: D3 F2
|
|
arc: D5 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: D7 F2
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q5
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000010101010
|
|
word: SLICEB.K0.INIT 0000000010111111
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000010100000000
|
|
word: SLICED.K1.INIT 0010001011110010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R44C13:PLC2
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0701
|
|
arc: B0 F1
|
|
arc: C0 V02S0401
|
|
arc: C1 H00L0000
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D0 Q0
|
|
arc: D1 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0103 F1
|
|
word: SLICEA.K0.INIT 0100111100010000
|
|
word: SLICEA.K1.INIT 0000000001011111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R44C14:PLC2
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R44C16:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
|
|
.tile R44C17:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R44C18:PLC2
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R44C2:PLC2
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: B5 V01S0000
|
|
arc: C5 V02N0201
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D5 H01W0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0501 Q5
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: M2 H02E0601
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0303 Q5
|
|
arc: V01S0000 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R44C3:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: A3 H02E0501
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0100
|
|
arc: D3 V00T0100
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0101 Q3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R44C4:PLC2
|
|
arc: N1_V02N0301 H02E0301
|
|
|
|
.tile R44C5:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: W1_H02W0001 V06S0003
|
|
|
|
.tile R44C6:PLC2
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R44C7:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R44C8:PLC2
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R44C9:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R45C10:PLC2
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R45C12:PLC2
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
|
|
.tile R45C13:PLC2
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R45C16:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R45C17:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R45C18:PLC2
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R45C2:PLC2
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02E0701
|
|
arc: CLK0 G_HPBX0100
|
|
arc: LSR0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0201 Q2
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE ASYNC
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R45C8:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
|
|
.tile R45C9:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
|
|
.tile R46C11:PLC2
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R46C2:PLC2
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
|
|
.tile TAP_R15C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R16C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R16C4:TAP_DRIVE
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R17C22:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C4:TAP_DRIVE
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R18C22:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C4:TAP_DRIVE
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R19C22:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C4:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R20C22:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C4:TAP_DRIVE
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R21C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R22C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R22C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R23C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R23C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R24C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R24C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R25C4:TAP_DRIVE_CIB
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R26C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R26C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R27C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R27C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R28C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R28C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R29C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R29C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R30C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R30C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R31C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R31C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R32C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R32C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R33C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R33C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R34C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R34C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R35C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R35C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R36C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R36C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R38C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R38C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R39C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R39C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R40C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R40C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R41C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R41C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R42C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R42C4:TAP_DRIVE
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R43C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R43C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R44C22:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R44C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
arc: R_HPBX0100 G_VPTX0100
|
|
|
|
.tile TAP_R45C4:TAP_DRIVE
|
|
arc: L_HPBX0100 G_VPTX0100
|
|
|
|
.bram_init 3
|
|
000 000 000 000 000 000 000 000
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
|
|
.bram_init 4
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
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000 000 000 000 000 000 000 000
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000 000 000 000 000 000 000 000
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word: EBR2.WID 101000000
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enum: EBR2.REGMODE_A NOREG
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enum: EBR2.REGMODE_B NOREG
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enum: EBR2.RESETMODE SYNC
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enum: EBR2.ASYNC_RESET_RELEASE SYNC
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enum: EBR2.GSR DISABLED
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enum: EBR2.CLKAMUX CLKA
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enum: EBR2.CLKBMUX CLKB
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enum: EBR2.RSTAMUX INV
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enum: EBR2.RSTBMUX INV
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enum: EBR2.WEAMUX WEA
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enum: EBR2.WEBMUX INV
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enum: EBR2.CEAMUX CEA
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enum: EBR2.CEBMUX CEB
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enum: EBR2.OCEAMUX OCEA
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enum: EBR2.OCEBMUX OCEB
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.tile_group MIB_R25C10:MIB_EBR6 MIB_R25C11:MIB_EBR7 MIB_R25C12:MIB_EBR8
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enum: EBR3.DP16KD.DATA_WIDTH_B 9
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enum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE
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enum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE
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enum: EBR3.REGMODE_A NOREG
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enum: EBR3.REGMODE_B NOREG
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enum: EBR3.RESETMODE SYNC
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enum: EBR3.ASYNC_RESET_RELEASE SYNC
|
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enum: EBR3.GSR DISABLED
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|
enum: EBR3.CLKAMUX CLKA
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|
enum: EBR3.CLKBMUX CLKB
|
|
enum: EBR3.RSTAMUX INV
|
|
enum: EBR3.RSTBMUX INV
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enum: EBR3.WEAMUX WEA
|
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enum: EBR3.WEBMUX INV
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enum: EBR3.CEAMUX CEA
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enum: EBR3.CEBMUX CEB
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enum: EBR3.OCEAMUX OCEA
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enum: EBR3.OCEBMUX OCEB
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|
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.tile_group MIB_R25C6:MIB_EBR2 MIB_R25C7:MIB_EBR3 MIB_R25C8:MIB_EBR4
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enum: EBR1.DP16KD.DATA_WIDTH_B 9
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enum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE
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enum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE
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enum: EBR1.REGMODE_A NOREG
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enum: EBR1.REGMODE_B NOREG
|
|
enum: EBR1.RESETMODE SYNC
|
|
enum: EBR1.ASYNC_RESET_RELEASE SYNC
|
|
enum: EBR1.GSR DISABLED
|
|
enum: EBR1.CLKAMUX CLKA
|
|
enum: EBR1.CLKBMUX CLKB
|
|
enum: EBR1.RSTAMUX INV
|
|
enum: EBR1.RSTBMUX INV
|
|
enum: EBR1.WEAMUX WEA
|
|
enum: EBR1.WEBMUX INV
|
|
enum: EBR1.CEAMUX CEA
|
|
enum: EBR1.CEBMUX CEB
|
|
enum: EBR1.OCEAMUX OCEA
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|
enum: EBR1.OCEBMUX OCEB
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|
|
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.tile_group MIB_R25C4:MIB_EBR0 MIB_R25C5:MIB_EBR1
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word: EBR0.WID 110000000
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word: EBR0.CSDECODE_A 111
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word: EBR0.CSDECODE_B 111
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enum: EBR0.MODE DP16KD
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enum: EBR0.DP16KD.DATA_WIDTH_A 9
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enum: EBR0.DP16KD.DATA_WIDTH_B 9
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enum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE
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enum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE
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enum: EBR0.REGMODE_A NOREG
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enum: EBR0.REGMODE_B NOREG
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enum: EBR0.RESETMODE SYNC
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enum: EBR0.ASYNC_RESET_RELEASE SYNC
|
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enum: EBR0.GSR DISABLED
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enum: EBR0.CLKAMUX CLKA
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enum: EBR0.CLKBMUX CLKB
|
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enum: EBR0.RSTAMUX INV
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enum: EBR0.RSTBMUX INV
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enum: EBR0.WEAMUX WEA
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enum: EBR0.WEBMUX INV
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enum: EBR0.CEAMUX CEA
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enum: EBR0.CEBMUX CEB
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enum: EBR0.OCEAMUX OCEA
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enum: EBR0.OCEBMUX OCEB
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|
|