0dacc978da
not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation. |
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| .. | ||
| exu.sv | ||
| exu_alu_ctl.sv | ||
| exu_div_ctl.sv | ||
| exu_mul_ctl.sv | ||