Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues.		2019-10-15 13:14:36 -07:00
..
cdecode	SweRV 1.1	2019-06-04 07:57:48 -07:00
csrdecode	SweRV 1.1	2019-06-04 07:57:48 -07:00
dec.sv	Untabified files.	2019-08-13 12:48:48 -07:00
dec_decode_ctl.sv	Move declarations to top of Verilog file to fix fpga compile issues.	2019-10-15 13:14:36 -07:00
dec_gpr_ctl.sv	Untabified files.	2019-08-13 12:48:48 -07:00
dec_ib_ctl.sv	Untabified files.	2019-08-13 12:48:48 -07:00
dec_tlu_ctl.sv	Untabified files.	2019-08-13 12:48:48 -07:00
dec_trigger.sv	Untabified files.	2019-08-13 12:48:48 -07:00
decode	SweRV 1.1	2019-06-04 07:57:48 -07:00