Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues.		2019-10-15 13:14:36 -07:00
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dbg	Untabified files.	2019-08-13 12:48:48 -07:00
dec	Move declarations to top of Verilog file to fix fpga compile issues.	2019-10-15 13:14:36 -07:00
dmi	Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does	2019-08-07 17:04:48 -07:00
exu	Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does	2019-08-07 17:04:48 -07:00
ifu	Untabified files.	2019-08-13 12:48:48 -07:00
include	Untabified files.	2019-08-13 12:48:48 -07:00
lib	Change clock header instance name in beh_lib.sv	2019-09-04 14:39:10 -07:00
lsu	Untabified files.	2019-08-13 12:48:48 -07:00
dma_ctrl.sv	Untabified files.	2019-08-13 12:48:48 -07:00
mem.sv	Untabified files.	2019-08-13 12:48:48 -07:00
pic_ctrl.sv	Untabified files.	2019-08-13 12:48:48 -07:00
swerv.sv	Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.	2019-09-04 13:29:39 -07:00
swerv_wrapper.sv	Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.	2019-09-04 13:29:39 -07:00